Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7852937 |
1 |
|
|
T29 |
174 |
|
T30 |
26 |
|
T31 |
300 |
| auto[1] |
5819155 |
1 |
|
|
T30 |
31 |
|
T32 |
31 |
|
T19 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12933209 |
1 |
|
|
T29 |
174 |
|
T30 |
55 |
|
T31 |
300 |
| auto[1] |
738883 |
1 |
|
|
T30 |
2 |
|
T32 |
3 |
|
T19 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7855819 |
1 |
|
|
T29 |
174 |
|
T30 |
21 |
|
T31 |
300 |
| auto[1] |
5816273 |
1 |
|
|
T30 |
36 |
|
T32 |
25 |
|
T19 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2538345 |
1 |
|
|
T30 |
11 |
|
T32 |
14 |
|
T19 |
30 |
| auto[1] |
auto[0] |
auto[1] |
368815 |
1 |
|
|
T32 |
1 |
|
T19 |
2 |
|
T21 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2539045 |
1 |
|
|
T30 |
23 |
|
T32 |
8 |
|
T21 |
40 |
| auto[1] |
auto[1] |
auto[1] |
370068 |
1 |
|
|
T30 |
2 |
|
T32 |
2 |
|
T21 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |