Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7921131 |
1 |
|
|
T29 |
174 |
|
T30 |
57 |
|
T31 |
300 |
| auto[1] |
5750961 |
1 |
|
|
T32 |
48 |
|
T19 |
10 |
|
T21 |
149 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12933213 |
1 |
|
|
T29 |
174 |
|
T30 |
55 |
|
T31 |
300 |
| auto[1] |
738879 |
1 |
|
|
T30 |
2 |
|
T32 |
1 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7855656 |
1 |
|
|
T29 |
174 |
|
T30 |
24 |
|
T31 |
300 |
| auto[1] |
5816436 |
1 |
|
|
T30 |
33 |
|
T32 |
36 |
|
T19 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2562349 |
1 |
|
|
T30 |
31 |
|
T32 |
17 |
|
T19 |
14 |
| auto[1] |
auto[0] |
auto[1] |
373090 |
1 |
|
|
T30 |
2 |
|
T19 |
1 |
|
T21 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2515208 |
1 |
|
|
T32 |
18 |
|
T21 |
81 |
|
T116 |
447 |
| auto[1] |
auto[1] |
auto[1] |
365789 |
1 |
|
|
T32 |
1 |
|
T21 |
7 |
|
T116 |
120 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |