Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889174 |
1 |
|
|
T29 |
174 |
|
T30 |
40 |
|
T31 |
300 |
| auto[1] |
5782918 |
1 |
|
|
T30 |
17 |
|
T32 |
43 |
|
T19 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12939245 |
1 |
|
|
T29 |
174 |
|
T30 |
55 |
|
T31 |
300 |
| auto[1] |
732847 |
1 |
|
|
T30 |
2 |
|
T21 |
5 |
|
T116 |
202 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7892483 |
1 |
|
|
T29 |
174 |
|
T30 |
32 |
|
T31 |
300 |
| auto[1] |
5779609 |
1 |
|
|
T30 |
25 |
|
T32 |
36 |
|
T19 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2542265 |
1 |
|
|
T30 |
23 |
|
T32 |
17 |
|
T19 |
3 |
| auto[1] |
auto[0] |
auto[1] |
369719 |
1 |
|
|
T30 |
2 |
|
T21 |
4 |
|
T116 |
100 |
| auto[1] |
auto[1] |
auto[0] |
2504497 |
1 |
|
|
T32 |
19 |
|
T19 |
6 |
|
T21 |
24 |
| auto[1] |
auto[1] |
auto[1] |
363128 |
1 |
|
|
T21 |
1 |
|
T116 |
102 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |