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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 943
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T109 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1232576490 Jul 17 06:54:22 PM PDT 24 Jul 17 06:54:25 PM PDT 24 29032424 ps
T51 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1725239465 Jul 17 06:54:12 PM PDT 24 Jul 17 06:54:13 PM PDT 24 153191618 ps
T764 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4294423391 Jul 17 06:54:24 PM PDT 24 Jul 17 06:54:26 PM PDT 24 23998434 ps
T765 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1558250472 Jul 17 06:54:19 PM PDT 24 Jul 17 06:54:22 PM PDT 24 29656628 ps
T766 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1901113933 Jul 17 06:54:05 PM PDT 24 Jul 17 06:54:09 PM PDT 24 59654110 ps
T767 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.178602032 Jul 17 06:54:19 PM PDT 24 Jul 17 06:54:22 PM PDT 24 199019408 ps
T768 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3015326561 Jul 17 06:54:04 PM PDT 24 Jul 17 06:54:06 PM PDT 24 19303983 ps
T769 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1376864789 Jul 17 06:54:59 PM PDT 24 Jul 17 06:55:03 PM PDT 24 28605362 ps
T770 /workspace/coverage/cover_reg_top/21.gpio_intr_test.960051262 Jul 17 06:54:58 PM PDT 24 Jul 17 06:55:02 PM PDT 24 18234784 ps
T48 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3029127044 Jul 17 06:54:23 PM PDT 24 Jul 17 06:54:26 PM PDT 24 69492611 ps
T110 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3027566297 Jul 17 06:54:03 PM PDT 24 Jul 17 06:54:04 PM PDT 24 26113744 ps
T771 /workspace/coverage/cover_reg_top/48.gpio_intr_test.1960745550 Jul 17 06:56:20 PM PDT 24 Jul 17 06:56:24 PM PDT 24 11494707 ps
T111 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.102326858 Jul 17 06:54:59 PM PDT 24 Jul 17 06:55:02 PM PDT 24 48605586 ps
T99 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1083678284 Jul 17 06:54:21 PM PDT 24 Jul 17 06:54:23 PM PDT 24 14309226 ps
T115 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2900917192 Jul 17 06:54:21 PM PDT 24 Jul 17 06:54:25 PM PDT 24 298574204 ps
T772 /workspace/coverage/cover_reg_top/37.gpio_intr_test.514333279 Jul 17 06:56:28 PM PDT 24 Jul 17 06:56:36 PM PDT 24 36484377 ps
T773 /workspace/coverage/cover_reg_top/16.gpio_intr_test.887976815 Jul 17 06:55:00 PM PDT 24 Jul 17 06:55:03 PM PDT 24 18686248 ps
T774 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2846264712 Jul 17 06:54:04 PM PDT 24 Jul 17 06:54:08 PM PDT 24 404513158 ps
T775 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3286044227 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:28 PM PDT 24 66045584 ps
T776 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.113386352 Jul 17 06:54:58 PM PDT 24 Jul 17 06:55:02 PM PDT 24 179878951 ps
T777 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3491289647 Jul 17 06:54:20 PM PDT 24 Jul 17 06:54:23 PM PDT 24 14265059 ps
T778 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1752967965 Jul 17 06:54:03 PM PDT 24 Jul 17 06:54:05 PM PDT 24 20003436 ps
T100 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1966094295 Jul 17 06:54:04 PM PDT 24 Jul 17 06:54:07 PM PDT 24 114647254 ps
T779 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.138382813 Jul 17 06:54:04 PM PDT 24 Jul 17 06:54:07 PM PDT 24 105098630 ps
T780 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3808857517 Jul 17 06:55:00 PM PDT 24 Jul 17 06:55:04 PM PDT 24 118547621 ps
T781 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2410690775 Jul 17 06:54:19 PM PDT 24 Jul 17 06:54:22 PM PDT 24 120483928 ps
T782 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2705338096 Jul 17 06:56:20 PM PDT 24 Jul 17 06:56:23 PM PDT 24 42409177 ps
T783 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3567443442 Jul 17 06:54:03 PM PDT 24 Jul 17 06:54:05 PM PDT 24 59779191 ps
T784 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3425745919 Jul 17 06:53:57 PM PDT 24 Jul 17 06:53:59 PM PDT 24 108844535 ps
T785 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2990067639 Jul 17 06:54:58 PM PDT 24 Jul 17 06:55:02 PM PDT 24 29562937 ps
T786 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2704230294 Jul 17 06:54:08 PM PDT 24 Jul 17 06:54:11 PM PDT 24 61137460 ps
T787 /workspace/coverage/cover_reg_top/17.gpio_intr_test.825779343 Jul 17 06:54:58 PM PDT 24 Jul 17 06:55:02 PM PDT 24 18146124 ps
T788 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2180643457 Jul 17 06:54:03 PM PDT 24 Jul 17 06:54:05 PM PDT 24 26910685 ps
T789 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3799140186 Jul 17 06:54:57 PM PDT 24 Jul 17 06:55:00 PM PDT 24 45564414 ps
T790 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.802478219 Jul 17 06:54:57 PM PDT 24 Jul 17 06:54:59 PM PDT 24 102466809 ps
T791 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2169773649 Jul 17 06:54:18 PM PDT 24 Jul 17 06:54:20 PM PDT 24 198424444 ps
T792 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3113667519 Jul 17 06:54:57 PM PDT 24 Jul 17 06:55:00 PM PDT 24 50709495 ps
T793 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.880290038 Jul 17 06:54:02 PM PDT 24 Jul 17 06:54:04 PM PDT 24 144603069 ps
T794 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2537908695 Jul 17 06:54:19 PM PDT 24 Jul 17 06:54:22 PM PDT 24 42161526 ps
T795 /workspace/coverage/cover_reg_top/25.gpio_intr_test.1075283256 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:30 PM PDT 24 13809247 ps
T796 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2667536354 Jul 17 06:56:20 PM PDT 24 Jul 17 06:56:24 PM PDT 24 16206236 ps
T797 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2564413243 Jul 17 06:54:56 PM PDT 24 Jul 17 06:54:58 PM PDT 24 88724284 ps
T49 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.628082731 Jul 17 06:54:56 PM PDT 24 Jul 17 06:54:59 PM PDT 24 76855767 ps
T798 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.197823000 Jul 17 06:54:05 PM PDT 24 Jul 17 06:54:09 PM PDT 24 2605660211 ps
T799 /workspace/coverage/cover_reg_top/28.gpio_intr_test.943946275 Jul 17 06:56:20 PM PDT 24 Jul 17 06:56:23 PM PDT 24 16725544 ps
T800 /workspace/coverage/cover_reg_top/45.gpio_intr_test.631840294 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:31 PM PDT 24 14596214 ps
T801 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3127474671 Jul 17 06:54:57 PM PDT 24 Jul 17 06:55:00 PM PDT 24 51803708 ps
T802 /workspace/coverage/cover_reg_top/44.gpio_intr_test.376982778 Jul 17 06:56:20 PM PDT 24 Jul 17 06:56:22 PM PDT 24 61267960 ps
T803 /workspace/coverage/cover_reg_top/8.gpio_intr_test.4133814303 Jul 17 06:54:18 PM PDT 24 Jul 17 06:54:19 PM PDT 24 15845433 ps
T804 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3193622736 Jul 17 06:54:58 PM PDT 24 Jul 17 06:55:02 PM PDT 24 66975632 ps
T805 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.4262727106 Jul 17 06:53:56 PM PDT 24 Jul 17 06:53:58 PM PDT 24 25040622 ps
T806 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2400077239 Jul 17 06:53:57 PM PDT 24 Jul 17 06:53:59 PM PDT 24 18298369 ps
T807 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3368529256 Jul 17 06:54:03 PM PDT 24 Jul 17 06:54:06 PM PDT 24 55283667 ps
T808 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4034220441 Jul 17 06:54:57 PM PDT 24 Jul 17 06:55:01 PM PDT 24 40059683 ps
T809 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1038082863 Jul 17 06:54:58 PM PDT 24 Jul 17 06:55:02 PM PDT 24 32807767 ps
T50 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3679430567 Jul 17 06:54:01 PM PDT 24 Jul 17 06:54:03 PM PDT 24 368890855 ps
T810 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.866001796 Jul 17 06:54:08 PM PDT 24 Jul 17 06:54:10 PM PDT 24 58934364 ps
T811 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2715435855 Jul 17 06:54:19 PM PDT 24 Jul 17 06:54:20 PM PDT 24 50250929 ps
T812 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3682329850 Jul 17 06:54:04 PM PDT 24 Jul 17 06:54:07 PM PDT 24 77292614 ps
T813 /workspace/coverage/cover_reg_top/30.gpio_intr_test.2654931942 Jul 17 06:56:19 PM PDT 24 Jul 17 06:56:22 PM PDT 24 27356545 ps
T814 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.336767105 Jul 17 06:54:03 PM PDT 24 Jul 17 06:54:07 PM PDT 24 107771074 ps
T815 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1961002836 Jul 17 06:54:58 PM PDT 24 Jul 17 06:55:02 PM PDT 24 14735019 ps
T816 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.106668271 Jul 17 06:54:04 PM PDT 24 Jul 17 06:54:08 PM PDT 24 183327993 ps
T817 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.204998723 Jul 17 06:54:16 PM PDT 24 Jul 17 06:54:18 PM PDT 24 55573443 ps
T818 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1779247123 Jul 17 06:54:23 PM PDT 24 Jul 17 06:54:26 PM PDT 24 22780872 ps
T819 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.957010588 Jul 17 06:54:21 PM PDT 24 Jul 17 06:54:24 PM PDT 24 242135445 ps
T101 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1654979723 Jul 17 06:53:56 PM PDT 24 Jul 17 06:53:58 PM PDT 24 66939024 ps
T820 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3598786843 Jul 17 06:54:58 PM PDT 24 Jul 17 06:55:02 PM PDT 24 133963071 ps
T821 /workspace/coverage/cover_reg_top/39.gpio_intr_test.3225435786 Jul 17 06:56:28 PM PDT 24 Jul 17 06:56:36 PM PDT 24 55146636 ps
T822 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3686687008 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:29 PM PDT 24 21751896 ps
T823 /workspace/coverage/cover_reg_top/47.gpio_intr_test.923744591 Jul 17 06:56:19 PM PDT 24 Jul 17 06:56:22 PM PDT 24 14005955 ps
T824 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2137744276 Jul 17 06:54:59 PM PDT 24 Jul 17 06:55:05 PM PDT 24 517438432 ps
T825 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.169321389 Jul 17 06:54:58 PM PDT 24 Jul 17 06:55:01 PM PDT 24 27585941 ps
T102 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3121026832 Jul 17 06:54:19 PM PDT 24 Jul 17 06:54:21 PM PDT 24 111453337 ps
T826 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2232453020 Jul 17 06:54:11 PM PDT 24 Jul 17 06:54:12 PM PDT 24 23179917 ps
T827 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3460003432 Jul 17 06:54:08 PM PDT 24 Jul 17 06:54:12 PM PDT 24 432779656 ps
T828 /workspace/coverage/cover_reg_top/42.gpio_intr_test.738714162 Jul 17 06:56:20 PM PDT 24 Jul 17 06:56:23 PM PDT 24 45811590 ps
T104 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1248620998 Jul 17 06:54:05 PM PDT 24 Jul 17 06:54:08 PM PDT 24 21282693 ps
T829 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1915125456 Jul 17 06:54:18 PM PDT 24 Jul 17 06:54:21 PM PDT 24 54409022 ps
T830 /workspace/coverage/cover_reg_top/46.gpio_intr_test.2913290951 Jul 17 06:56:21 PM PDT 24 Jul 17 06:56:26 PM PDT 24 15576871 ps
T831 /workspace/coverage/cover_reg_top/35.gpio_intr_test.249205735 Jul 17 06:56:20 PM PDT 24 Jul 17 06:56:23 PM PDT 24 194100587 ps
T832 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3724962371 Jul 17 06:54:20 PM PDT 24 Jul 17 06:54:23 PM PDT 24 15712566 ps
T833 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2105918696 Jul 17 06:54:20 PM PDT 24 Jul 17 06:54:23 PM PDT 24 30490534 ps
T834 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1766645007 Jul 17 06:54:56 PM PDT 24 Jul 17 06:54:58 PM PDT 24 37714106 ps
T835 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.4184937621 Jul 17 06:54:57 PM PDT 24 Jul 17 06:55:00 PM PDT 24 17848502 ps
T836 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1985472127 Jul 17 06:54:21 PM PDT 24 Jul 17 06:54:24 PM PDT 24 15859212 ps
T837 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1894604130 Jul 17 06:54:04 PM PDT 24 Jul 17 06:54:06 PM PDT 24 14969458 ps
T838 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.688016062 Jul 17 06:54:58 PM PDT 24 Jul 17 06:55:03 PM PDT 24 367756595 ps
T839 /workspace/coverage/cover_reg_top/7.gpio_intr_test.585787460 Jul 17 06:54:19 PM PDT 24 Jul 17 06:54:21 PM PDT 24 13965144 ps
T840 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3650511227 Jul 17 06:54:59 PM PDT 24 Jul 17 06:55:03 PM PDT 24 30750719 ps
T841 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.4242844526 Jul 17 06:54:20 PM PDT 24 Jul 17 06:54:23 PM PDT 24 89209656 ps
T842 /workspace/coverage/cover_reg_top/15.gpio_intr_test.541774987 Jul 17 06:54:58 PM PDT 24 Jul 17 06:55:02 PM PDT 24 13008649 ps
T843 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4121652404 Jul 17 06:54:18 PM PDT 24 Jul 17 06:54:20 PM PDT 24 17141747 ps
T844 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.193394138 Jul 17 06:56:24 PM PDT 24 Jul 17 06:56:33 PM PDT 24 1063717412 ps
T845 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4128613268 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:31 PM PDT 24 74506188 ps
T846 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1046288750 Jul 17 06:56:29 PM PDT 24 Jul 17 06:56:37 PM PDT 24 44452597 ps
T847 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2060635187 Jul 17 06:56:28 PM PDT 24 Jul 17 06:56:36 PM PDT 24 32856438 ps
T848 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.743097944 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:30 PM PDT 24 78548896 ps
T849 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4224100014 Jul 17 06:56:24 PM PDT 24 Jul 17 06:56:33 PM PDT 24 317962557 ps
T850 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1208613092 Jul 17 06:56:25 PM PDT 24 Jul 17 06:56:33 PM PDT 24 241392554 ps
T851 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.555262888 Jul 17 06:56:21 PM PDT 24 Jul 17 06:56:28 PM PDT 24 150768189 ps
T852 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1393807808 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:30 PM PDT 24 58354948 ps
T853 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1375926239 Jul 17 06:56:28 PM PDT 24 Jul 17 06:56:37 PM PDT 24 42756729 ps
T854 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.180169040 Jul 17 06:56:26 PM PDT 24 Jul 17 06:56:34 PM PDT 24 52137550 ps
T855 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2537381426 Jul 17 06:56:25 PM PDT 24 Jul 17 06:56:34 PM PDT 24 153392871 ps
T856 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4285604486 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:30 PM PDT 24 39147854 ps
T857 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.166731820 Jul 17 06:56:27 PM PDT 24 Jul 17 06:56:36 PM PDT 24 35246383 ps
T858 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2695153827 Jul 17 06:56:19 PM PDT 24 Jul 17 06:56:22 PM PDT 24 186911138 ps
T859 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3874013291 Jul 17 06:56:27 PM PDT 24 Jul 17 06:56:35 PM PDT 24 104615036 ps
T860 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3173003358 Jul 17 06:56:24 PM PDT 24 Jul 17 06:56:33 PM PDT 24 337248466 ps
T861 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2148545951 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:30 PM PDT 24 202452132 ps
T862 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.792569836 Jul 17 06:56:27 PM PDT 24 Jul 17 06:56:36 PM PDT 24 130309066 ps
T863 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3305650694 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:31 PM PDT 24 60540967 ps
T864 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1702727098 Jul 17 06:56:26 PM PDT 24 Jul 17 06:56:34 PM PDT 24 150875033 ps
T865 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1935563610 Jul 17 06:56:25 PM PDT 24 Jul 17 06:56:34 PM PDT 24 66076063 ps
T866 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4144250929 Jul 17 06:56:27 PM PDT 24 Jul 17 06:56:35 PM PDT 24 51026718 ps
T867 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.799222464 Jul 17 06:56:21 PM PDT 24 Jul 17 06:56:26 PM PDT 24 223282818 ps
T868 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2684426799 Jul 17 06:56:29 PM PDT 24 Jul 17 06:56:37 PM PDT 24 55141846 ps
T869 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.225057356 Jul 17 06:56:29 PM PDT 24 Jul 17 06:56:37 PM PDT 24 65042149 ps
T870 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1901575719 Jul 17 06:56:27 PM PDT 24 Jul 17 06:56:35 PM PDT 24 60428511 ps
T871 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3438966595 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:31 PM PDT 24 76323361 ps
T872 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2234454448 Jul 17 06:56:21 PM PDT 24 Jul 17 06:56:28 PM PDT 24 211768059 ps
T873 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4235690272 Jul 17 06:56:27 PM PDT 24 Jul 17 06:56:36 PM PDT 24 37822948 ps
T874 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1273918626 Jul 17 06:56:26 PM PDT 24 Jul 17 06:56:35 PM PDT 24 176651483 ps
T875 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1737585211 Jul 17 06:56:25 PM PDT 24 Jul 17 06:56:34 PM PDT 24 44044488 ps
T876 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3725224046 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:30 PM PDT 24 57808631 ps
T877 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.138431874 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:30 PM PDT 24 443590800 ps
T878 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2506528951 Jul 17 06:56:26 PM PDT 24 Jul 17 06:56:35 PM PDT 24 74382191 ps
T879 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.701870529 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:30 PM PDT 24 95014031 ps
T880 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2089230126 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:32 PM PDT 24 97695158 ps
T881 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4024823857 Jul 17 06:56:32 PM PDT 24 Jul 17 06:56:39 PM PDT 24 87119063 ps
T882 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4158286269 Jul 17 06:56:21 PM PDT 24 Jul 17 06:56:26 PM PDT 24 69920393 ps
T883 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3446004231 Jul 17 06:56:26 PM PDT 24 Jul 17 06:56:35 PM PDT 24 367434614 ps
T884 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2502898039 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:32 PM PDT 24 100035019 ps
T885 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.988294003 Jul 17 06:56:28 PM PDT 24 Jul 17 06:56:36 PM PDT 24 127220333 ps
T886 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1589144984 Jul 17 06:56:25 PM PDT 24 Jul 17 06:56:34 PM PDT 24 60939521 ps
T887 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3979699646 Jul 17 06:56:25 PM PDT 24 Jul 17 06:56:33 PM PDT 24 75975472 ps
T888 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1040776292 Jul 17 06:56:28 PM PDT 24 Jul 17 06:56:37 PM PDT 24 164622171 ps
T889 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1077219473 Jul 17 06:56:28 PM PDT 24 Jul 17 06:56:37 PM PDT 24 303811269 ps
T890 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1340585216 Jul 17 06:56:24 PM PDT 24 Jul 17 06:56:33 PM PDT 24 320455618 ps
T891 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3730148712 Jul 17 06:56:28 PM PDT 24 Jul 17 06:56:36 PM PDT 24 98028122 ps
T892 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2043940802 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:31 PM PDT 24 268264336 ps
T893 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3088100074 Jul 17 06:56:27 PM PDT 24 Jul 17 06:56:36 PM PDT 24 43867673 ps
T894 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2087651026 Jul 17 06:56:32 PM PDT 24 Jul 17 06:56:38 PM PDT 24 58096082 ps
T895 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1776033508 Jul 17 06:56:26 PM PDT 24 Jul 17 06:56:35 PM PDT 24 117788480 ps
T896 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3125790098 Jul 17 06:56:21 PM PDT 24 Jul 17 06:56:25 PM PDT 24 69942617 ps
T897 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3071176280 Jul 17 06:56:21 PM PDT 24 Jul 17 06:56:26 PM PDT 24 1084477574 ps
T898 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3996140708 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:28 PM PDT 24 101351345 ps
T899 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3773423044 Jul 17 06:56:29 PM PDT 24 Jul 17 06:56:37 PM PDT 24 145952709 ps
T900 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.622082435 Jul 17 06:56:29 PM PDT 24 Jul 17 06:56:37 PM PDT 24 50912779 ps
T901 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4026037098 Jul 17 06:56:28 PM PDT 24 Jul 17 06:56:36 PM PDT 24 123369726 ps
T902 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3342287682 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:31 PM PDT 24 511335211 ps
T903 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1569786574 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:30 PM PDT 24 36761592 ps
T904 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2518654743 Jul 17 06:56:20 PM PDT 24 Jul 17 06:56:24 PM PDT 24 78700424 ps
T905 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1363975753 Jul 17 06:56:28 PM PDT 24 Jul 17 06:56:36 PM PDT 24 296050854 ps
T906 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.89522740 Jul 17 06:56:37 PM PDT 24 Jul 17 06:56:41 PM PDT 24 61935339 ps
T907 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.407976902 Jul 17 06:56:21 PM PDT 24 Jul 17 06:56:28 PM PDT 24 322522088 ps
T908 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3091919727 Jul 17 06:56:26 PM PDT 24 Jul 17 06:56:34 PM PDT 24 26429370 ps
T909 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2577765051 Jul 17 06:56:27 PM PDT 24 Jul 17 06:56:35 PM PDT 24 653162948 ps
T910 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2271507173 Jul 17 06:56:26 PM PDT 24 Jul 17 06:56:35 PM PDT 24 309095364 ps
T911 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2324491177 Jul 17 06:56:21 PM PDT 24 Jul 17 06:56:27 PM PDT 24 30865454 ps
T912 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1911729659 Jul 17 06:56:24 PM PDT 24 Jul 17 06:56:32 PM PDT 24 379437551 ps
T913 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3365576315 Jul 17 06:56:27 PM PDT 24 Jul 17 06:56:35 PM PDT 24 288801210 ps
T914 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4051905927 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:32 PM PDT 24 54394436 ps
T915 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.972097743 Jul 17 06:56:27 PM PDT 24 Jul 17 06:56:35 PM PDT 24 117222531 ps
T916 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3459380593 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:29 PM PDT 24 108165974 ps
T917 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.4035824242 Jul 17 06:56:21 PM PDT 24 Jul 17 06:56:27 PM PDT 24 64765299 ps
T918 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2977995949 Jul 17 06:56:26 PM PDT 24 Jul 17 06:56:35 PM PDT 24 179525983 ps
T919 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.838724674 Jul 17 06:56:21 PM PDT 24 Jul 17 06:56:26 PM PDT 24 61235567 ps
T920 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2595091641 Jul 17 06:56:26 PM PDT 24 Jul 17 06:56:34 PM PDT 24 58563122 ps
T921 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2388353407 Jul 17 06:56:25 PM PDT 24 Jul 17 06:56:33 PM PDT 24 118319314 ps
T922 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3986893317 Jul 17 06:56:30 PM PDT 24 Jul 17 06:56:37 PM PDT 24 31833820 ps
T923 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3998238936 Jul 17 06:56:26 PM PDT 24 Jul 17 06:56:34 PM PDT 24 104081456 ps
T924 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2727932557 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:30 PM PDT 24 127588855 ps
T925 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3118522254 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:28 PM PDT 24 83724992 ps
T926 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4064324640 Jul 17 06:56:26 PM PDT 24 Jul 17 06:56:35 PM PDT 24 107389215 ps
T927 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1086285938 Jul 17 06:56:24 PM PDT 24 Jul 17 06:56:33 PM PDT 24 127570101 ps
T928 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1213704913 Jul 17 06:56:28 PM PDT 24 Jul 17 06:56:36 PM PDT 24 43514585 ps
T929 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2044347648 Jul 17 06:56:25 PM PDT 24 Jul 17 06:56:33 PM PDT 24 241899069 ps
T930 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1067759795 Jul 17 06:56:29 PM PDT 24 Jul 17 06:56:37 PM PDT 24 38009553 ps
T931 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2057970053 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:30 PM PDT 24 32637279 ps
T932 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2036475863 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:31 PM PDT 24 48016742 ps
T933 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.890754864 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:28 PM PDT 24 70730582 ps
T934 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.539204721 Jul 17 06:56:20 PM PDT 24 Jul 17 06:56:25 PM PDT 24 68079506 ps
T935 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2335734489 Jul 17 06:56:24 PM PDT 24 Jul 17 06:56:32 PM PDT 24 515048228 ps
T936 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2087328732 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:30 PM PDT 24 83397022 ps
T937 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1694595417 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:29 PM PDT 24 31015423 ps
T938 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2432584577 Jul 17 06:56:21 PM PDT 24 Jul 17 06:56:26 PM PDT 24 120958766 ps
T939 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2517679018 Jul 17 06:56:21 PM PDT 24 Jul 17 06:56:26 PM PDT 24 83113796 ps
T940 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2044815122 Jul 17 06:56:21 PM PDT 24 Jul 17 06:56:26 PM PDT 24 169927228 ps
T941 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3149262509 Jul 17 06:56:24 PM PDT 24 Jul 17 06:56:32 PM PDT 24 103705826 ps
T942 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3428191804 Jul 17 06:56:22 PM PDT 24 Jul 17 06:56:28 PM PDT 24 94521916 ps
T943 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1827894089 Jul 17 06:56:23 PM PDT 24 Jul 17 06:56:30 PM PDT 24 145368838 ps

Test location /workspace/coverage/default/8.gpio_full_random.3968961259
Short name T32
Test name
Test status
Simulation time 300061563 ps
CPU time 0.99 seconds
Started Jul 17 06:57:49 PM PDT 24
Finished Jul 17 06:57:52 PM PDT 24
Peak memory 198808 kb
Host smart-ad0efa22-8e94-42ac-8b91-630303dbdec1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968961259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3968961259
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1567842431
Short name T12
Test name
Test status
Simulation time 59145919 ps
CPU time 2.39 seconds
Started Jul 17 06:59:37 PM PDT 24
Finished Jul 17 06:59:44 PM PDT 24
Peak memory 198672 kb
Host smart-3f646937-3f5d-4bd6-bac7-dc2a5a460538
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567842431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1567842431
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.4150612968
Short name T16
Test name
Test status
Simulation time 513608017026 ps
CPU time 2082.36 seconds
Started Jul 17 06:59:16 PM PDT 24
Finished Jul 17 07:33:59 PM PDT 24
Peak memory 198896 kb
Host smart-3e7e4099-9bbe-433d-931a-6c0650f812e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4150612968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.4150612968
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2762767085
Short name T2
Test name
Test status
Simulation time 12698041707 ps
CPU time 154.09 seconds
Started Jul 17 06:58:51 PM PDT 24
Finished Jul 17 07:01:27 PM PDT 24
Peak memory 198760 kb
Host smart-a133df54-5daf-421c-a5ef-df9ba2d9ac41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762767085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2762767085
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1993019031
Short name T90
Test name
Test status
Simulation time 1662293595 ps
CPU time 2.45 seconds
Started Jul 17 06:54:03 PM PDT 24
Finished Jul 17 06:54:06 PM PDT 24
Peak memory 197932 kb
Host smart-8b8da994-388a-4e81-a513-58b0d8308873
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993019031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1993019031
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3230546649
Short name T39
Test name
Test status
Simulation time 180745565 ps
CPU time 1.14 seconds
Started Jul 17 06:53:56 PM PDT 24
Finished Jul 17 06:53:58 PM PDT 24
Peak memory 198772 kb
Host smart-782b17c0-a947-43ae-a873-963a2e60d1bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230546649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3230546649
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2545920591
Short name T27
Test name
Test status
Simulation time 16702028 ps
CPU time 0.55 seconds
Started Jul 17 06:57:49 PM PDT 24
Finished Jul 17 06:57:51 PM PDT 24
Peak memory 194628 kb
Host smart-5397289f-9392-4fc6-8aa0-bfd975f4596b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545920591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2545920591
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1707416384
Short name T21
Test name
Test status
Simulation time 84353260 ps
CPU time 1.45 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 198628 kb
Host smart-ed73134a-9baa-4708-8548-0771ef18bc1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707416384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1707416384
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2351704053
Short name T41
Test name
Test status
Simulation time 625140658 ps
CPU time 0.91 seconds
Started Jul 17 06:56:57 PM PDT 24
Finished Jul 17 06:56:59 PM PDT 24
Peak memory 215344 kb
Host smart-1a06a88f-f474-4bb7-b917-c87a3a5074dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351704053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2351704053
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3679430567
Short name T50
Test name
Test status
Simulation time 368890855 ps
CPU time 1.36 seconds
Started Jul 17 06:54:01 PM PDT 24
Finished Jul 17 06:54:03 PM PDT 24
Peak memory 198660 kb
Host smart-ad9fc83e-4e76-4131-a8c7-4599aad45bb7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679430567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3679430567
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2481531036
Short name T106
Test name
Test status
Simulation time 32612263 ps
CPU time 0.84 seconds
Started Jul 17 06:53:52 PM PDT 24
Finished Jul 17 06:53:56 PM PDT 24
Peak memory 197660 kb
Host smart-530f0965-786e-4dc1-be2f-7f8aabc29ddc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481531036 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2481531036
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3009071210
Short name T37
Test name
Test status
Simulation time 264645154 ps
CPU time 1.48 seconds
Started Jul 17 06:54:20 PM PDT 24
Finished Jul 17 06:54:23 PM PDT 24
Peak memory 198736 kb
Host smart-812066c0-641c-42b5-a186-1d476e903be3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009071210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3009071210
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3394505460
Short name T38
Test name
Test status
Simulation time 168969791 ps
CPU time 1.12 seconds
Started Jul 17 06:54:57 PM PDT 24
Finished Jul 17 06:55:01 PM PDT 24
Peak memory 198900 kb
Host smart-dce06e00-9cf3-425f-b544-f4c8e1676c67
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394505460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3394505460
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1654979723
Short name T101
Test name
Test status
Simulation time 66939024 ps
CPU time 0.64 seconds
Started Jul 17 06:53:56 PM PDT 24
Finished Jul 17 06:53:58 PM PDT 24
Peak memory 195732 kb
Host smart-a42a7cd3-231e-49e8-be12-94e95d924c4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654979723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1654979723
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.828323197
Short name T103
Test name
Test status
Simulation time 262301319 ps
CPU time 2.56 seconds
Started Jul 17 06:53:49 PM PDT 24
Finished Jul 17 06:53:53 PM PDT 24
Peak memory 197444 kb
Host smart-3132f0f8-8e40-4ac0-9e40-5325e2d4d4e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828323197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.828323197
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1839476631
Short name T742
Test name
Test status
Simulation time 51880608 ps
CPU time 0.64 seconds
Started Jul 17 06:53:49 PM PDT 24
Finished Jul 17 06:53:52 PM PDT 24
Peak memory 195540 kb
Host smart-6f1e9330-9ed1-4796-bc9e-ef8a87e316d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839476631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1839476631
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.362879697
Short name T721
Test name
Test status
Simulation time 23109980 ps
CPU time 0.77 seconds
Started Jul 17 06:53:57 PM PDT 24
Finished Jul 17 06:53:59 PM PDT 24
Peak memory 198664 kb
Host smart-f55847ae-3512-409e-9ad4-1ff420c8c81b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362879697 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.362879697
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.4262727106
Short name T805
Test name
Test status
Simulation time 25040622 ps
CPU time 0.59 seconds
Started Jul 17 06:53:56 PM PDT 24
Finished Jul 17 06:53:58 PM PDT 24
Peak memory 195972 kb
Host smart-256d9b7f-7594-4f1d-a936-d88a2a844c28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262727106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.4262727106
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2400077239
Short name T806
Test name
Test status
Simulation time 18298369 ps
CPU time 0.58 seconds
Started Jul 17 06:53:57 PM PDT 24
Finished Jul 17 06:53:59 PM PDT 24
Peak memory 194420 kb
Host smart-c2d6353d-6ea5-45e6-970c-7f2aa3b3d61a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400077239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2400077239
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3425745919
Short name T784
Test name
Test status
Simulation time 108844535 ps
CPU time 1.21 seconds
Started Jul 17 06:53:57 PM PDT 24
Finished Jul 17 06:53:59 PM PDT 24
Peak memory 198720 kb
Host smart-96e19837-cf00-4014-8894-5557c4a3c991
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425745919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3425745919
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3865021454
Short name T97
Test name
Test status
Simulation time 15569672 ps
CPU time 0.75 seconds
Started Jul 17 06:54:11 PM PDT 24
Finished Jul 17 06:54:13 PM PDT 24
Peak memory 197060 kb
Host smart-9457ebf7-70ca-481d-8645-e1565c75296e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865021454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3865021454
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1966094295
Short name T100
Test name
Test status
Simulation time 114647254 ps
CPU time 0.62 seconds
Started Jul 17 06:54:04 PM PDT 24
Finished Jul 17 06:54:07 PM PDT 24
Peak memory 195696 kb
Host smart-036a6de5-e805-4e2b-849e-80af3378489b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966094295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1966094295
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3682329850
Short name T812
Test name
Test status
Simulation time 77292614 ps
CPU time 1.01 seconds
Started Jul 17 06:54:04 PM PDT 24
Finished Jul 17 06:54:07 PM PDT 24
Peak memory 198576 kb
Host smart-f62ced5e-8e1a-4c22-b3c4-c483e6d98df6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682329850 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3682329850
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3464287109
Short name T88
Test name
Test status
Simulation time 14758043 ps
CPU time 0.63 seconds
Started Jul 17 06:54:05 PM PDT 24
Finished Jul 17 06:54:08 PM PDT 24
Peak memory 195688 kb
Host smart-e0c7d09c-c8e5-42ca-9722-d69763220308
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464287109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3464287109
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.18559986
Short name T752
Test name
Test status
Simulation time 24533333 ps
CPU time 0.61 seconds
Started Jul 17 06:54:05 PM PDT 24
Finished Jul 17 06:54:08 PM PDT 24
Peak memory 194988 kb
Host smart-31d3123d-9a6f-4f75-81b8-fc4e58e13269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18559986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.18559986
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3027566297
Short name T110
Test name
Test status
Simulation time 26113744 ps
CPU time 0.67 seconds
Started Jul 17 06:54:03 PM PDT 24
Finished Jul 17 06:54:04 PM PDT 24
Peak memory 196236 kb
Host smart-fa04d00e-8c05-4293-be67-a5536733c51a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027566297 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3027566297
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2846264712
Short name T774
Test name
Test status
Simulation time 404513158 ps
CPU time 1.1 seconds
Started Jul 17 06:54:04 PM PDT 24
Finished Jul 17 06:54:08 PM PDT 24
Peak memory 198568 kb
Host smart-47c74af6-d4de-4fbd-9bd2-59f0be71166d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846264712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2846264712
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3139413664
Short name T734
Test name
Test status
Simulation time 49837696 ps
CPU time 0.92 seconds
Started Jul 17 06:54:19 PM PDT 24
Finished Jul 17 06:54:22 PM PDT 24
Peak memory 198552 kb
Host smart-666f1b6b-596a-46cf-8536-d03513ac11cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139413664 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3139413664
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3121026832
Short name T102
Test name
Test status
Simulation time 111453337 ps
CPU time 0.61 seconds
Started Jul 17 06:54:19 PM PDT 24
Finished Jul 17 06:54:21 PM PDT 24
Peak memory 195476 kb
Host smart-aff8d319-f73a-43f8-9ce3-d7ea70c736c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121026832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3121026832
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3052216217
Short name T741
Test name
Test status
Simulation time 12606177 ps
CPU time 0.56 seconds
Started Jul 17 06:54:20 PM PDT 24
Finished Jul 17 06:54:23 PM PDT 24
Peak memory 194308 kb
Host smart-36405d14-f276-4cc4-ae1d-32ed7a781a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052216217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3052216217
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2105918696
Short name T833
Test name
Test status
Simulation time 30490534 ps
CPU time 0.64 seconds
Started Jul 17 06:54:20 PM PDT 24
Finished Jul 17 06:54:23 PM PDT 24
Peak memory 195620 kb
Host smart-d19dfedb-ac68-4456-a34c-09fc2ac08061
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105918696 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2105918696
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.178602032
Short name T767
Test name
Test status
Simulation time 199019408 ps
CPU time 2.04 seconds
Started Jul 17 06:54:19 PM PDT 24
Finished Jul 17 06:54:22 PM PDT 24
Peak memory 198740 kb
Host smart-28ff4718-1e9b-4821-8fed-54e695d1333a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178602032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.178602032
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2715435855
Short name T811
Test name
Test status
Simulation time 50250929 ps
CPU time 0.66 seconds
Started Jul 17 06:54:19 PM PDT 24
Finished Jul 17 06:54:20 PM PDT 24
Peak memory 197892 kb
Host smart-41c25ee3-04a6-4e53-a8ca-db5cbd2d0348
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715435855 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2715435855
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1083678284
Short name T99
Test name
Test status
Simulation time 14309226 ps
CPU time 0.57 seconds
Started Jul 17 06:54:21 PM PDT 24
Finished Jul 17 06:54:23 PM PDT 24
Peak memory 193956 kb
Host smart-d87b9b5e-2fb6-4eae-91e1-32d90ec8b849
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083678284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1083678284
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1558250472
Short name T765
Test name
Test status
Simulation time 29656628 ps
CPU time 0.61 seconds
Started Jul 17 06:54:19 PM PDT 24
Finished Jul 17 06:54:22 PM PDT 24
Peak memory 194364 kb
Host smart-a89ecbfa-7287-475c-a77e-6aa5213803c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558250472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1558250472
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1779247123
Short name T818
Test name
Test status
Simulation time 22780872 ps
CPU time 0.69 seconds
Started Jul 17 06:54:23 PM PDT 24
Finished Jul 17 06:54:26 PM PDT 24
Peak memory 196472 kb
Host smart-925b9210-9708-49ae-a557-500dd8048727
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779247123 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1779247123
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.673046254
Short name T743
Test name
Test status
Simulation time 407212747 ps
CPU time 2.22 seconds
Started Jul 17 06:54:20 PM PDT 24
Finished Jul 17 06:54:23 PM PDT 24
Peak memory 198908 kb
Host smart-d8c7a222-893b-4c97-9dca-77f5d2d3e486
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673046254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.673046254
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.4242844526
Short name T841
Test name
Test status
Simulation time 89209656 ps
CPU time 0.86 seconds
Started Jul 17 06:54:20 PM PDT 24
Finished Jul 17 06:54:23 PM PDT 24
Peak memory 197952 kb
Host smart-99e3ac6a-d803-484c-afdf-53e3e22cebed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242844526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.4242844526
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2410690775
Short name T781
Test name
Test status
Simulation time 120483928 ps
CPU time 1.43 seconds
Started Jul 17 06:54:19 PM PDT 24
Finished Jul 17 06:54:22 PM PDT 24
Peak memory 198772 kb
Host smart-28fd8629-4713-4395-be28-e82135f28175
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410690775 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2410690775
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3491289647
Short name T777
Test name
Test status
Simulation time 14265059 ps
CPU time 0.57 seconds
Started Jul 17 06:54:20 PM PDT 24
Finished Jul 17 06:54:23 PM PDT 24
Peak memory 195912 kb
Host smart-f1b63bd5-9828-45ea-8a61-494b002e4daa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491289647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3491289647
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.811640064
Short name T757
Test name
Test status
Simulation time 18663014 ps
CPU time 0.57 seconds
Started Jul 17 06:54:56 PM PDT 24
Finished Jul 17 06:54:57 PM PDT 24
Peak memory 194324 kb
Host smart-e67d34f8-a2c3-4f75-976a-6f4ad14ecf43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811640064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.811640064
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3567620320
Short name T105
Test name
Test status
Simulation time 109950446 ps
CPU time 0.76 seconds
Started Jul 17 06:54:19 PM PDT 24
Finished Jul 17 06:54:22 PM PDT 24
Peak memory 197676 kb
Host smart-c353db9b-c44e-4af5-ae55-dc7c4984167e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567620320 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3567620320
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1904643399
Short name T754
Test name
Test status
Simulation time 169216871 ps
CPU time 2.3 seconds
Started Jul 17 06:54:22 PM PDT 24
Finished Jul 17 06:54:26 PM PDT 24
Peak memory 198720 kb
Host smart-35eb6ff1-2f8f-47e0-abd7-a8f4bc6678a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904643399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1904643399
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3029127044
Short name T48
Test name
Test status
Simulation time 69492611 ps
CPU time 1.07 seconds
Started Jul 17 06:54:23 PM PDT 24
Finished Jul 17 06:54:26 PM PDT 24
Peak memory 198244 kb
Host smart-279839e9-dcad-4509-96d2-e293cd62b768
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029127044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3029127044
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3808857517
Short name T780
Test name
Test status
Simulation time 118547621 ps
CPU time 0.93 seconds
Started Jul 17 06:55:00 PM PDT 24
Finished Jul 17 06:55:04 PM PDT 24
Peak memory 198572 kb
Host smart-6c830015-9f6a-4099-83d7-6acd18bb203b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808857517 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3808857517
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3650511227
Short name T840
Test name
Test status
Simulation time 30750719 ps
CPU time 0.57 seconds
Started Jul 17 06:54:59 PM PDT 24
Finished Jul 17 06:55:03 PM PDT 24
Peak memory 194640 kb
Host smart-1b846a59-7e78-4371-b357-b47b8e4fd16a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650511227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3650511227
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3127474671
Short name T801
Test name
Test status
Simulation time 51803708 ps
CPU time 0.6 seconds
Started Jul 17 06:54:57 PM PDT 24
Finished Jul 17 06:55:00 PM PDT 24
Peak memory 194420 kb
Host smart-04e16937-62db-44d7-9b71-5244d11166d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127474671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3127474671
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.786673802
Short name T107
Test name
Test status
Simulation time 151598016 ps
CPU time 0.87 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 197340 kb
Host smart-42bf5e07-6662-4d55-a41e-7cc297cc5992
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786673802 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.786673802
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.113386352
Short name T776
Test name
Test status
Simulation time 179878951 ps
CPU time 1.92 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 198796 kb
Host smart-48f5ee33-3db9-4da0-b376-e852f228659c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113386352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.113386352
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2448023880
Short name T46
Test name
Test status
Simulation time 122896942 ps
CPU time 1.44 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 198680 kb
Host smart-5a75948f-209c-471e-bc15-1a9b59e5ef38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448023880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2448023880
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2800227638
Short name T753
Test name
Test status
Simulation time 31984335 ps
CPU time 0.89 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 198580 kb
Host smart-a19492b2-26b9-4ef7-9761-d0cfb3157cc2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800227638 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2800227638
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2054431196
Short name T758
Test name
Test status
Simulation time 34729981 ps
CPU time 0.58 seconds
Started Jul 17 06:54:57 PM PDT 24
Finished Jul 17 06:54:58 PM PDT 24
Peak memory 194032 kb
Host smart-4e75fe3d-c1c9-4fe8-b202-40f045d1ff6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054431196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2054431196
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3444019320
Short name T724
Test name
Test status
Simulation time 13073912 ps
CPU time 0.59 seconds
Started Jul 17 06:54:57 PM PDT 24
Finished Jul 17 06:54:59 PM PDT 24
Peak memory 194388 kb
Host smart-e9e86406-8d02-40c8-997f-f2e783777612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444019320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3444019320
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3587267479
Short name T96
Test name
Test status
Simulation time 20011619 ps
CPU time 0.79 seconds
Started Jul 17 06:54:57 PM PDT 24
Finished Jul 17 06:54:59 PM PDT 24
Peak memory 196796 kb
Host smart-0f736951-bafb-46f2-b549-b9d5eae6b93e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587267479 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3587267479
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.688016062
Short name T838
Test name
Test status
Simulation time 367756595 ps
CPU time 2.97 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:03 PM PDT 24
Peak memory 198724 kb
Host smart-c7f0be57-fdc8-4e06-804f-092c769dadf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688016062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.688016062
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.929570531
Short name T747
Test name
Test status
Simulation time 46663448 ps
CPU time 0.91 seconds
Started Jul 17 06:54:59 PM PDT 24
Finished Jul 17 06:55:03 PM PDT 24
Peak memory 197948 kb
Host smart-e691be45-e3da-4561-872a-630b2e03e376
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929570531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.929570531
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.169321389
Short name T825
Test name
Test status
Simulation time 27585941 ps
CPU time 0.82 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:01 PM PDT 24
Peak memory 198576 kb
Host smart-7bdcd91d-0464-46da-a68c-68031cffa84c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169321389 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.169321389
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.4184937621
Short name T835
Test name
Test status
Simulation time 17848502 ps
CPU time 0.61 seconds
Started Jul 17 06:54:57 PM PDT 24
Finished Jul 17 06:55:00 PM PDT 24
Peak memory 195236 kb
Host smart-0f3cb817-c2ef-4b07-8ae0-89820c2beb09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184937621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.4184937621
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.541774987
Short name T842
Test name
Test status
Simulation time 13008649 ps
CPU time 0.58 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 195028 kb
Host smart-8c463aab-6529-4934-ab76-6caf6b9a627b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541774987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.541774987
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3193622736
Short name T804
Test name
Test status
Simulation time 66975632 ps
CPU time 0.62 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 196192 kb
Host smart-a2073031-70cf-4590-ad71-0a714d91c294
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193622736 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3193622736
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1979836393
Short name T727
Test name
Test status
Simulation time 68045806 ps
CPU time 1.31 seconds
Started Jul 17 06:54:56 PM PDT 24
Finished Jul 17 06:54:59 PM PDT 24
Peak memory 198688 kb
Host smart-3f39043c-9bf3-4df9-9d4e-2dfb20c7f3dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979836393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1979836393
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2879621445
Short name T52
Test name
Test status
Simulation time 296070957 ps
CPU time 1.12 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 198724 kb
Host smart-fb0c5e83-7e18-4ce3-a3a2-22f9eb085518
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879621445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2879621445
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1217576130
Short name T761
Test name
Test status
Simulation time 34118051 ps
CPU time 1.05 seconds
Started Jul 17 06:55:00 PM PDT 24
Finished Jul 17 06:55:04 PM PDT 24
Peak memory 198568 kb
Host smart-247e08f1-b155-4c80-83b3-040d6cb53434
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217576130 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1217576130
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4034220441
Short name T808
Test name
Test status
Simulation time 40059683 ps
CPU time 0.62 seconds
Started Jul 17 06:54:57 PM PDT 24
Finished Jul 17 06:55:01 PM PDT 24
Peak memory 195928 kb
Host smart-1cf81805-a863-41ae-8a9d-3c1c7bc6a76e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034220441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.4034220441
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.887976815
Short name T773
Test name
Test status
Simulation time 18686248 ps
CPU time 0.57 seconds
Started Jul 17 06:55:00 PM PDT 24
Finished Jul 17 06:55:03 PM PDT 24
Peak memory 194976 kb
Host smart-ddff0e7d-3251-4283-bc97-d466ae0477bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887976815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.887976815
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1038082863
Short name T809
Test name
Test status
Simulation time 32807767 ps
CPU time 0.83 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 197680 kb
Host smart-cc8273b8-5f4b-488c-b976-e65563da10c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038082863 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1038082863
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1033208795
Short name T736
Test name
Test status
Simulation time 259148901 ps
CPU time 1.66 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:03 PM PDT 24
Peak memory 198776 kb
Host smart-2ff24cf2-165c-4351-bca4-34f733f922a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033208795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1033208795
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2564413243
Short name T797
Test name
Test status
Simulation time 88724284 ps
CPU time 1.15 seconds
Started Jul 17 06:54:56 PM PDT 24
Finished Jul 17 06:54:58 PM PDT 24
Peak memory 198716 kb
Host smart-7ff52b3a-35a9-4dbb-87a1-35aea2c8d899
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564413243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2564413243
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.4199218935
Short name T730
Test name
Test status
Simulation time 27101663 ps
CPU time 1.22 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 198724 kb
Host smart-df642198-a7d8-4064-aedd-6e89b6e3ad87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199218935 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.4199218935
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.732200579
Short name T95
Test name
Test status
Simulation time 14670625 ps
CPU time 0.6 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:01 PM PDT 24
Peak memory 195004 kb
Host smart-6f8791bd-dbd6-4ae1-91fb-fedd40eeb144
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732200579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.732200579
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.825779343
Short name T787
Test name
Test status
Simulation time 18146124 ps
CPU time 0.62 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 194364 kb
Host smart-70f0b0ba-9fdb-4ede-9ea0-04ef5c059007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825779343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.825779343
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.102326858
Short name T111
Test name
Test status
Simulation time 48605586 ps
CPU time 0.77 seconds
Started Jul 17 06:54:59 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 196548 kb
Host smart-92d98521-4df3-4279-b30c-2494cc5061b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102326858 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.102326858
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2137744276
Short name T824
Test name
Test status
Simulation time 517438432 ps
CPU time 2.58 seconds
Started Jul 17 06:54:59 PM PDT 24
Finished Jul 17 06:55:05 PM PDT 24
Peak memory 198644 kb
Host smart-1585b793-e0b2-443b-85ff-afad37c753c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137744276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2137744276
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3799140186
Short name T789
Test name
Test status
Simulation time 45564414 ps
CPU time 0.84 seconds
Started Jul 17 06:54:57 PM PDT 24
Finished Jul 17 06:55:00 PM PDT 24
Peak memory 197916 kb
Host smart-5dcfed45-a127-49ee-8561-9953ece1e924
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799140186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3799140186
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2990067639
Short name T785
Test name
Test status
Simulation time 29562937 ps
CPU time 0.67 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 197568 kb
Host smart-0023651a-13a3-40d9-91c9-e0e16d7f3e61
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990067639 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2990067639
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3750028579
Short name T113
Test name
Test status
Simulation time 25044985 ps
CPU time 0.65 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 195464 kb
Host smart-f3ab3159-f8f2-4c7c-8647-8c7597bbe2f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750028579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3750028579
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3821512967
Short name T748
Test name
Test status
Simulation time 60053323 ps
CPU time 0.61 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 194432 kb
Host smart-8d61b618-d9e2-4aee-aee6-7600fe0c1504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821512967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3821512967
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2182277791
Short name T91
Test name
Test status
Simulation time 29179622 ps
CPU time 0.81 seconds
Started Jul 17 06:55:00 PM PDT 24
Finished Jul 17 06:55:03 PM PDT 24
Peak memory 196896 kb
Host smart-90f26eda-5a00-43f6-869d-0614bd17bae1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182277791 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2182277791
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3789703348
Short name T732
Test name
Test status
Simulation time 406930034 ps
CPU time 1.31 seconds
Started Jul 17 06:54:57 PM PDT 24
Finished Jul 17 06:54:59 PM PDT 24
Peak memory 198752 kb
Host smart-46246371-c29f-4aae-8260-73d2cd6f66f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789703348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3789703348
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.802478219
Short name T790
Test name
Test status
Simulation time 102466809 ps
CPU time 1.18 seconds
Started Jul 17 06:54:57 PM PDT 24
Finished Jul 17 06:54:59 PM PDT 24
Peak memory 198808 kb
Host smart-d9458a1b-3be5-454b-9aab-163e72206497
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802478219 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.802478219
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3113667519
Short name T792
Test name
Test status
Simulation time 50709495 ps
CPU time 0.66 seconds
Started Jul 17 06:54:57 PM PDT 24
Finished Jul 17 06:55:00 PM PDT 24
Peak memory 195148 kb
Host smart-90256714-3ea2-4d97-9752-878431407cae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113667519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3113667519
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2169910509
Short name T739
Test name
Test status
Simulation time 11262198 ps
CPU time 0.58 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:01 PM PDT 24
Peak memory 194276 kb
Host smart-b99f4e3e-4fa4-4fa9-94fb-d472ef523476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169910509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2169910509
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1766645007
Short name T834
Test name
Test status
Simulation time 37714106 ps
CPU time 0.87 seconds
Started Jul 17 06:54:56 PM PDT 24
Finished Jul 17 06:54:58 PM PDT 24
Peak memory 197668 kb
Host smart-ae1cd0cf-d039-4693-bdb1-3f4ca683d39a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766645007 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1766645007
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3598786843
Short name T820
Test name
Test status
Simulation time 133963071 ps
CPU time 1.25 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 198732 kb
Host smart-c509a1ba-3e71-434b-8bc6-f7de01e1a005
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598786843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3598786843
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.628082731
Short name T49
Test name
Test status
Simulation time 76855767 ps
CPU time 1.12 seconds
Started Jul 17 06:54:56 PM PDT 24
Finished Jul 17 06:54:59 PM PDT 24
Peak memory 198724 kb
Host smart-558f1960-6591-4e07-a554-9cc78b943ae3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628082731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.628082731
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.4093108368
Short name T759
Test name
Test status
Simulation time 13811079 ps
CPU time 0.65 seconds
Started Jul 17 06:54:12 PM PDT 24
Finished Jul 17 06:54:14 PM PDT 24
Peak memory 195128 kb
Host smart-c3b627ff-df37-4e5c-87c7-77e431a95dcf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093108368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.4093108368
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.197823000
Short name T798
Test name
Test status
Simulation time 2605660211 ps
CPU time 1.48 seconds
Started Jul 17 06:54:05 PM PDT 24
Finished Jul 17 06:54:09 PM PDT 24
Peak memory 197260 kb
Host smart-0825596e-a377-442c-af48-6a7a94670500
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197823000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.197823000
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.481391376
Short name T93
Test name
Test status
Simulation time 74684578 ps
CPU time 0.66 seconds
Started Jul 17 06:54:05 PM PDT 24
Finished Jul 17 06:54:09 PM PDT 24
Peak memory 195672 kb
Host smart-b132c21e-14ad-4c37-8cca-829ae2f1466a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481391376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.481391376
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.204998723
Short name T817
Test name
Test status
Simulation time 55573443 ps
CPU time 0.86 seconds
Started Jul 17 06:54:16 PM PDT 24
Finished Jul 17 06:54:18 PM PDT 24
Peak memory 198640 kb
Host smart-f2b5ac56-c6bd-4a04-b65e-e708722c4cab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204998723 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.204998723
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3368529256
Short name T807
Test name
Test status
Simulation time 55283667 ps
CPU time 0.62 seconds
Started Jul 17 06:54:03 PM PDT 24
Finished Jul 17 06:54:06 PM PDT 24
Peak memory 195516 kb
Host smart-3504c9bb-048c-4c7e-b8eb-ab306eb34b86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368529256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3368529256
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1970704001
Short name T751
Test name
Test status
Simulation time 13335803 ps
CPU time 0.6 seconds
Started Jul 17 06:54:04 PM PDT 24
Finished Jul 17 06:54:06 PM PDT 24
Peak memory 194912 kb
Host smart-606030fe-bf5a-4c3b-8dc7-6b7f4c6f425a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970704001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1970704001
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2180643457
Short name T788
Test name
Test status
Simulation time 26910685 ps
CPU time 0.75 seconds
Started Jul 17 06:54:03 PM PDT 24
Finished Jul 17 06:54:05 PM PDT 24
Peak memory 196888 kb
Host smart-ecd77c36-5c41-46e1-8a25-9fcb228adcaa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180643457 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2180643457
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3460003432
Short name T827
Test name
Test status
Simulation time 432779656 ps
CPU time 2.31 seconds
Started Jul 17 06:54:08 PM PDT 24
Finished Jul 17 06:54:12 PM PDT 24
Peak memory 198760 kb
Host smart-c85533e6-4ce1-4cfe-99e7-537eef339c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460003432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3460003432
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.336767105
Short name T814
Test name
Test status
Simulation time 107771074 ps
CPU time 1.53 seconds
Started Jul 17 06:54:03 PM PDT 24
Finished Jul 17 06:54:07 PM PDT 24
Peak memory 198740 kb
Host smart-00088213-d054-405c-98cc-cca3dc847919
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336767105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.336767105
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1376864789
Short name T769
Test name
Test status
Simulation time 28605362 ps
CPU time 0.59 seconds
Started Jul 17 06:54:59 PM PDT 24
Finished Jul 17 06:55:03 PM PDT 24
Peak memory 194408 kb
Host smart-5e334fd1-2e7a-4ef1-82c5-17a252080835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376864789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1376864789
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.960051262
Short name T770
Test name
Test status
Simulation time 18234784 ps
CPU time 0.66 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 194460 kb
Host smart-9200a161-def9-436a-bc4f-14fd4bfad648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960051262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.960051262
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3891987142
Short name T745
Test name
Test status
Simulation time 15441513 ps
CPU time 0.57 seconds
Started Jul 17 06:54:57 PM PDT 24
Finished Jul 17 06:55:00 PM PDT 24
Peak memory 194296 kb
Host smart-f2ea9712-9132-4ce5-b123-509cafca9058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891987142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3891987142
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1961002836
Short name T815
Test name
Test status
Simulation time 14735019 ps
CPU time 0.63 seconds
Started Jul 17 06:54:58 PM PDT 24
Finished Jul 17 06:55:02 PM PDT 24
Peak memory 195048 kb
Host smart-3a4f46d0-8c9a-4f93-b843-e52b343d84b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961002836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1961002836
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.104087339
Short name T737
Test name
Test status
Simulation time 42940399 ps
CPU time 0.58 seconds
Started Jul 17 06:54:59 PM PDT 24
Finished Jul 17 06:55:03 PM PDT 24
Peak memory 194372 kb
Host smart-4e1d0153-8ef9-4452-852d-7e8198279046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104087339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.104087339
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1075283256
Short name T795
Test name
Test status
Simulation time 13809247 ps
CPU time 0.59 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 195012 kb
Host smart-e4f4ac62-f85f-41d9-9014-97f5a2a5aeb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075283256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1075283256
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3807962824
Short name T746
Test name
Test status
Simulation time 17801993 ps
CPU time 0.64 seconds
Started Jul 17 06:56:20 PM PDT 24
Finished Jul 17 06:56:23 PM PDT 24
Peak memory 194408 kb
Host smart-07b1bb9d-86c6-454d-b62a-017c3cebde78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807962824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3807962824
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.818626763
Short name T720
Test name
Test status
Simulation time 11088120 ps
CPU time 0.59 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:25 PM PDT 24
Peak memory 195004 kb
Host smart-e0c30003-683f-4263-986b-0fc8bd993662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818626763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.818626763
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.943946275
Short name T799
Test name
Test status
Simulation time 16725544 ps
CPU time 0.64 seconds
Started Jul 17 06:56:20 PM PDT 24
Finished Jul 17 06:56:23 PM PDT 24
Peak memory 195044 kb
Host smart-3288d3ca-9ff3-4f32-bdce-2315def570a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943946275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.943946275
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3286044227
Short name T775
Test name
Test status
Simulation time 66045584 ps
CPU time 0.57 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:28 PM PDT 24
Peak memory 194360 kb
Host smart-1425c627-a8d0-4a66-bdef-d1ce4289b10f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286044227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3286044227
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1778686881
Short name T94
Test name
Test status
Simulation time 95231907 ps
CPU time 0.79 seconds
Started Jul 17 06:54:04 PM PDT 24
Finished Jul 17 06:54:07 PM PDT 24
Peak memory 197300 kb
Host smart-f7950606-7475-423d-b750-904880d5b7d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778686881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1778686881
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4232796733
Short name T89
Test name
Test status
Simulation time 59878717 ps
CPU time 2.22 seconds
Started Jul 17 06:54:05 PM PDT 24
Finished Jul 17 06:54:10 PM PDT 24
Peak memory 197496 kb
Host smart-63b476a0-6baa-44e9-a3c7-be90b23c602b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232796733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.4232796733
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2437069138
Short name T112
Test name
Test status
Simulation time 33366707 ps
CPU time 0.65 seconds
Started Jul 17 06:54:03 PM PDT 24
Finished Jul 17 06:54:05 PM PDT 24
Peak memory 195248 kb
Host smart-84fb9c22-1289-43f9-8140-9127eafc5770
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437069138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2437069138
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2263412184
Short name T729
Test name
Test status
Simulation time 32241713 ps
CPU time 1.44 seconds
Started Jul 17 06:54:02 PM PDT 24
Finished Jul 17 06:54:05 PM PDT 24
Peak memory 198768 kb
Host smart-13804b56-9d9a-455d-8a59-742848b3d598
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263412184 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2263412184
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2232453020
Short name T826
Test name
Test status
Simulation time 23179917 ps
CPU time 0.57 seconds
Started Jul 17 06:54:11 PM PDT 24
Finished Jul 17 06:54:12 PM PDT 24
Peak memory 194016 kb
Host smart-b8148b09-eed1-4f06-999e-0ea99302bc09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232453020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2232453020
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3015326561
Short name T768
Test name
Test status
Simulation time 19303983 ps
CPU time 0.62 seconds
Started Jul 17 06:54:04 PM PDT 24
Finished Jul 17 06:54:06 PM PDT 24
Peak memory 195052 kb
Host smart-81d220fe-c6af-4aa2-b084-313c8fa559f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015326561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3015326561
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.866001796
Short name T810
Test name
Test status
Simulation time 58934364 ps
CPU time 0.79 seconds
Started Jul 17 06:54:08 PM PDT 24
Finished Jul 17 06:54:10 PM PDT 24
Peak memory 197116 kb
Host smart-03eafce8-580d-45cc-ba08-18e2057b9eb7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866001796 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.866001796
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.106668271
Short name T816
Test name
Test status
Simulation time 183327993 ps
CPU time 1.12 seconds
Started Jul 17 06:54:04 PM PDT 24
Finished Jul 17 06:54:08 PM PDT 24
Peak memory 198756 kb
Host smart-8d6bb5aa-a2c9-4e8a-86d2-e6914eabde2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106668271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.106668271
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3674505476
Short name T47
Test name
Test status
Simulation time 295862852 ps
CPU time 1.08 seconds
Started Jul 17 06:54:03 PM PDT 24
Finished Jul 17 06:54:06 PM PDT 24
Peak memory 198680 kb
Host smart-1b722919-dc3a-4b28-8c44-cf12ec135213
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674505476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3674505476
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2654931942
Short name T813
Test name
Test status
Simulation time 27356545 ps
CPU time 0.61 seconds
Started Jul 17 06:56:19 PM PDT 24
Finished Jul 17 06:56:22 PM PDT 24
Peak memory 194448 kb
Host smart-c304941f-0750-41aa-8d2b-0dc7fcfafd66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654931942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2654931942
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.122474514
Short name T731
Test name
Test status
Simulation time 14216919 ps
CPU time 0.6 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 194456 kb
Host smart-3c66d348-12a3-474e-acfc-e29ef109ceda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122474514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.122474514
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.4061236616
Short name T728
Test name
Test status
Simulation time 68240248 ps
CPU time 0.67 seconds
Started Jul 17 06:56:20 PM PDT 24
Finished Jul 17 06:56:23 PM PDT 24
Peak memory 194672 kb
Host smart-6f188f02-f78f-4f28-8301-8fa4d98c1461
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061236616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.4061236616
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2667536354
Short name T796
Test name
Test status
Simulation time 16206236 ps
CPU time 0.61 seconds
Started Jul 17 06:56:20 PM PDT 24
Finished Jul 17 06:56:24 PM PDT 24
Peak memory 194356 kb
Host smart-cc817335-40f5-4205-8adc-2a393daf3ba7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667536354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2667536354
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1534859589
Short name T755
Test name
Test status
Simulation time 15102388 ps
CPU time 0.63 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:26 PM PDT 24
Peak memory 194404 kb
Host smart-188a049e-c41a-45eb-a372-b71664e58181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534859589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1534859589
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.249205735
Short name T831
Test name
Test status
Simulation time 194100587 ps
CPU time 0.67 seconds
Started Jul 17 06:56:20 PM PDT 24
Finished Jul 17 06:56:23 PM PDT 24
Peak memory 194472 kb
Host smart-7fa049aa-e088-405c-8572-2d8e185bf15a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249205735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.249205735
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2705338096
Short name T782
Test name
Test status
Simulation time 42409177 ps
CPU time 0.6 seconds
Started Jul 17 06:56:20 PM PDT 24
Finished Jul 17 06:56:23 PM PDT 24
Peak memory 194396 kb
Host smart-8b406760-e92d-4a21-92ec-47584266d740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705338096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2705338096
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.514333279
Short name T772
Test name
Test status
Simulation time 36484377 ps
CPU time 0.58 seconds
Started Jul 17 06:56:28 PM PDT 24
Finished Jul 17 06:56:36 PM PDT 24
Peak memory 194944 kb
Host smart-5b4663e1-3e8e-4d1e-b2a5-74a94e3327f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514333279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.514333279
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1156256382
Short name T725
Test name
Test status
Simulation time 61285744 ps
CPU time 0.61 seconds
Started Jul 17 06:56:19 PM PDT 24
Finished Jul 17 06:56:22 PM PDT 24
Peak memory 194296 kb
Host smart-d0b4e971-1bd0-4be0-a276-764eb3c782a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156256382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1156256382
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3225435786
Short name T821
Test name
Test status
Simulation time 55146636 ps
CPU time 0.63 seconds
Started Jul 17 06:56:28 PM PDT 24
Finished Jul 17 06:56:36 PM PDT 24
Peak memory 194332 kb
Host smart-7814ae3c-1585-4d0b-8c74-d7c00dcc030a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225435786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3225435786
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3938592236
Short name T750
Test name
Test status
Simulation time 15053414 ps
CPU time 0.66 seconds
Started Jul 17 06:54:05 PM PDT 24
Finished Jul 17 06:54:09 PM PDT 24
Peak memory 195792 kb
Host smart-42a1cde4-6b5d-4efd-adb4-3d899d5ed5b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938592236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3938592236
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3700450178
Short name T98
Test name
Test status
Simulation time 126683875 ps
CPU time 2.91 seconds
Started Jul 17 06:54:04 PM PDT 24
Finished Jul 17 06:54:09 PM PDT 24
Peak memory 197504 kb
Host smart-1ce2ba78-731c-46aa-9155-d237d3f85b03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700450178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3700450178
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3630028579
Short name T114
Test name
Test status
Simulation time 92028992 ps
CPU time 0.67 seconds
Started Jul 17 06:54:04 PM PDT 24
Finished Jul 17 06:54:06 PM PDT 24
Peak memory 195056 kb
Host smart-db3fea03-c748-4877-a9ce-c3a9e0dcbc50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630028579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3630028579
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2305244927
Short name T733
Test name
Test status
Simulation time 45408786 ps
CPU time 1.36 seconds
Started Jul 17 06:54:11 PM PDT 24
Finished Jul 17 06:54:13 PM PDT 24
Peak memory 198748 kb
Host smart-8bc57ff2-084b-4acd-b9a1-3ca12ecb76a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305244927 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2305244927
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1894604130
Short name T837
Test name
Test status
Simulation time 14969458 ps
CPU time 0.58 seconds
Started Jul 17 06:54:04 PM PDT 24
Finished Jul 17 06:54:06 PM PDT 24
Peak memory 193972 kb
Host smart-4043f29e-15d6-46ed-be60-792bc4487e1c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894604130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1894604130
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3629303020
Short name T740
Test name
Test status
Simulation time 73814735 ps
CPU time 0.59 seconds
Started Jul 17 06:54:04 PM PDT 24
Finished Jul 17 06:54:08 PM PDT 24
Peak memory 194328 kb
Host smart-c82c885a-16cf-4e28-8367-e6a600cf74df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629303020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3629303020
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2363721869
Short name T108
Test name
Test status
Simulation time 19236228 ps
CPU time 0.65 seconds
Started Jul 17 06:54:03 PM PDT 24
Finished Jul 17 06:54:05 PM PDT 24
Peak memory 195376 kb
Host smart-04e3c812-ac34-4ca9-b942-297ad7454146
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363721869 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2363721869
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.880290038
Short name T793
Test name
Test status
Simulation time 144603069 ps
CPU time 1.9 seconds
Started Jul 17 06:54:02 PM PDT 24
Finished Jul 17 06:54:04 PM PDT 24
Peak memory 198800 kb
Host smart-2487e838-34f7-416c-9817-6a975ea48ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880290038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.880290038
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.686159481
Short name T53
Test name
Test status
Simulation time 159020031 ps
CPU time 0.86 seconds
Started Jul 17 06:54:04 PM PDT 24
Finished Jul 17 06:54:07 PM PDT 24
Peak memory 197892 kb
Host smart-9742314c-caf2-4fac-b6bb-41e532a52dc3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686159481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.686159481
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.4021903331
Short name T723
Test name
Test status
Simulation time 23227236 ps
CPU time 0.59 seconds
Started Jul 17 06:56:20 PM PDT 24
Finished Jul 17 06:56:24 PM PDT 24
Peak memory 194296 kb
Host smart-112ea607-e3f6-485c-8f49-f467531e2b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021903331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.4021903331
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1941504018
Short name T738
Test name
Test status
Simulation time 42599280 ps
CPU time 0.63 seconds
Started Jul 17 06:56:28 PM PDT 24
Finished Jul 17 06:56:36 PM PDT 24
Peak memory 195056 kb
Host smart-dc89a2cc-e1f1-4f57-a43f-a47cb93bcec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941504018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1941504018
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.738714162
Short name T828
Test name
Test status
Simulation time 45811590 ps
CPU time 0.61 seconds
Started Jul 17 06:56:20 PM PDT 24
Finished Jul 17 06:56:23 PM PDT 24
Peak memory 194404 kb
Host smart-37b850f3-0348-4791-9e91-cf794cb064a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738714162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.738714162
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3686687008
Short name T822
Test name
Test status
Simulation time 21751896 ps
CPU time 0.58 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:29 PM PDT 24
Peak memory 194348 kb
Host smart-dc97cc01-e6b4-45ae-8510-2abaae9a1939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686687008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3686687008
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.376982778
Short name T802
Test name
Test status
Simulation time 61267960 ps
CPU time 0.65 seconds
Started Jul 17 06:56:20 PM PDT 24
Finished Jul 17 06:56:22 PM PDT 24
Peak memory 195116 kb
Host smart-c35761cd-f39d-4d61-9f92-58a49f89a1a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376982778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.376982778
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.631840294
Short name T800
Test name
Test status
Simulation time 14596214 ps
CPU time 0.59 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:31 PM PDT 24
Peak memory 195044 kb
Host smart-7e1f2e48-9dbc-4400-a863-3ff09499b58f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631840294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.631840294
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2913290951
Short name T830
Test name
Test status
Simulation time 15576871 ps
CPU time 0.55 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:26 PM PDT 24
Peak memory 194340 kb
Host smart-48ebabea-c06b-48df-908d-41a68cf66311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913290951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2913290951
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.923744591
Short name T823
Test name
Test status
Simulation time 14005955 ps
CPU time 0.59 seconds
Started Jul 17 06:56:19 PM PDT 24
Finished Jul 17 06:56:22 PM PDT 24
Peak memory 195012 kb
Host smart-3c25bcb5-ea1d-48d7-bc04-e46f1ae9cb72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923744591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.923744591
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1960745550
Short name T771
Test name
Test status
Simulation time 11494707 ps
CPU time 0.61 seconds
Started Jul 17 06:56:20 PM PDT 24
Finished Jul 17 06:56:24 PM PDT 24
Peak memory 194640 kb
Host smart-30be7acf-ccff-459d-85b5-7a047bc8ac1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960745550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1960745550
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.864018593
Short name T760
Test name
Test status
Simulation time 13426520 ps
CPU time 0.57 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:26 PM PDT 24
Peak memory 194356 kb
Host smart-627d2962-bc88-489a-a41b-06a32db93a98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864018593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.864018593
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3567443442
Short name T783
Test name
Test status
Simulation time 59779191 ps
CPU time 0.74 seconds
Started Jul 17 06:54:03 PM PDT 24
Finished Jul 17 06:54:05 PM PDT 24
Peak memory 198556 kb
Host smart-383deb17-c98c-4ec5-b0b2-83e82f04a1c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567443442 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3567443442
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.138382813
Short name T779
Test name
Test status
Simulation time 105098630 ps
CPU time 0.66 seconds
Started Jul 17 06:54:04 PM PDT 24
Finished Jul 17 06:54:07 PM PDT 24
Peak memory 195292 kb
Host smart-1edf4033-594d-4e66-bd90-e56f2f93a172
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138382813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.138382813
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3917972576
Short name T735
Test name
Test status
Simulation time 21807269 ps
CPU time 0.62 seconds
Started Jul 17 06:54:02 PM PDT 24
Finished Jul 17 06:54:03 PM PDT 24
Peak memory 194304 kb
Host smart-2d7a00d9-29e8-4657-a8de-4f691d3bdd9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917972576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3917972576
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.771692343
Short name T92
Test name
Test status
Simulation time 25060465 ps
CPU time 0.69 seconds
Started Jul 17 06:54:13 PM PDT 24
Finished Jul 17 06:54:14 PM PDT 24
Peak memory 196232 kb
Host smart-607ec416-7432-4453-ba01-dfe74aa92501
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771692343 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.771692343
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2704230294
Short name T786
Test name
Test status
Simulation time 61137460 ps
CPU time 1.46 seconds
Started Jul 17 06:54:08 PM PDT 24
Finished Jul 17 06:54:11 PM PDT 24
Peak memory 198788 kb
Host smart-b0346a79-8099-4b59-bb2c-8257b23373f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704230294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2704230294
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1725239465
Short name T51
Test name
Test status
Simulation time 153191618 ps
CPU time 0.87 seconds
Started Jul 17 06:54:12 PM PDT 24
Finished Jul 17 06:54:13 PM PDT 24
Peak memory 198536 kb
Host smart-dc99baa2-6364-4926-b4c0-17c1fda0a115
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725239465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1725239465
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1901113933
Short name T766
Test name
Test status
Simulation time 59654110 ps
CPU time 0.83 seconds
Started Jul 17 06:54:05 PM PDT 24
Finished Jul 17 06:54:09 PM PDT 24
Peak memory 198576 kb
Host smart-764e9d9c-ba42-47ed-b159-18afbfce7c3e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901113933 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1901113933
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1248620998
Short name T104
Test name
Test status
Simulation time 21282693 ps
CPU time 0.58 seconds
Started Jul 17 06:54:05 PM PDT 24
Finished Jul 17 06:54:08 PM PDT 24
Peak memory 193972 kb
Host smart-8185f71b-446c-4f19-b51b-38035bc2591f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248620998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1248620998
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3271919992
Short name T756
Test name
Test status
Simulation time 15402475 ps
CPU time 0.59 seconds
Started Jul 17 06:54:21 PM PDT 24
Finished Jul 17 06:54:24 PM PDT 24
Peak memory 194368 kb
Host smart-513cdcb6-ba9d-4f89-a6bb-871a3db10122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271919992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3271919992
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1752967965
Short name T778
Test name
Test status
Simulation time 20003436 ps
CPU time 0.79 seconds
Started Jul 17 06:54:03 PM PDT 24
Finished Jul 17 06:54:05 PM PDT 24
Peak memory 196956 kb
Host smart-c3676787-8c6a-4118-a222-47135389600c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752967965 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1752967965
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.50516439
Short name T744
Test name
Test status
Simulation time 23854130 ps
CPU time 1.17 seconds
Started Jul 17 06:54:18 PM PDT 24
Finished Jul 17 06:54:20 PM PDT 24
Peak memory 198740 kb
Host smart-e2620602-3412-43e8-bdca-cc2a0f5d5fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50516439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.50516439
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1579007391
Short name T45
Test name
Test status
Simulation time 263226759 ps
CPU time 1.09 seconds
Started Jul 17 06:54:18 PM PDT 24
Finished Jul 17 06:54:20 PM PDT 24
Peak memory 198788 kb
Host smart-aea300d0-5dec-4f98-93fa-a99a401e73ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579007391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1579007391
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4121652404
Short name T843
Test name
Test status
Simulation time 17141747 ps
CPU time 0.76 seconds
Started Jul 17 06:54:18 PM PDT 24
Finished Jul 17 06:54:20 PM PDT 24
Peak memory 198608 kb
Host smart-942759ba-91a0-40ec-93dc-2e9711a24381
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121652404 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.4121652404
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3490744070
Short name T763
Test name
Test status
Simulation time 42662387 ps
CPU time 0.59 seconds
Started Jul 17 06:54:20 PM PDT 24
Finished Jul 17 06:54:22 PM PDT 24
Peak memory 195956 kb
Host smart-fdfbfa44-3f18-4c88-a69d-fe24ed93d510
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490744070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3490744070
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.585787460
Short name T839
Test name
Test status
Simulation time 13965144 ps
CPU time 0.57 seconds
Started Jul 17 06:54:19 PM PDT 24
Finished Jul 17 06:54:21 PM PDT 24
Peak memory 195008 kb
Host smart-2e98f5df-936f-4664-9db3-b8d936be15d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585787460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.585787460
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1232576490
Short name T109
Test name
Test status
Simulation time 29032424 ps
CPU time 0.76 seconds
Started Jul 17 06:54:22 PM PDT 24
Finished Jul 17 06:54:25 PM PDT 24
Peak memory 196448 kb
Host smart-7bc68679-da6d-43ee-8152-bba28ccedac1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232576490 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1232576490
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2537908695
Short name T794
Test name
Test status
Simulation time 42161526 ps
CPU time 1.1 seconds
Started Jul 17 06:54:19 PM PDT 24
Finished Jul 17 06:54:22 PM PDT 24
Peak memory 198568 kb
Host smart-4a42316b-585a-4ce7-a9d4-1b9d4ec04df1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537908695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2537908695
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2900917192
Short name T115
Test name
Test status
Simulation time 298574204 ps
CPU time 1.16 seconds
Started Jul 17 06:54:21 PM PDT 24
Finished Jul 17 06:54:25 PM PDT 24
Peak memory 198696 kb
Host smart-4fb95ec3-8ea6-444e-8588-5f9f76bf2af5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900917192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2900917192
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2459939043
Short name T762
Test name
Test status
Simulation time 19650589 ps
CPU time 0.86 seconds
Started Jul 17 06:54:23 PM PDT 24
Finished Jul 17 06:54:26 PM PDT 24
Peak memory 198620 kb
Host smart-40022910-43ad-4379-86e1-6d6b5fcf716d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459939043 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2459939043
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2505662582
Short name T749
Test name
Test status
Simulation time 42418995 ps
CPU time 0.58 seconds
Started Jul 17 06:54:21 PM PDT 24
Finished Jul 17 06:54:24 PM PDT 24
Peak memory 195208 kb
Host smart-ce0f1c7e-8e0d-423d-a096-961f3118e1f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505662582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2505662582
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.4133814303
Short name T803
Test name
Test status
Simulation time 15845433 ps
CPU time 0.63 seconds
Started Jul 17 06:54:18 PM PDT 24
Finished Jul 17 06:54:19 PM PDT 24
Peak memory 195112 kb
Host smart-d96ebc5f-556b-4701-b247-d54c6158be3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133814303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.4133814303
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1985472127
Short name T836
Test name
Test status
Simulation time 15859212 ps
CPU time 0.73 seconds
Started Jul 17 06:54:21 PM PDT 24
Finished Jul 17 06:54:24 PM PDT 24
Peak memory 196668 kb
Host smart-8c9bc226-56bd-4964-a5d2-92c9b266e381
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985472127 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1985472127
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3442644991
Short name T726
Test name
Test status
Simulation time 83427076 ps
CPU time 1.3 seconds
Started Jul 17 06:54:18 PM PDT 24
Finished Jul 17 06:54:20 PM PDT 24
Peak memory 198780 kb
Host smart-b8aa260a-8bee-4ee5-8f69-ebeb57f7ab6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442644991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3442644991
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2079469048
Short name T54
Test name
Test status
Simulation time 231715101 ps
CPU time 1.56 seconds
Started Jul 17 06:54:21 PM PDT 24
Finished Jul 17 06:54:25 PM PDT 24
Peak memory 198784 kb
Host smart-fa8f93df-133c-40fd-aab3-ec00d8930560
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079469048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2079469048
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1915125456
Short name T829
Test name
Test status
Simulation time 54409022 ps
CPU time 1.28 seconds
Started Jul 17 06:54:18 PM PDT 24
Finished Jul 17 06:54:21 PM PDT 24
Peak memory 198748 kb
Host smart-75751b66-608d-45f9-a329-f3cb5d9d7c03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915125456 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1915125456
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3724962371
Short name T832
Test name
Test status
Simulation time 15712566 ps
CPU time 0.6 seconds
Started Jul 17 06:54:20 PM PDT 24
Finished Jul 17 06:54:23 PM PDT 24
Peak memory 195400 kb
Host smart-4d2f67f5-76c2-4d4d-9023-97fb1a6f96f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724962371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3724962371
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3136839424
Short name T722
Test name
Test status
Simulation time 17959832 ps
CPU time 0.59 seconds
Started Jul 17 06:54:22 PM PDT 24
Finished Jul 17 06:54:25 PM PDT 24
Peak memory 195088 kb
Host smart-404e8e63-b691-43b8-b994-db041a465969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136839424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3136839424
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2169773649
Short name T791
Test name
Test status
Simulation time 198424444 ps
CPU time 0.82 seconds
Started Jul 17 06:54:18 PM PDT 24
Finished Jul 17 06:54:20 PM PDT 24
Peak memory 196824 kb
Host smart-0a0e610f-3341-4ef6-968e-2b385a652b33
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169773649 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2169773649
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4294423391
Short name T764
Test name
Test status
Simulation time 23998434 ps
CPU time 1 seconds
Started Jul 17 06:54:24 PM PDT 24
Finished Jul 17 06:54:26 PM PDT 24
Peak memory 198508 kb
Host smart-898920e7-f93d-46df-9327-4f1c74905f40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294423391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.4294423391
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.957010588
Short name T819
Test name
Test status
Simulation time 242135445 ps
CPU time 1.1 seconds
Started Jul 17 06:54:21 PM PDT 24
Finished Jul 17 06:54:24 PM PDT 24
Peak memory 198736 kb
Host smart-14b9d562-79a1-404f-a9d2-960808e49952
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957010588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.957010588
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2568125425
Short name T609
Test name
Test status
Simulation time 31163534 ps
CPU time 0.65 seconds
Started Jul 17 06:56:53 PM PDT 24
Finished Jul 17 06:56:55 PM PDT 24
Peak memory 195532 kb
Host smart-c48de4c7-e8d3-440c-8fc4-48e1ce9f9b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568125425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2568125425
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3362501062
Short name T316
Test name
Test status
Simulation time 118178232 ps
CPU time 0.89 seconds
Started Jul 17 06:56:57 PM PDT 24
Finished Jul 17 06:56:59 PM PDT 24
Peak memory 197352 kb
Host smart-199a7452-1a6f-44aa-94be-0da77fb3a502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362501062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3362501062
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.229862646
Short name T622
Test name
Test status
Simulation time 394023035 ps
CPU time 3.51 seconds
Started Jul 17 06:56:57 PM PDT 24
Finished Jul 17 06:57:02 PM PDT 24
Peak memory 197216 kb
Host smart-7fa51f0d-1c84-4071-8922-be80d7190182
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229862646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.229862646
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2512216749
Short name T345
Test name
Test status
Simulation time 92481677 ps
CPU time 1.03 seconds
Started Jul 17 06:56:56 PM PDT 24
Finished Jul 17 06:56:58 PM PDT 24
Peak memory 197360 kb
Host smart-b1506717-1acc-4191-b3ec-d670f61e5468
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512216749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2512216749
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3492318259
Short name T163
Test name
Test status
Simulation time 167526970 ps
CPU time 1.13 seconds
Started Jul 17 06:56:55 PM PDT 24
Finished Jul 17 06:56:57 PM PDT 24
Peak memory 196448 kb
Host smart-f4208989-8db9-4d6b-b287-60ba3797d0e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492318259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3492318259
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1100660131
Short name T456
Test name
Test status
Simulation time 205903442 ps
CPU time 2.12 seconds
Started Jul 17 06:56:56 PM PDT 24
Finished Jul 17 06:56:59 PM PDT 24
Peak memory 198624 kb
Host smart-d838cdba-4df4-4b83-b018-87d9ff736dd0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100660131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1100660131
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1821597840
Short name T356
Test name
Test status
Simulation time 190621757 ps
CPU time 2.59 seconds
Started Jul 17 06:56:54 PM PDT 24
Finished Jul 17 06:56:57 PM PDT 24
Peak memory 197148 kb
Host smart-bf0ac3c9-2b68-4435-9318-fbdfe09ed0d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821597840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1821597840
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3712485169
Short name T276
Test name
Test status
Simulation time 83990007 ps
CPU time 0.67 seconds
Started Jul 17 06:56:53 PM PDT 24
Finished Jul 17 06:56:55 PM PDT 24
Peak memory 195096 kb
Host smart-b7841dd2-d848-473e-a049-1246ead4afc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712485169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3712485169
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3585475893
Short name T589
Test name
Test status
Simulation time 79059080 ps
CPU time 0.91 seconds
Started Jul 17 06:56:53 PM PDT 24
Finished Jul 17 06:56:55 PM PDT 24
Peak memory 197360 kb
Host smart-8f12d1a9-f829-4fcd-80ee-b5ff4ed65f98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585475893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3585475893
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2317738433
Short name T374
Test name
Test status
Simulation time 193480712 ps
CPU time 5.42 seconds
Started Jul 17 06:56:54 PM PDT 24
Finished Jul 17 06:57:01 PM PDT 24
Peak memory 198644 kb
Host smart-b947d787-95bf-4c97-8d10-20653eadeeac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317738433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2317738433
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.3627684921
Short name T645
Test name
Test status
Simulation time 92080666 ps
CPU time 1.38 seconds
Started Jul 17 06:56:55 PM PDT 24
Finished Jul 17 06:56:57 PM PDT 24
Peak memory 198704 kb
Host smart-c819d5f8-eaf2-44c7-ae83-c6a13bacd70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627684921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3627684921
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.660650050
Short name T553
Test name
Test status
Simulation time 17292474 ps
CPU time 0.7 seconds
Started Jul 17 06:56:54 PM PDT 24
Finished Jul 17 06:56:56 PM PDT 24
Peak memory 195644 kb
Host smart-8abea442-ffa9-45f2-8d09-4cc35d0cc8b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660650050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.660650050
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3913519524
Short name T121
Test name
Test status
Simulation time 4143172916 ps
CPU time 95.84 seconds
Started Jul 17 06:56:57 PM PDT 24
Finished Jul 17 06:58:33 PM PDT 24
Peak memory 198800 kb
Host smart-d10c69d0-93f8-40bd-a02e-9680ce3ccd99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913519524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3913519524
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1641701129
Short name T68
Test name
Test status
Simulation time 43837201768 ps
CPU time 981.98 seconds
Started Jul 17 06:56:54 PM PDT 24
Finished Jul 17 07:13:17 PM PDT 24
Peak memory 198868 kb
Host smart-d8584816-98da-4fb9-8051-6bea3dd7cca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1641701129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.1641701129
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.4107571356
Short name T182
Test name
Test status
Simulation time 21615018 ps
CPU time 0.62 seconds
Started Jul 17 06:57:02 PM PDT 24
Finished Jul 17 06:57:04 PM PDT 24
Peak memory 194672 kb
Host smart-4a87167e-2a84-4df4-a08e-4c18088f4963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107571356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.4107571356
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3265820834
Short name T631
Test name
Test status
Simulation time 66035298 ps
CPU time 0.63 seconds
Started Jul 17 06:56:56 PM PDT 24
Finished Jul 17 06:56:58 PM PDT 24
Peak memory 194640 kb
Host smart-daa9f3cc-c111-4187-8435-5bf4f2d9fb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265820834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3265820834
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2195533123
Short name T77
Test name
Test status
Simulation time 211751570 ps
CPU time 7.44 seconds
Started Jul 17 06:57:01 PM PDT 24
Finished Jul 17 06:57:09 PM PDT 24
Peak memory 198620 kb
Host smart-8c50dc6e-66e6-4edf-83b2-b411412c431b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195533123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2195533123
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1264726595
Short name T363
Test name
Test status
Simulation time 179444713 ps
CPU time 0.78 seconds
Started Jul 17 06:57:00 PM PDT 24
Finished Jul 17 06:57:01 PM PDT 24
Peak memory 196648 kb
Host smart-a9a3dd9c-049f-472d-bbd1-13f834614205
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264726595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1264726595
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1681756419
Short name T562
Test name
Test status
Simulation time 256802304 ps
CPU time 1.14 seconds
Started Jul 17 06:57:02 PM PDT 24
Finished Jul 17 06:57:04 PM PDT 24
Peak memory 196448 kb
Host smart-5086536c-c584-476f-bc76-f216d241743b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681756419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1681756419
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1854001568
Short name T646
Test name
Test status
Simulation time 405594180 ps
CPU time 2.44 seconds
Started Jul 17 06:57:02 PM PDT 24
Finished Jul 17 06:57:06 PM PDT 24
Peak memory 198632 kb
Host smart-d93dac59-f4d3-4e68-822b-f36927058ad9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854001568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1854001568
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2824249936
Short name T272
Test name
Test status
Simulation time 71501424 ps
CPU time 2.11 seconds
Started Jul 17 06:57:02 PM PDT 24
Finished Jul 17 06:57:06 PM PDT 24
Peak memory 197760 kb
Host smart-003ace24-b490-45f9-aff2-b216cbece603
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824249936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2824249936
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.304923920
Short name T447
Test name
Test status
Simulation time 159392154 ps
CPU time 1.08 seconds
Started Jul 17 06:56:54 PM PDT 24
Finished Jul 17 06:56:56 PM PDT 24
Peak memory 196716 kb
Host smart-11fe4de9-9773-44f7-b8c1-a1fac863cad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304923920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.304923920
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3282392275
Short name T365
Test name
Test status
Simulation time 488967366 ps
CPU time 1.14 seconds
Started Jul 17 06:56:56 PM PDT 24
Finished Jul 17 06:56:58 PM PDT 24
Peak memory 198796 kb
Host smart-984b5de6-64ca-4e90-b252-234a16396114
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282392275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3282392275
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1510726349
Short name T494
Test name
Test status
Simulation time 297895513 ps
CPU time 3.47 seconds
Started Jul 17 06:56:47 PM PDT 24
Finished Jul 17 06:56:50 PM PDT 24
Peak memory 198704 kb
Host smart-0201c40d-75b9-47b1-8c09-083eaf69cbc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510726349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1510726349
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1996049976
Short name T55
Test name
Test status
Simulation time 31942848 ps
CPU time 0.8 seconds
Started Jul 17 06:57:02 PM PDT 24
Finished Jul 17 06:57:03 PM PDT 24
Peak memory 214292 kb
Host smart-0ebe90cd-444e-4a8c-8feb-5359d364d01b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996049976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1996049976
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.80292553
Short name T135
Test name
Test status
Simulation time 243813708 ps
CPU time 1.13 seconds
Started Jul 17 06:56:52 PM PDT 24
Finished Jul 17 06:56:54 PM PDT 24
Peak memory 196328 kb
Host smart-de5ecc34-1dbe-4ed6-8a98-9e284767d7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80292553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.80292553
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2803861686
Short name T617
Test name
Test status
Simulation time 163339951 ps
CPU time 0.94 seconds
Started Jul 17 06:56:54 PM PDT 24
Finished Jul 17 06:56:56 PM PDT 24
Peak memory 195908 kb
Host smart-0fb5a080-7d49-4a88-b8e4-33df02d9519e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803861686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2803861686
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2281380995
Short name T366
Test name
Test status
Simulation time 29256409356 ps
CPU time 66.52 seconds
Started Jul 17 06:57:02 PM PDT 24
Finished Jul 17 06:58:10 PM PDT 24
Peak memory 198844 kb
Host smart-479cda80-4676-4a14-a6d9-2e4c4a3144b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281380995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2281380995
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2403507937
Short name T517
Test name
Test status
Simulation time 15733542 ps
CPU time 0.56 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:04 PM PDT 24
Peak memory 195392 kb
Host smart-389c7417-c014-41cc-b555-4eadbcdc8835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403507937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2403507937
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2264371170
Short name T618
Test name
Test status
Simulation time 32240336 ps
CPU time 0.82 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:57:59 PM PDT 24
Peak memory 195916 kb
Host smart-72ebee46-0237-4084-9391-2b0e7602ab36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264371170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2264371170
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.949378582
Short name T154
Test name
Test status
Simulation time 3242161843 ps
CPU time 11.75 seconds
Started Jul 17 06:57:51 PM PDT 24
Finished Jul 17 06:58:05 PM PDT 24
Peak memory 197268 kb
Host smart-528c6878-1709-47d3-9a5c-8c36b370e630
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949378582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.949378582
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1183040769
Short name T636
Test name
Test status
Simulation time 75514596 ps
CPU time 0.66 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:58:00 PM PDT 24
Peak memory 194916 kb
Host smart-4ca5e315-ed41-4b79-a59c-cc618e9cfa96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183040769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1183040769
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1707288144
Short name T236
Test name
Test status
Simulation time 141488275 ps
CPU time 0.71 seconds
Started Jul 17 06:57:50 PM PDT 24
Finished Jul 17 06:57:53 PM PDT 24
Peak memory 195756 kb
Host smart-1d3d7fd3-e9bf-42c3-9dd8-7c577e8022c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707288144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1707288144
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2935487908
Short name T186
Test name
Test status
Simulation time 357197164 ps
CPU time 3.72 seconds
Started Jul 17 06:57:57 PM PDT 24
Finished Jul 17 06:58:04 PM PDT 24
Peak memory 198756 kb
Host smart-549a5f4c-7142-4656-a88b-8a47f58a8df8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935487908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2935487908
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.921073175
Short name T572
Test name
Test status
Simulation time 162368712 ps
CPU time 2.98 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:07 PM PDT 24
Peak memory 197876 kb
Host smart-eea2713d-5e8c-450b-9eac-187893bbc311
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921073175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
921073175
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1653991540
Short name T313
Test name
Test status
Simulation time 145406372 ps
CPU time 1.1 seconds
Started Jul 17 06:57:57 PM PDT 24
Finished Jul 17 06:58:02 PM PDT 24
Peak memory 197372 kb
Host smart-95a42d34-a64e-4fdd-8908-c27449825da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653991540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1653991540
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1577168959
Short name T73
Test name
Test status
Simulation time 29014829 ps
CPU time 1.08 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:58:01 PM PDT 24
Peak memory 196520 kb
Host smart-800f8761-38b3-48c2-8ed7-393483465e50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577168959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1577168959
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.4175238418
Short name T58
Test name
Test status
Simulation time 1182555497 ps
CPU time 4.73 seconds
Started Jul 17 06:57:49 PM PDT 24
Finished Jul 17 06:57:56 PM PDT 24
Peak memory 198560 kb
Host smart-bbd4a8c5-917e-4b59-ae7a-724a157b0f82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175238418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.4175238418
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1899672268
Short name T659
Test name
Test status
Simulation time 50913975 ps
CPU time 1.43 seconds
Started Jul 17 06:57:51 PM PDT 24
Finished Jul 17 06:57:55 PM PDT 24
Peak memory 196200 kb
Host smart-87ca9ed8-c71b-42c3-ac6f-2e53d4780607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899672268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1899672268
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1670079100
Short name T652
Test name
Test status
Simulation time 279806165 ps
CPU time 1.4 seconds
Started Jul 17 06:57:50 PM PDT 24
Finished Jul 17 06:57:54 PM PDT 24
Peak memory 197416 kb
Host smart-ba01ba9a-7e99-4465-aac0-a1d254dff39e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670079100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1670079100
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1029858732
Short name T165
Test name
Test status
Simulation time 8729458669 ps
CPU time 55.94 seconds
Started Jul 17 06:57:57 PM PDT 24
Finished Jul 17 06:58:56 PM PDT 24
Peak memory 198812 kb
Host smart-ceae4572-6139-4b37-88ca-b626644c693c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029858732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1029858732
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3697294247
Short name T338
Test name
Test status
Simulation time 45167047 ps
CPU time 0.58 seconds
Started Jul 17 06:57:59 PM PDT 24
Finished Jul 17 06:58:05 PM PDT 24
Peak memory 194900 kb
Host smart-4c308a3f-7a10-4b2c-b545-6dee2e3a46a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697294247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3697294247
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.657888077
Short name T532
Test name
Test status
Simulation time 59697113 ps
CPU time 0.94 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:05 PM PDT 24
Peak memory 197996 kb
Host smart-73a3a091-7c01-4239-ac14-09d15124d6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657888077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.657888077
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.235483466
Short name T519
Test name
Test status
Simulation time 564591374 ps
CPU time 8.21 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:12 PM PDT 24
Peak memory 197660 kb
Host smart-1ec2002b-9589-4f42-ac82-038629e0bd4c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235483466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.235483466
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3508791237
Short name T223
Test name
Test status
Simulation time 116431456 ps
CPU time 0.79 seconds
Started Jul 17 06:57:57 PM PDT 24
Finished Jul 17 06:58:02 PM PDT 24
Peak memory 196532 kb
Host smart-ef058b1f-9002-46fd-94bd-17bb3f449f71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508791237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3508791237
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3580943926
Short name T174
Test name
Test status
Simulation time 195003844 ps
CPU time 1 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:05 PM PDT 24
Peak memory 197236 kb
Host smart-c2f068c1-1b3e-49c7-b8ae-67af7afe4187
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580943926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3580943926
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3911051267
Short name T319
Test name
Test status
Simulation time 58879974 ps
CPU time 2.46 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:58:02 PM PDT 24
Peak memory 198784 kb
Host smart-5bf1f9cd-b68c-49b1-af8c-44cb727d08d0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911051267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3911051267
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1763360988
Short name T708
Test name
Test status
Simulation time 508572852 ps
CPU time 1.8 seconds
Started Jul 17 06:57:55 PM PDT 24
Finished Jul 17 06:58:00 PM PDT 24
Peak memory 196696 kb
Host smart-c496b3a7-0571-498b-8f36-23b26ba6e36c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763360988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1763360988
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.25962517
Short name T388
Test name
Test status
Simulation time 26850651 ps
CPU time 1.06 seconds
Started Jul 17 06:57:59 PM PDT 24
Finished Jul 17 06:58:05 PM PDT 24
Peak memory 197228 kb
Host smart-f3d3e011-3d98-4deb-ad81-bd53f240d552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25962517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.25962517
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.301739848
Short name T586
Test name
Test status
Simulation time 99753592 ps
CPU time 1.03 seconds
Started Jul 17 06:58:02 PM PDT 24
Finished Jul 17 06:58:06 PM PDT 24
Peak memory 196552 kb
Host smart-411be903-0bc6-4b46-9b8d-d1fdfcaa714a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301739848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.301739848
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2354346621
Short name T203
Test name
Test status
Simulation time 505653834 ps
CPU time 4.17 seconds
Started Jul 17 06:58:02 PM PDT 24
Finished Jul 17 06:58:10 PM PDT 24
Peak memory 198680 kb
Host smart-b51b9e46-5c11-4c86-ab7a-458ed7280055
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354346621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2354346621
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3581702854
Short name T129
Test name
Test status
Simulation time 31057567 ps
CPU time 0.78 seconds
Started Jul 17 06:57:54 PM PDT 24
Finished Jul 17 06:57:57 PM PDT 24
Peak memory 195872 kb
Host smart-abce588e-1705-40d3-a497-633274a103a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581702854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3581702854
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.579671695
Short name T507
Test name
Test status
Simulation time 46555867 ps
CPU time 1.09 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:58:00 PM PDT 24
Peak memory 196480 kb
Host smart-88743a45-a4ba-4fa3-9836-2bf3f0177b29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579671695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.579671695
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3034009439
Short name T292
Test name
Test status
Simulation time 13275869313 ps
CPU time 66.11 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:59:09 PM PDT 24
Peak memory 198740 kb
Host smart-e074356b-7bb6-4832-ae2f-c78bf62615e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034009439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3034009439
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1817438147
Short name T64
Test name
Test status
Simulation time 15881157 ps
CPU time 0.63 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:58:00 PM PDT 24
Peak memory 194688 kb
Host smart-441e285d-a490-49c4-aa12-e7cdc487eed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817438147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1817438147
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3030833065
Short name T226
Test name
Test status
Simulation time 141610013 ps
CPU time 0.84 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:03 PM PDT 24
Peak memory 196080 kb
Host smart-ddd6c8d5-1670-4b38-9fe8-5d7ac5643910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030833065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3030833065
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3332668454
Short name T84
Test name
Test status
Simulation time 6667416506 ps
CPU time 21.14 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:25 PM PDT 24
Peak memory 197268 kb
Host smart-a1428dc6-fc51-413f-8f54-50a86ec56246
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332668454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3332668454
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1021290258
Short name T19
Test name
Test status
Simulation time 85694868 ps
CPU time 0.81 seconds
Started Jul 17 06:57:59 PM PDT 24
Finished Jul 17 06:58:05 PM PDT 24
Peak memory 196468 kb
Host smart-19010270-d449-4a3c-a879-1d46a5b3c4cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021290258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1021290258
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.305064580
Short name T318
Test name
Test status
Simulation time 46238875 ps
CPU time 1.29 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:05 PM PDT 24
Peak memory 197216 kb
Host smart-395341c6-a2a1-4871-b331-6e7994d23a5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305064580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.305064580
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.503624582
Short name T581
Test name
Test status
Simulation time 398030244 ps
CPU time 3.06 seconds
Started Jul 17 06:57:59 PM PDT 24
Finished Jul 17 06:58:07 PM PDT 24
Peak memory 197020 kb
Host smart-0578f177-8264-40b5-bc8c-4c9425b1565d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503624582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.503624582
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1108463762
Short name T689
Test name
Test status
Simulation time 826293728 ps
CPU time 1.85 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:05 PM PDT 24
Peak memory 196440 kb
Host smart-70024b82-a2a1-45a5-9359-3f1a80dc7fda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108463762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1108463762
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2881135598
Short name T538
Test name
Test status
Simulation time 374467263 ps
CPU time 1.16 seconds
Started Jul 17 06:57:59 PM PDT 24
Finished Jul 17 06:58:06 PM PDT 24
Peak memory 197244 kb
Host smart-4e93f250-8246-44e6-ba7a-43af527033b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881135598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2881135598
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.60225430
Short name T377
Test name
Test status
Simulation time 75656129 ps
CPU time 1.13 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:05 PM PDT 24
Peak memory 196452 kb
Host smart-22b1085b-38c3-4245-a596-b879fb910f0f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60225430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup_
pulldown.60225430
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.780976883
Short name T334
Test name
Test status
Simulation time 606192740 ps
CPU time 3.06 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:07 PM PDT 24
Peak memory 198664 kb
Host smart-9acdc4f5-4adb-4bc2-af06-4931b96b52b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780976883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.780976883
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1920899792
Short name T687
Test name
Test status
Simulation time 212080070 ps
CPU time 0.94 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:04 PM PDT 24
Peak memory 196488 kb
Host smart-da9848b4-b7be-4c66-b193-bb888eb21ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920899792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1920899792
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2985150655
Short name T644
Test name
Test status
Simulation time 101979602 ps
CPU time 1.36 seconds
Started Jul 17 06:57:57 PM PDT 24
Finished Jul 17 06:58:03 PM PDT 24
Peak memory 196196 kb
Host smart-37324529-3e50-4dab-8361-8665a721b351
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985150655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2985150655
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2405965032
Short name T270
Test name
Test status
Simulation time 5111540678 ps
CPU time 34.36 seconds
Started Jul 17 06:57:57 PM PDT 24
Finished Jul 17 06:58:35 PM PDT 24
Peak memory 198776 kb
Host smart-7a57d5f1-940a-41bb-ba38-9e4e054ecebd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405965032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2405965032
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1729738989
Short name T370
Test name
Test status
Simulation time 82433369235 ps
CPU time 590.48 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 07:07:50 PM PDT 24
Peak memory 198960 kb
Host smart-5c7b8d0c-d7c6-4053-95ce-9bec76e39bc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1729738989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1729738989
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1229473808
Short name T628
Test name
Test status
Simulation time 35186398 ps
CPU time 0.56 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:58:00 PM PDT 24
Peak memory 194680 kb
Host smart-6b132fa4-2ad9-4bae-be43-d2046c61cc30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229473808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1229473808
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3925443393
Short name T704
Test name
Test status
Simulation time 188845575 ps
CPU time 0.9 seconds
Started Jul 17 06:57:50 PM PDT 24
Finished Jul 17 06:57:54 PM PDT 24
Peak memory 197220 kb
Host smart-5f1e9069-c735-4c7c-8caa-76b92b094747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925443393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3925443393
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1856095394
Short name T698
Test name
Test status
Simulation time 211027154 ps
CPU time 10.81 seconds
Started Jul 17 06:57:50 PM PDT 24
Finished Jul 17 06:58:03 PM PDT 24
Peak memory 197412 kb
Host smart-8bbc2c57-f82d-4ccc-b1b2-c053234176b4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856095394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1856095394
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1013786736
Short name T661
Test name
Test status
Simulation time 260451815 ps
CPU time 1.06 seconds
Started Jul 17 06:57:51 PM PDT 24
Finished Jul 17 06:57:55 PM PDT 24
Peak memory 197136 kb
Host smart-01788aca-1063-4523-9c22-a12b21c6cf8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013786736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1013786736
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2365915377
Short name T496
Test name
Test status
Simulation time 624210818 ps
CPU time 1.19 seconds
Started Jul 17 06:57:50 PM PDT 24
Finished Jul 17 06:57:54 PM PDT 24
Peak memory 196776 kb
Host smart-426b0145-9a70-4400-b127-f2b8a349d0d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365915377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2365915377
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2521955189
Short name T153
Test name
Test status
Simulation time 263098993 ps
CPU time 3.74 seconds
Started Jul 17 06:57:57 PM PDT 24
Finished Jul 17 06:58:04 PM PDT 24
Peak memory 198672 kb
Host smart-3864ffaf-7e20-4a16-832f-340851a53bfa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521955189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2521955189
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3013168753
Short name T213
Test name
Test status
Simulation time 190975805 ps
CPU time 1.63 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:58:00 PM PDT 24
Peak memory 196808 kb
Host smart-d9d62043-fd68-46e9-bcbe-a0c5fe7b7815
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013168753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3013168753
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2161870062
Short name T719
Test name
Test status
Simulation time 17753265 ps
CPU time 0.68 seconds
Started Jul 17 06:57:57 PM PDT 24
Finished Jul 17 06:58:01 PM PDT 24
Peak memory 194840 kb
Host smart-cd6931da-f217-45d8-903f-0e57750ba6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161870062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2161870062
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2845799300
Short name T260
Test name
Test status
Simulation time 176390455 ps
CPU time 1.05 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:58:01 PM PDT 24
Peak memory 196744 kb
Host smart-c877a5e6-7744-4318-bf7c-ee20493af31f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845799300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2845799300
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2107585577
Short name T384
Test name
Test status
Simulation time 66287201 ps
CPU time 2.89 seconds
Started Jul 17 06:57:50 PM PDT 24
Finished Jul 17 06:57:55 PM PDT 24
Peak memory 198664 kb
Host smart-691857eb-562e-44a7-936c-b9861ff4bc81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107585577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2107585577
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.984362981
Short name T261
Test name
Test status
Simulation time 295753895 ps
CPU time 1.51 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:58:02 PM PDT 24
Peak memory 198732 kb
Host smart-eadde4b2-a329-4f97-bb95-62f607cf9670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984362981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.984362981
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.4073430778
Short name T327
Test name
Test status
Simulation time 163670349 ps
CPU time 0.91 seconds
Started Jul 17 06:57:57 PM PDT 24
Finished Jul 17 06:58:03 PM PDT 24
Peak memory 197112 kb
Host smart-86a7ac66-9aa7-4ee3-a8c1-bf29c25d4d25
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073430778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.4073430778
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3059998507
Short name T346
Test name
Test status
Simulation time 1953967327 ps
CPU time 22.8 seconds
Started Jul 17 06:57:54 PM PDT 24
Finished Jul 17 06:58:19 PM PDT 24
Peak memory 198656 kb
Host smart-0dfca797-f438-495f-9f5a-9d778aef8b24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059998507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3059998507
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.964459390
Short name T67
Test name
Test status
Simulation time 78257092643 ps
CPU time 1469.97 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 07:22:29 PM PDT 24
Peak memory 198848 kb
Host smart-77b46c31-806b-47b7-80bc-35e949215271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=964459390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.964459390
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3923359814
Short name T255
Test name
Test status
Simulation time 11896722 ps
CPU time 0.54 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:57:59 PM PDT 24
Peak memory 194664 kb
Host smart-49f08ddc-7e34-4485-9fc4-940deee53640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923359814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3923359814
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.865170333
Short name T621
Test name
Test status
Simulation time 29227853 ps
CPU time 0.92 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:57:59 PM PDT 24
Peak memory 196696 kb
Host smart-a160ae86-0192-4398-8202-8c21a2e47194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865170333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.865170333
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1384981460
Short name T158
Test name
Test status
Simulation time 311544151 ps
CPU time 15.08 seconds
Started Jul 17 06:57:59 PM PDT 24
Finished Jul 17 06:58:19 PM PDT 24
Peak memory 197308 kb
Host smart-405982e3-1489-4ae9-b271-8dffb29f0511
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384981460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1384981460
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3503686209
Short name T79
Test name
Test status
Simulation time 324382150 ps
CPU time 0.94 seconds
Started Jul 17 06:57:55 PM PDT 24
Finished Jul 17 06:57:59 PM PDT 24
Peak memory 197032 kb
Host smart-c02d369a-4586-4cf0-965a-3fd31f831f1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503686209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3503686209
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2548378950
Short name T155
Test name
Test status
Simulation time 50521292 ps
CPU time 0.99 seconds
Started Jul 17 06:57:50 PM PDT 24
Finished Jul 17 06:57:54 PM PDT 24
Peak memory 196840 kb
Host smart-f6f9fab8-4301-41d7-bcea-c19e33e7355c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548378950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2548378950
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3855414153
Short name T291
Test name
Test status
Simulation time 146123792 ps
CPU time 1.15 seconds
Started Jul 17 06:57:57 PM PDT 24
Finished Jul 17 06:58:04 PM PDT 24
Peak memory 198572 kb
Host smart-64d550d7-e16a-48e4-9b00-03a23f5b40aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855414153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3855414153
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3810885463
Short name T61
Test name
Test status
Simulation time 351208189 ps
CPU time 1.92 seconds
Started Jul 17 06:57:54 PM PDT 24
Finished Jul 17 06:57:59 PM PDT 24
Peak memory 196860 kb
Host smart-6656afec-8898-407b-b4e2-be55f127eb94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810885463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3810885463
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.872952930
Short name T629
Test name
Test status
Simulation time 100915862 ps
CPU time 0.95 seconds
Started Jul 17 06:57:49 PM PDT 24
Finished Jul 17 06:57:53 PM PDT 24
Peak memory 196752 kb
Host smart-f762f84c-80bd-494d-8c40-9b4e0c89ba1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872952930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.872952930
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.4096808243
Short name T590
Test name
Test status
Simulation time 35103295 ps
CPU time 0.94 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:58:01 PM PDT 24
Peak memory 196552 kb
Host smart-531acbae-63d0-4419-b437-1ca7ba995d8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096808243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.4096808243
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3145183790
Short name T324
Test name
Test status
Simulation time 239353923 ps
CPU time 2.92 seconds
Started Jul 17 06:57:55 PM PDT 24
Finished Jul 17 06:58:01 PM PDT 24
Peak memory 198604 kb
Host smart-5a09b499-bdfd-48a4-8eb8-b70ee96eb2e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145183790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3145183790
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.895749153
Short name T234
Test name
Test status
Simulation time 135256954 ps
CPU time 1.11 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:58:00 PM PDT 24
Peak memory 196860 kb
Host smart-e29bf862-b876-4fd4-8276-5ef1898020e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895749153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.895749153
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3604168428
Short name T262
Test name
Test status
Simulation time 103955559 ps
CPU time 0.89 seconds
Started Jul 17 06:57:50 PM PDT 24
Finished Jul 17 06:57:53 PM PDT 24
Peak memory 196072 kb
Host smart-368d3d9e-247c-4c08-999f-dd262d84498b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604168428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3604168428
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3521740534
Short name T503
Test name
Test status
Simulation time 21445979045 ps
CPU time 75.8 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:59:18 PM PDT 24
Peak memory 198808 kb
Host smart-275548c5-0450-4728-b88c-768dd45550eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521740534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3521740534
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1535034934
Short name T713
Test name
Test status
Simulation time 124656729150 ps
CPU time 876.7 seconds
Started Jul 17 06:57:54 PM PDT 24
Finished Jul 17 07:12:34 PM PDT 24
Peak memory 198960 kb
Host smart-027a2b01-1cdc-4fda-993b-26c6690d38cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1535034934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1535034934
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2317822438
Short name T518
Test name
Test status
Simulation time 57008023 ps
CPU time 0.57 seconds
Started Jul 17 06:58:01 PM PDT 24
Finished Jul 17 06:58:06 PM PDT 24
Peak memory 194672 kb
Host smart-3ddbb5b8-1e35-4a37-a0c6-548637de0665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317822438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2317822438
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1774746235
Short name T29
Test name
Test status
Simulation time 161454145 ps
CPU time 0.9 seconds
Started Jul 17 06:58:02 PM PDT 24
Finished Jul 17 06:58:06 PM PDT 24
Peak memory 196720 kb
Host smart-a774713d-8433-48a3-abd7-40e3502c1b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774746235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1774746235
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.620456424
Short name T337
Test name
Test status
Simulation time 230738303 ps
CPU time 12.08 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:16 PM PDT 24
Peak memory 197640 kb
Host smart-61a2ad95-f65c-49ca-a115-3790ec8e1743
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620456424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.620456424
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3385829082
Short name T478
Test name
Test status
Simulation time 38302523 ps
CPU time 0.72 seconds
Started Jul 17 06:57:52 PM PDT 24
Finished Jul 17 06:57:55 PM PDT 24
Peak memory 195424 kb
Host smart-e8b33f4b-4854-4c8c-9bdf-0214440f511d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385829082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3385829082
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3531263366
Short name T138
Test name
Test status
Simulation time 28761937 ps
CPU time 0.79 seconds
Started Jul 17 06:57:57 PM PDT 24
Finished Jul 17 06:58:03 PM PDT 24
Peak memory 195992 kb
Host smart-ef0056ed-cab5-4088-9324-db3b000d8e26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531263366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3531263366
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1323776657
Short name T434
Test name
Test status
Simulation time 101799771 ps
CPU time 1.17 seconds
Started Jul 17 06:57:59 PM PDT 24
Finished Jul 17 06:58:06 PM PDT 24
Peak memory 198568 kb
Host smart-72f57ad6-25bf-40d7-9a1d-fa71d3c3bdc7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323776657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1323776657
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1310606994
Short name T116
Test name
Test status
Simulation time 120967472 ps
CPU time 2.71 seconds
Started Jul 17 06:57:59 PM PDT 24
Finished Jul 17 06:58:07 PM PDT 24
Peak memory 197776 kb
Host smart-355752b8-5413-4c77-9783-b7978e6dd5f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310606994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1310606994
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2838389686
Short name T376
Test name
Test status
Simulation time 768982159 ps
CPU time 1.35 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:05 PM PDT 24
Peak memory 197424 kb
Host smart-3fbf25c3-8218-4b5d-a168-45b8797585aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838389686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2838389686
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1992969664
Short name T464
Test name
Test status
Simulation time 143840154 ps
CPU time 0.85 seconds
Started Jul 17 06:58:01 PM PDT 24
Finished Jul 17 06:58:06 PM PDT 24
Peak memory 196924 kb
Host smart-1b3b78a3-1d9c-436b-8d14-40eccbe8bbb9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992969664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1992969664
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.166520002
Short name T716
Test name
Test status
Simulation time 346055657 ps
CPU time 2.25 seconds
Started Jul 17 06:57:59 PM PDT 24
Finished Jul 17 06:58:06 PM PDT 24
Peak memory 198592 kb
Host smart-023cad96-1135-418d-be06-65acc03a180d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166520002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.166520002
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1838044900
Short name T131
Test name
Test status
Simulation time 57860464 ps
CPU time 0.99 seconds
Started Jul 17 06:58:02 PM PDT 24
Finished Jul 17 06:58:06 PM PDT 24
Peak memory 196324 kb
Host smart-9fc240f4-3570-4560-b754-c9daf037d687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838044900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1838044900
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2952633905
Short name T31
Test name
Test status
Simulation time 205882839 ps
CPU time 1.16 seconds
Started Jul 17 06:58:02 PM PDT 24
Finished Jul 17 06:58:07 PM PDT 24
Peak memory 197100 kb
Host smart-a69b7523-76f3-4827-906d-bd65c8301c40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952633905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2952633905
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3990876925
Short name T432
Test name
Test status
Simulation time 25832388028 ps
CPU time 172.46 seconds
Started Jul 17 06:58:01 PM PDT 24
Finished Jul 17 07:00:58 PM PDT 24
Peak memory 198808 kb
Host smart-87040d8b-a915-4f71-ab88-9542940426df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990876925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3990876925
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1359506123
Short name T563
Test name
Test status
Simulation time 11866599 ps
CPU time 0.57 seconds
Started Jul 17 06:58:17 PM PDT 24
Finished Jul 17 06:58:22 PM PDT 24
Peak memory 195376 kb
Host smart-43b5f853-4897-4f63-80f4-2a8075e79c41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359506123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1359506123
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1707711137
Short name T75
Test name
Test status
Simulation time 98726979 ps
CPU time 0.86 seconds
Started Jul 17 06:58:06 PM PDT 24
Finished Jul 17 06:58:08 PM PDT 24
Peak memory 197204 kb
Host smart-41226b52-61e2-4230-a448-6911d01cca8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707711137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1707711137
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3730479962
Short name T425
Test name
Test status
Simulation time 1196317658 ps
CPU time 27.97 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:47 PM PDT 24
Peak memory 197668 kb
Host smart-b0bcd393-1245-4702-abf7-dffc320dcc9f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730479962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3730479962
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.268950558
Short name T83
Test name
Test status
Simulation time 270225512 ps
CPU time 0.94 seconds
Started Jul 17 06:58:10 PM PDT 24
Finished Jul 17 06:58:12 PM PDT 24
Peak memory 197272 kb
Host smart-c8024799-af89-46d9-a682-209b6788adbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268950558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.268950558
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3429273325
Short name T497
Test name
Test status
Simulation time 77310832 ps
CPU time 1.07 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:19 PM PDT 24
Peak memory 196496 kb
Host smart-6d4941db-5dcb-4a7c-a405-92d424bcaddd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429273325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3429273325
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1732613757
Short name T214
Test name
Test status
Simulation time 41071180 ps
CPU time 1.62 seconds
Started Jul 17 06:58:11 PM PDT 24
Finished Jul 17 06:58:15 PM PDT 24
Peak memory 197140 kb
Host smart-3ead1516-4793-4b19-bf49-ced4870055cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732613757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1732613757
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.442868722
Short name T241
Test name
Test status
Simulation time 377008693 ps
CPU time 2.58 seconds
Started Jul 17 06:58:11 PM PDT 24
Finished Jul 17 06:58:16 PM PDT 24
Peak memory 197808 kb
Host smart-a2d3ce02-40df-47c2-bbd8-4003c4d7a0ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442868722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
442868722
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.986914329
Short name T534
Test name
Test status
Simulation time 55170038 ps
CPU time 0.99 seconds
Started Jul 17 06:58:01 PM PDT 24
Finished Jul 17 06:58:06 PM PDT 24
Peak memory 196696 kb
Host smart-bc6df8af-74c7-4c0e-b4dd-9c9542925e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986914329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.986914329
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.578195559
Short name T141
Test name
Test status
Simulation time 138516839 ps
CPU time 1.13 seconds
Started Jul 17 06:58:05 PM PDT 24
Finished Jul 17 06:58:08 PM PDT 24
Peak memory 196728 kb
Host smart-3b16fd2c-a65a-4218-89ab-30217ffeeff8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578195559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.578195559
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.993548
Short name T446
Test name
Test status
Simulation time 122669684 ps
CPU time 1.4 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:21 PM PDT 24
Peak memory 198356 kb
Host smart-c314ad22-0579-4e28-b8bc-ec795eec6938
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_wri
tes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random
_long_reg_writes_reg_reads.993548
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3316364800
Short name T253
Test name
Test status
Simulation time 53422062 ps
CPU time 0.98 seconds
Started Jul 17 06:58:00 PM PDT 24
Finished Jul 17 06:58:06 PM PDT 24
Peak memory 196248 kb
Host smart-af2a1cc2-5bff-43c5-bf65-4aaadc3fad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316364800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3316364800
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3264409783
Short name T400
Test name
Test status
Simulation time 100420029 ps
CPU time 1.47 seconds
Started Jul 17 06:58:01 PM PDT 24
Finished Jul 17 06:58:07 PM PDT 24
Peak memory 198712 kb
Host smart-c123a202-5315-48bf-adeb-0a3c533dc9ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264409783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3264409783
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.921811611
Short name T662
Test name
Test status
Simulation time 6095318568 ps
CPU time 35.53 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 06:58:52 PM PDT 24
Peak memory 198576 kb
Host smart-e5879ee5-ff55-45f3-834c-b65342bf0092
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921811611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.921811611
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.4030083337
Short name T78
Test name
Test status
Simulation time 243093678734 ps
CPU time 1329.9 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 07:20:27 PM PDT 24
Peak memory 198924 kb
Host smart-036756c0-0eb4-47ba-8b9c-c8879145237b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4030083337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.4030083337
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3372258327
Short name T387
Test name
Test status
Simulation time 45408059 ps
CPU time 0.58 seconds
Started Jul 17 06:58:12 PM PDT 24
Finished Jul 17 06:58:15 PM PDT 24
Peak memory 194708 kb
Host smart-60aac900-e974-4e53-9575-c150391a05e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372258327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3372258327
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.421319571
Short name T695
Test name
Test status
Simulation time 21641962 ps
CPU time 0.66 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 06:58:18 PM PDT 24
Peak memory 194704 kb
Host smart-1de3347e-b904-41ae-b5d9-ab5d64ca795c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421319571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.421319571
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3674975212
Short name T250
Test name
Test status
Simulation time 2167021751 ps
CPU time 24.5 seconds
Started Jul 17 06:58:09 PM PDT 24
Finished Jul 17 06:58:35 PM PDT 24
Peak memory 198772 kb
Host smart-3a7b1bb3-4f95-418a-acb2-a4854d9cce75
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674975212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3674975212
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.295983745
Short name T343
Test name
Test status
Simulation time 39587285 ps
CPU time 0.79 seconds
Started Jul 17 06:58:12 PM PDT 24
Finished Jul 17 06:58:15 PM PDT 24
Peak memory 197320 kb
Host smart-dec27f9a-e499-45cb-817f-845bcc2769c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295983745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.295983745
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2269221350
Short name T281
Test name
Test status
Simulation time 159149323 ps
CPU time 0.86 seconds
Started Jul 17 06:58:09 PM PDT 24
Finished Jul 17 06:58:11 PM PDT 24
Peak memory 196136 kb
Host smart-295e2bdd-d242-468e-9a7a-0a0c60f66e09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269221350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2269221350
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1852790401
Short name T117
Test name
Test status
Simulation time 58439097 ps
CPU time 2.33 seconds
Started Jul 17 06:58:08 PM PDT 24
Finished Jul 17 06:58:11 PM PDT 24
Peak memory 198604 kb
Host smart-6072b8f5-d991-40f5-8717-db83af526cf3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852790401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1852790401
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1261849712
Short name T217
Test name
Test status
Simulation time 207797804 ps
CPU time 2.83 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 06:58:20 PM PDT 24
Peak memory 196208 kb
Host smart-888c2418-8625-4123-8bdf-3ce4f43b03ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261849712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1261849712
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3691930091
Short name T147
Test name
Test status
Simulation time 58992473 ps
CPU time 1.25 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:21 PM PDT 24
Peak memory 197248 kb
Host smart-6f349d0d-2338-46c1-bea2-f4a5ba6edc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691930091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3691930091
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2585855853
Short name T630
Test name
Test status
Simulation time 25435871 ps
CPU time 1.05 seconds
Started Jul 17 06:58:06 PM PDT 24
Finished Jul 17 06:58:08 PM PDT 24
Peak memory 196460 kb
Host smart-8ab9e0f1-4f99-4ab7-b401-2c7b1c49f85e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585855853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2585855853
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.4086480035
Short name T461
Test name
Test status
Simulation time 576733365 ps
CPU time 4.87 seconds
Started Jul 17 06:58:06 PM PDT 24
Finished Jul 17 06:58:12 PM PDT 24
Peak memory 198684 kb
Host smart-9f42bca4-409a-4ed5-9d44-f88a64febff8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086480035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.4086480035
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.777991966
Short name T574
Test name
Test status
Simulation time 230413741 ps
CPU time 1.59 seconds
Started Jul 17 06:58:08 PM PDT 24
Finished Jul 17 06:58:11 PM PDT 24
Peak memory 197528 kb
Host smart-3f47e3b6-1a92-4ae4-9473-1470e0501414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777991966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.777991966
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1595523912
Short name T160
Test name
Test status
Simulation time 72981232 ps
CPU time 1.17 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:20 PM PDT 24
Peak memory 196180 kb
Host smart-c01194e6-58ff-4e5e-95f6-ed27806793be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595523912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1595523912
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3924026976
Short name T145
Test name
Test status
Simulation time 54772131802 ps
CPU time 187.57 seconds
Started Jul 17 06:58:15 PM PDT 24
Finished Jul 17 07:01:28 PM PDT 24
Peak memory 198776 kb
Host smart-9ee4e706-ed20-491f-809d-152fe7eb475d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924026976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3924026976
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.623876483
Short name T208
Test name
Test status
Simulation time 36496016 ps
CPU time 0.55 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:20 PM PDT 24
Peak memory 195312 kb
Host smart-dbd0f1fa-0ced-46f2-9bdb-54ee5bf5da67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623876483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.623876483
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2990858610
Short name T491
Test name
Test status
Simulation time 34360248 ps
CPU time 0.63 seconds
Started Jul 17 06:58:08 PM PDT 24
Finished Jul 17 06:58:10 PM PDT 24
Peak memory 194580 kb
Host smart-f0b16577-0843-4c8a-8c27-83954be8c7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990858610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2990858610
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.274386140
Short name T626
Test name
Test status
Simulation time 2102312677 ps
CPU time 18.3 seconds
Started Jul 17 06:58:11 PM PDT 24
Finished Jul 17 06:58:31 PM PDT 24
Peak memory 197764 kb
Host smart-f9eb05a5-b26d-4294-9ecf-4ab588a3d5dc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274386140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.274386140
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3766714694
Short name T458
Test name
Test status
Simulation time 46478431 ps
CPU time 0.64 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 06:58:18 PM PDT 24
Peak memory 195416 kb
Host smart-86d45da3-e999-4eb6-b053-c459ceb1043c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766714694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3766714694
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.308628007
Short name T632
Test name
Test status
Simulation time 109211082 ps
CPU time 1.02 seconds
Started Jul 17 06:58:08 PM PDT 24
Finished Jul 17 06:58:10 PM PDT 24
Peak memory 196780 kb
Host smart-d68947b8-69e2-4abd-a800-707da391eed6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308628007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.308628007
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2276112146
Short name T575
Test name
Test status
Simulation time 75128309 ps
CPU time 1.51 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:21 PM PDT 24
Peak memory 197052 kb
Host smart-34af961b-799a-4954-a376-24b3fa5d0ccc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276112146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2276112146
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3963656922
Short name T172
Test name
Test status
Simulation time 528308272 ps
CPU time 1.57 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 06:58:18 PM PDT 24
Peak memory 196592 kb
Host smart-b1e9ecbf-5c86-49c8-8541-9bad0d13541f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963656922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3963656922
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1485875580
Short name T663
Test name
Test status
Simulation time 41048682 ps
CPU time 1.15 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 06:58:18 PM PDT 24
Peak memory 196732 kb
Host smart-77bce0aa-27f6-44db-bcb8-04a60c81cc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485875580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1485875580
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.248439095
Short name T717
Test name
Test status
Simulation time 58847427 ps
CPU time 1.09 seconds
Started Jul 17 06:58:12 PM PDT 24
Finished Jul 17 06:58:17 PM PDT 24
Peak memory 196792 kb
Host smart-17b13c10-46a5-479d-8552-1863b177e821
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248439095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.248439095
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3336003290
Short name T150
Test name
Test status
Simulation time 237115861 ps
CPU time 2.85 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 06:58:20 PM PDT 24
Peak memory 198580 kb
Host smart-a5215612-7b48-4eb2-a0f3-b47a4c1725ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336003290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3336003290
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2473011260
Short name T28
Test name
Test status
Simulation time 597053469 ps
CPU time 1.35 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 06:58:18 PM PDT 24
Peak memory 197472 kb
Host smart-552fab60-53ca-4c2a-8d6e-ccb2fdedd659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473011260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2473011260
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1587879716
Short name T184
Test name
Test status
Simulation time 399328402 ps
CPU time 1.23 seconds
Started Jul 17 06:58:08 PM PDT 24
Finished Jul 17 06:58:10 PM PDT 24
Peak memory 197076 kb
Host smart-2beea29e-adf7-4c30-8284-95e8c6a74866
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587879716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1587879716
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3336184460
Short name T457
Test name
Test status
Simulation time 18569479704 ps
CPU time 196.26 seconds
Started Jul 17 06:58:07 PM PDT 24
Finished Jul 17 07:01:24 PM PDT 24
Peak memory 198812 kb
Host smart-a7c1954d-b03f-4fa2-9080-5f4fac211db3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336184460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3336184460
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3169875217
Short name T566
Test name
Test status
Simulation time 701257969891 ps
CPU time 735.26 seconds
Started Jul 17 06:58:06 PM PDT 24
Finished Jul 17 07:10:23 PM PDT 24
Peak memory 199204 kb
Host smart-25af88e9-fe74-46f1-92a4-22f6a92067d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3169875217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3169875217
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3436750550
Short name T490
Test name
Test status
Simulation time 12798706 ps
CPU time 0.57 seconds
Started Jul 17 06:58:11 PM PDT 24
Finished Jul 17 06:58:14 PM PDT 24
Peak memory 194576 kb
Host smart-5b1f6c42-d2a5-4eb8-9915-d503dd7ab036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436750550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3436750550
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.158889629
Short name T339
Test name
Test status
Simulation time 66154217 ps
CPU time 0.7 seconds
Started Jul 17 06:58:12 PM PDT 24
Finished Jul 17 06:58:15 PM PDT 24
Peak memory 195572 kb
Host smart-e45b7206-e7e6-478d-be84-f2953e49e467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158889629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.158889629
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2996253191
Short name T14
Test name
Test status
Simulation time 686273096 ps
CPU time 5.8 seconds
Started Jul 17 06:58:11 PM PDT 24
Finished Jul 17 06:58:18 PM PDT 24
Peak memory 197680 kb
Host smart-b572933d-2dd4-4043-841f-b76c6f3102ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996253191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2996253191
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2536167227
Short name T472
Test name
Test status
Simulation time 77839336 ps
CPU time 0.73 seconds
Started Jul 17 06:58:18 PM PDT 24
Finished Jul 17 06:58:23 PM PDT 24
Peak memory 195436 kb
Host smart-ec55d3e4-d9a4-44cd-af96-9c09797be461
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536167227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2536167227
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.4012531339
Short name T444
Test name
Test status
Simulation time 125503819 ps
CPU time 0.78 seconds
Started Jul 17 06:58:15 PM PDT 24
Finished Jul 17 06:58:21 PM PDT 24
Peak memory 196800 kb
Host smart-1809e319-8251-4613-9b15-64ff0c0cecfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012531339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.4012531339
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.699411166
Short name T382
Test name
Test status
Simulation time 72464416 ps
CPU time 1.62 seconds
Started Jul 17 06:58:11 PM PDT 24
Finished Jul 17 06:58:14 PM PDT 24
Peak memory 197388 kb
Host smart-96db1e68-d43a-496d-bc1b-84ef6c502be5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699411166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.699411166
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1904740360
Short name T514
Test name
Test status
Simulation time 62583307 ps
CPU time 1.59 seconds
Started Jul 17 06:58:18 PM PDT 24
Finished Jul 17 06:58:23 PM PDT 24
Peak memory 196748 kb
Host smart-540d27a2-abaa-42c4-bd91-fec28e2a3f38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904740360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1904740360
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2282563829
Short name T173
Test name
Test status
Simulation time 76639151 ps
CPU time 0.88 seconds
Started Jul 17 06:58:08 PM PDT 24
Finished Jul 17 06:58:10 PM PDT 24
Peak memory 197228 kb
Host smart-c95f46e0-ddcd-49d5-97e4-a611fa8db865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282563829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2282563829
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1548933054
Short name T392
Test name
Test status
Simulation time 93918823 ps
CPU time 1.19 seconds
Started Jul 17 06:58:12 PM PDT 24
Finished Jul 17 06:58:16 PM PDT 24
Peak memory 197632 kb
Host smart-348ca349-fe81-47fd-8020-2dc3c7981c71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548933054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1548933054
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.657190571
Short name T177
Test name
Test status
Simulation time 807666760 ps
CPU time 3.36 seconds
Started Jul 17 06:58:12 PM PDT 24
Finished Jul 17 06:58:19 PM PDT 24
Peak memory 198068 kb
Host smart-17ff430b-40c5-4a3c-b6b7-2305ed19b802
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657190571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.657190571
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2857682454
Short name T577
Test name
Test status
Simulation time 166810410 ps
CPU time 1 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:20 PM PDT 24
Peak memory 196260 kb
Host smart-f5d6ea6e-7d9e-44c2-88fe-5d5ac8ec946b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857682454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2857682454
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2887676741
Short name T658
Test name
Test status
Simulation time 1146110282 ps
CPU time 1.16 seconds
Started Jul 17 06:58:17 PM PDT 24
Finished Jul 17 06:58:23 PM PDT 24
Peak memory 196308 kb
Host smart-9852971f-5621-4790-9257-e5b43c1b52bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887676741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2887676741
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3141464476
Short name T486
Test name
Test status
Simulation time 45794141158 ps
CPU time 143.68 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 07:00:41 PM PDT 24
Peak memory 198820 kb
Host smart-2cb5e38f-c95a-426d-84d8-e4b864762ae8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141464476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3141464476
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1158294049
Short name T69
Test name
Test status
Simulation time 505313746486 ps
CPU time 2576.71 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 07:41:14 PM PDT 24
Peak memory 198984 kb
Host smart-11896981-7fa0-40d3-bbb7-ce5bf31a3922
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1158294049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1158294049
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.605902135
Short name T246
Test name
Test status
Simulation time 120952874 ps
CPU time 0.55 seconds
Started Jul 17 06:57:02 PM PDT 24
Finished Jul 17 06:57:03 PM PDT 24
Peak memory 195596 kb
Host smart-80aa7674-2069-407d-88f4-270a909e9c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605902135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.605902135
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.4014607996
Short name T431
Test name
Test status
Simulation time 178135923 ps
CPU time 0.9 seconds
Started Jul 17 06:57:04 PM PDT 24
Finished Jul 17 06:57:06 PM PDT 24
Peak memory 197740 kb
Host smart-ee95102a-3f11-4636-a32d-6d930bdaf22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014607996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.4014607996
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.196104548
Short name T648
Test name
Test status
Simulation time 850678326 ps
CPU time 21.82 seconds
Started Jul 17 06:57:02 PM PDT 24
Finished Jul 17 06:57:26 PM PDT 24
Peak memory 197228 kb
Host smart-87d80d20-ae04-40bc-9ab4-58e59e91480b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196104548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.196104548
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2260608238
Short name T368
Test name
Test status
Simulation time 148224015 ps
CPU time 0.76 seconds
Started Jul 17 06:57:05 PM PDT 24
Finished Jul 17 06:57:06 PM PDT 24
Peak memory 196576 kb
Host smart-0fe91f92-6c76-423d-a20f-a92d9dc39312
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260608238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2260608238
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1172374431
Short name T459
Test name
Test status
Simulation time 92394570 ps
CPU time 1.24 seconds
Started Jul 17 06:56:53 PM PDT 24
Finished Jul 17 06:56:56 PM PDT 24
Peak memory 197852 kb
Host smart-0218e6a9-fdf3-4f44-8c15-5467947f19d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172374431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1172374431
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3787723171
Short name T535
Test name
Test status
Simulation time 340233424 ps
CPU time 3.71 seconds
Started Jul 17 06:57:00 PM PDT 24
Finished Jul 17 06:57:05 PM PDT 24
Peak memory 198736 kb
Host smart-b41d9313-e7b4-461f-b0f6-9ce7a1016969
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787723171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3787723171
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2536088603
Short name T205
Test name
Test status
Simulation time 731181495 ps
CPU time 3.22 seconds
Started Jul 17 06:57:03 PM PDT 24
Finished Jul 17 06:57:08 PM PDT 24
Peak memory 198696 kb
Host smart-4afa34e6-f7a8-467f-a58c-3ece67ec35bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536088603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2536088603
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3699564484
Short name T309
Test name
Test status
Simulation time 62037023 ps
CPU time 1.21 seconds
Started Jul 17 06:57:02 PM PDT 24
Finished Jul 17 06:57:04 PM PDT 24
Peak memory 197260 kb
Host smart-38d54b10-892e-45c1-b2be-f9b93644fbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699564484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3699564484
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3407083590
Short name T367
Test name
Test status
Simulation time 178929170 ps
CPU time 1.01 seconds
Started Jul 17 06:56:55 PM PDT 24
Finished Jul 17 06:56:57 PM PDT 24
Peak memory 196900 kb
Host smart-038342ef-af72-4b29-80b1-7e9195902eaf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407083590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3407083590
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2794761441
Short name T678
Test name
Test status
Simulation time 2225094502 ps
CPU time 6.17 seconds
Started Jul 17 06:57:05 PM PDT 24
Finished Jul 17 06:57:12 PM PDT 24
Peak memory 198752 kb
Host smart-c679d298-d6e6-4a69-a438-ad55f0c6151a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794761441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2794761441
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.265849047
Short name T56
Test name
Test status
Simulation time 494352573 ps
CPU time 0.9 seconds
Started Jul 17 06:57:06 PM PDT 24
Finished Jul 17 06:57:08 PM PDT 24
Peak memory 214224 kb
Host smart-b453445e-4d56-4eff-a339-5b0eb94711c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265849047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.265849047
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1024893553
Short name T643
Test name
Test status
Simulation time 527326613 ps
CPU time 1.33 seconds
Started Jul 17 06:57:01 PM PDT 24
Finished Jul 17 06:57:03 PM PDT 24
Peak memory 196972 kb
Host smart-88012228-6afc-463e-813e-2be8b3a5b902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024893553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1024893553
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.649364568
Short name T543
Test name
Test status
Simulation time 29779421 ps
CPU time 1.04 seconds
Started Jul 17 06:57:02 PM PDT 24
Finished Jul 17 06:57:04 PM PDT 24
Peak memory 196436 kb
Host smart-5a671c6f-6089-43ff-842e-4227e6c31b0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649364568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.649364568
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1243021094
Short name T348
Test name
Test status
Simulation time 12784337259 ps
CPU time 153.31 seconds
Started Jul 17 06:57:03 PM PDT 24
Finished Jul 17 06:59:37 PM PDT 24
Peak memory 198628 kb
Host smart-0ecb873e-9717-4c1d-96c9-46aa2737901a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243021094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1243021094
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.2052975407
Short name T85
Test name
Test status
Simulation time 134545281213 ps
CPU time 794.72 seconds
Started Jul 17 06:56:54 PM PDT 24
Finished Jul 17 07:10:10 PM PDT 24
Peak memory 198920 kb
Host smart-9ec094d1-94bb-40da-af1e-96f387923f81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2052975407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.2052975407
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3553198705
Short name T714
Test name
Test status
Simulation time 75698607 ps
CPU time 0.58 seconds
Started Jul 17 06:58:15 PM PDT 24
Finished Jul 17 06:58:21 PM PDT 24
Peak memory 194636 kb
Host smart-a45415a5-391a-4123-8d38-5cc0034f2953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553198705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3553198705
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.4056785896
Short name T156
Test name
Test status
Simulation time 49568639 ps
CPU time 0.99 seconds
Started Jul 17 06:58:11 PM PDT 24
Finished Jul 17 06:58:13 PM PDT 24
Peak memory 197292 kb
Host smart-1d64fb74-5ca6-4019-a5f3-6271c21dbca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056785896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.4056785896
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2956813009
Short name T624
Test name
Test status
Simulation time 667501064 ps
CPU time 17.1 seconds
Started Jul 17 06:58:11 PM PDT 24
Finished Jul 17 06:58:31 PM PDT 24
Peak memory 197496 kb
Host smart-b492a986-04ca-439e-aa1c-502cd07746c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956813009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2956813009
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3794386929
Short name T254
Test name
Test status
Simulation time 38810451 ps
CPU time 0.65 seconds
Started Jul 17 06:58:12 PM PDT 24
Finished Jul 17 06:58:16 PM PDT 24
Peak memory 195152 kb
Host smart-93c85720-53fe-48c4-a4c2-b8200b4bdc67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794386929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3794386929
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2816019072
Short name T488
Test name
Test status
Simulation time 63415176 ps
CPU time 1.07 seconds
Started Jul 17 06:58:11 PM PDT 24
Finished Jul 17 06:58:13 PM PDT 24
Peak memory 197508 kb
Host smart-5b487f55-91be-4fc8-95d0-6a883383e101
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816019072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2816019072
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3549152675
Short name T555
Test name
Test status
Simulation time 29833128 ps
CPU time 1.21 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 06:58:19 PM PDT 24
Peak memory 197680 kb
Host smart-0f873cf0-559d-42a9-aafd-74d537d81589
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549152675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3549152675
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.437602210
Short name T127
Test name
Test status
Simulation time 863053972 ps
CPU time 3.65 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:21 PM PDT 24
Peak memory 196524 kb
Host smart-67e06ab9-d1bb-4bb3-bbe7-e81be1426e35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437602210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
437602210
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.4117769256
Short name T681
Test name
Test status
Simulation time 34255762 ps
CPU time 0.7 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:20 PM PDT 24
Peak memory 196056 kb
Host smart-fb3493e9-734e-436a-9ad6-6739daaa04d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117769256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.4117769256
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1011568913
Short name T307
Test name
Test status
Simulation time 28289175 ps
CPU time 1.03 seconds
Started Jul 17 06:58:15 PM PDT 24
Finished Jul 17 06:58:22 PM PDT 24
Peak memory 196624 kb
Host smart-4f6dd525-5078-40ee-bda3-0e580d568b0d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011568913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1011568913
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1133247205
Short name T144
Test name
Test status
Simulation time 154822771 ps
CPU time 3.78 seconds
Started Jul 17 06:58:12 PM PDT 24
Finished Jul 17 06:58:19 PM PDT 24
Peak memory 198128 kb
Host smart-cf92ba9e-8bf9-4db2-a14b-492b50017250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133247205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1133247205
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1688135900
Short name T533
Test name
Test status
Simulation time 158556818 ps
CPU time 1.21 seconds
Started Jul 17 06:58:12 PM PDT 24
Finished Jul 17 06:58:15 PM PDT 24
Peak memory 196824 kb
Host smart-f651640c-5952-4586-9365-428ee73cf81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688135900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1688135900
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.770496011
Short name T373
Test name
Test status
Simulation time 41853012 ps
CPU time 1.25 seconds
Started Jul 17 06:58:06 PM PDT 24
Finished Jul 17 06:58:08 PM PDT 24
Peak memory 196176 kb
Host smart-f4dda974-18c5-45ea-8803-429e2e5be8e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770496011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.770496011
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.773128786
Short name T502
Test name
Test status
Simulation time 10255743965 ps
CPU time 46.2 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:59:06 PM PDT 24
Peak memory 198796 kb
Host smart-6f7a6f1d-3b97-4088-a76f-6be7f993709a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773128786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.773128786
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3359162933
Short name T315
Test name
Test status
Simulation time 37694966 ps
CPU time 0.57 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 06:58:18 PM PDT 24
Peak memory 194680 kb
Host smart-f4b6365b-9fe8-45a8-939f-e6d3a1d54936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359162933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3359162933
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3163555835
Short name T300
Test name
Test status
Simulation time 40363830 ps
CPU time 0.96 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:20 PM PDT 24
Peak memory 197076 kb
Host smart-7e5a3cb2-a4a8-425d-a08f-22d69231b0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163555835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3163555835
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1756412439
Short name T467
Test name
Test status
Simulation time 269477966 ps
CPU time 8.99 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:28 PM PDT 24
Peak memory 196184 kb
Host smart-690b5358-e2cd-4427-ae0a-fc9811992eb9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756412439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1756412439
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2458894834
Short name T3
Test name
Test status
Simulation time 47494721 ps
CPU time 0.78 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:19 PM PDT 24
Peak memory 196584 kb
Host smart-da7e293a-58a1-4a5a-8aca-b01b30960213
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458894834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2458894834
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.964459985
Short name T395
Test name
Test status
Simulation time 38481196 ps
CPU time 1.07 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:19 PM PDT 24
Peak memory 196504 kb
Host smart-5ec57903-a6c1-4677-876e-e11a9589e8ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964459985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.964459985
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1801160298
Short name T484
Test name
Test status
Simulation time 158592326 ps
CPU time 2.03 seconds
Started Jul 17 06:58:17 PM PDT 24
Finished Jul 17 06:58:24 PM PDT 24
Peak memory 198596 kb
Host smart-e6e4edc4-9ebe-4d60-9d88-f1b74baf5516
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801160298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1801160298
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.204634442
Short name T60
Test name
Test status
Simulation time 43795342 ps
CPU time 0.91 seconds
Started Jul 17 06:58:18 PM PDT 24
Finished Jul 17 06:58:23 PM PDT 24
Peak memory 196200 kb
Host smart-48f4e4d6-1a45-4120-b193-bee2ec8e4991
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204634442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
204634442
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3279936041
Short name T142
Test name
Test status
Simulation time 51859334 ps
CPU time 1.19 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:21 PM PDT 24
Peak memory 197364 kb
Host smart-d3d46459-5364-46ad-8dcd-d6ec38b49732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279936041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3279936041
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1182141440
Short name T479
Test name
Test status
Simulation time 24089418 ps
CPU time 0.89 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 06:58:18 PM PDT 24
Peak memory 197304 kb
Host smart-8cdef5aa-57a7-4375-b263-1d796a47bd49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182141440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1182141440
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1630362515
Short name T1
Test name
Test status
Simulation time 2441683519 ps
CPU time 2.15 seconds
Started Jul 17 06:58:12 PM PDT 24
Finished Jul 17 06:58:17 PM PDT 24
Peak memory 198684 kb
Host smart-e08c0253-7327-46a0-b45f-4a57db70bf8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630362515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1630362515
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3010573588
Short name T567
Test name
Test status
Simulation time 274454847 ps
CPU time 1.31 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 06:58:19 PM PDT 24
Peak memory 196916 kb
Host smart-2cb7fe42-69bc-4941-b327-8bad32fda945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010573588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3010573588
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2735781794
Short name T601
Test name
Test status
Simulation time 300558799 ps
CPU time 1.48 seconds
Started Jul 17 06:58:15 PM PDT 24
Finished Jul 17 06:58:22 PM PDT 24
Peak memory 197404 kb
Host smart-f6a18ae6-db61-43d9-9d33-e0b8faddcf2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735781794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2735781794
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1597395773
Short name T350
Test name
Test status
Simulation time 18076917613 ps
CPU time 182.65 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 07:01:21 PM PDT 24
Peak memory 198744 kb
Host smart-da5ceb87-a4e4-4cde-bce7-3c2b5d3bb4c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597395773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1597395773
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2349143827
Short name T558
Test name
Test status
Simulation time 62179794 ps
CPU time 0.58 seconds
Started Jul 17 06:58:23 PM PDT 24
Finished Jul 17 06:58:24 PM PDT 24
Peak memory 194868 kb
Host smart-7c328dce-7063-42ae-a5d1-e26143e315fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349143827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2349143827
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1687548402
Short name T670
Test name
Test status
Simulation time 46121012 ps
CPU time 0.69 seconds
Started Jul 17 06:58:17 PM PDT 24
Finished Jul 17 06:58:22 PM PDT 24
Peak memory 194808 kb
Host smart-e9447b41-4edd-4810-a8d3-9bd609679441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687548402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1687548402
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1919257024
Short name T522
Test name
Test status
Simulation time 1775409849 ps
CPU time 22.09 seconds
Started Jul 17 06:58:13 PM PDT 24
Finished Jul 17 06:58:39 PM PDT 24
Peak memory 196972 kb
Host smart-a8039f7c-9d6b-4386-a774-c9c0933e2ada
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919257024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1919257024
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.4286152969
Short name T244
Test name
Test status
Simulation time 105395886 ps
CPU time 0.91 seconds
Started Jul 17 06:58:24 PM PDT 24
Finished Jul 17 06:58:25 PM PDT 24
Peak memory 196756 kb
Host smart-6903014f-b927-4b6e-aaee-ae6958a689c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286152969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.4286152969
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.997789056
Short name T614
Test name
Test status
Simulation time 439522361 ps
CPU time 1.46 seconds
Started Jul 17 06:58:15 PM PDT 24
Finished Jul 17 06:58:21 PM PDT 24
Peak memory 196504 kb
Host smart-d1a29ebc-1ae1-4162-9e16-08d081d55894
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997789056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.997789056
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2886479972
Short name T152
Test name
Test status
Simulation time 177136257 ps
CPU time 3.5 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:22 PM PDT 24
Peak memory 198624 kb
Host smart-f4864a67-2af4-4c87-9104-05892d7b6a3d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886479972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2886479972
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1457307792
Short name T137
Test name
Test status
Simulation time 235910817 ps
CPU time 2.27 seconds
Started Jul 17 06:58:15 PM PDT 24
Finished Jul 17 06:58:22 PM PDT 24
Peak memory 197536 kb
Host smart-242e2629-70d6-4437-9270-902aed705798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457307792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1457307792
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1582076844
Short name T417
Test name
Test status
Simulation time 256289566 ps
CPU time 1.08 seconds
Started Jul 17 06:58:10 PM PDT 24
Finished Jul 17 06:58:13 PM PDT 24
Peak memory 197460 kb
Host smart-bdc8e506-83db-4882-a3f1-344ac6cc4c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582076844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1582076844
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1384807198
Short name T171
Test name
Test status
Simulation time 361137744 ps
CPU time 1.3 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:21 PM PDT 24
Peak memory 197704 kb
Host smart-afe02c05-79bf-4dbb-8dbd-486dcc360d2c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384807198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1384807198
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2581387167
Short name T4
Test name
Test status
Simulation time 930546571 ps
CPU time 2.94 seconds
Started Jul 17 06:58:36 PM PDT 24
Finished Jul 17 06:58:41 PM PDT 24
Peak memory 198648 kb
Host smart-73f7a336-1e1a-4708-bcb6-0633082c8513
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581387167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2581387167
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1000082931
Short name T279
Test name
Test status
Simulation time 212029208 ps
CPU time 1.07 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:20 PM PDT 24
Peak memory 196540 kb
Host smart-aba2e4bf-4251-4b41-9708-cfda58746ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000082931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1000082931
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1317852974
Short name T157
Test name
Test status
Simulation time 203282529 ps
CPU time 1.57 seconds
Started Jul 17 06:58:14 PM PDT 24
Finished Jul 17 06:58:20 PM PDT 24
Peak memory 198672 kb
Host smart-467d2ffb-27ef-4976-b870-9135bb145247
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317852974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1317852974
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1331920590
Short name T414
Test name
Test status
Simulation time 2087393606 ps
CPU time 19.96 seconds
Started Jul 17 06:58:36 PM PDT 24
Finished Jul 17 06:58:58 PM PDT 24
Peak memory 198740 kb
Host smart-873d0c7e-5b6e-4255-813d-6b6efb8e3c5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331920590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1331920590
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3322089222
Short name T435
Test name
Test status
Simulation time 14470222 ps
CPU time 0.56 seconds
Started Jul 17 06:58:25 PM PDT 24
Finished Jul 17 06:58:27 PM PDT 24
Peak memory 195092 kb
Host smart-3b6c89ed-5b0e-40dd-8fb1-65b65a929c4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322089222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3322089222
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1044525910
Short name T556
Test name
Test status
Simulation time 20333078 ps
CPU time 0.7 seconds
Started Jul 17 06:58:37 PM PDT 24
Finished Jul 17 06:58:41 PM PDT 24
Peak memory 195340 kb
Host smart-bbef7238-4a94-47e9-9deb-286f6417f254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044525910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1044525910
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.23501058
Short name T193
Test name
Test status
Simulation time 600428873 ps
CPU time 17.78 seconds
Started Jul 17 06:58:37 PM PDT 24
Finished Jul 17 06:58:58 PM PDT 24
Peak memory 197496 kb
Host smart-53484b8f-1fac-44c6-a641-811ce70f4c38
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23501058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stress
.23501058
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2727879602
Short name T548
Test name
Test status
Simulation time 179434923 ps
CPU time 0.92 seconds
Started Jul 17 06:58:29 PM PDT 24
Finished Jul 17 06:58:30 PM PDT 24
Peak memory 197772 kb
Host smart-a6e4d3ff-aa89-4049-9b1c-7221f5d08048
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727879602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2727879602
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1070701905
Short name T440
Test name
Test status
Simulation time 90980292 ps
CPU time 0.71 seconds
Started Jul 17 06:58:26 PM PDT 24
Finished Jul 17 06:58:27 PM PDT 24
Peak memory 195064 kb
Host smart-54b0942e-5736-48e1-87fa-54d97e9e5fd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070701905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1070701905
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2533054879
Short name T539
Test name
Test status
Simulation time 415654623 ps
CPU time 2.21 seconds
Started Jul 17 06:58:31 PM PDT 24
Finished Jul 17 06:58:34 PM PDT 24
Peak memory 198732 kb
Host smart-f4f8b694-b360-4bfb-b92b-de779aababd0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533054879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2533054879
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2812265827
Short name T355
Test name
Test status
Simulation time 119767875 ps
CPU time 2.74 seconds
Started Jul 17 06:58:37 PM PDT 24
Finished Jul 17 06:58:42 PM PDT 24
Peak memory 197048 kb
Host smart-e905b34d-829d-4cb8-9ba6-64551274d652
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812265827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2812265827
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2858803751
Short name T227
Test name
Test status
Simulation time 32080381 ps
CPU time 0.81 seconds
Started Jul 17 06:58:29 PM PDT 24
Finished Jul 17 06:58:31 PM PDT 24
Peak memory 196200 kb
Host smart-3b5d6c4e-5c11-4c1a-8691-b221cc73399b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858803751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2858803751
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.586671682
Short name T164
Test name
Test status
Simulation time 298723119 ps
CPU time 1.34 seconds
Started Jul 17 06:58:24 PM PDT 24
Finished Jul 17 06:58:27 PM PDT 24
Peak memory 198712 kb
Host smart-d5fa94aa-3ad1-46ce-b8a0-d536d58a3d63
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586671682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.586671682
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1261304865
Short name T5
Test name
Test status
Simulation time 129910147 ps
CPU time 1.53 seconds
Started Jul 17 06:58:37 PM PDT 24
Finished Jul 17 06:58:41 PM PDT 24
Peak memory 198640 kb
Host smart-e462aef3-0300-44b8-a8cc-c2f39eefa266
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261304865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1261304865
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.4149520791
Short name T481
Test name
Test status
Simulation time 116455231 ps
CPU time 1.01 seconds
Started Jul 17 06:58:30 PM PDT 24
Finished Jul 17 06:58:32 PM PDT 24
Peak memory 196464 kb
Host smart-e1e2b4fb-314c-471c-ab45-c4f450332bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149520791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.4149520791
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1941590602
Short name T493
Test name
Test status
Simulation time 124554462 ps
CPU time 0.94 seconds
Started Jul 17 06:58:24 PM PDT 24
Finished Jul 17 06:58:26 PM PDT 24
Peak memory 196700 kb
Host smart-906ebe79-22f3-4381-9b8f-226e9d98e4c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941590602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1941590602
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2790994914
Short name T195
Test name
Test status
Simulation time 48763409412 ps
CPU time 74.22 seconds
Started Jul 17 06:58:25 PM PDT 24
Finished Jul 17 06:59:40 PM PDT 24
Peak memory 198792 kb
Host smart-2cdac270-5180-4f82-a624-56aaf7724e76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790994914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2790994914
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.3792926564
Short name T72
Test name
Test status
Simulation time 134704144713 ps
CPU time 2699.73 seconds
Started Jul 17 06:58:33 PM PDT 24
Finished Jul 17 07:43:34 PM PDT 24
Peak memory 198896 kb
Host smart-e5e20b3d-3b3f-4a9c-aee1-e1aff2f450c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3792926564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.3792926564
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3313079413
Short name T592
Test name
Test status
Simulation time 37301976 ps
CPU time 0.58 seconds
Started Jul 17 06:58:25 PM PDT 24
Finished Jul 17 06:58:26 PM PDT 24
Peak memory 194704 kb
Host smart-ee512253-f636-4834-b8d5-624836d841f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313079413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3313079413
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3685386580
Short name T274
Test name
Test status
Simulation time 94958723 ps
CPU time 0.95 seconds
Started Jul 17 06:58:37 PM PDT 24
Finished Jul 17 06:58:40 PM PDT 24
Peak memory 196988 kb
Host smart-418926d5-7804-43c9-99e1-90fdf484eb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685386580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3685386580
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3260616984
Short name T243
Test name
Test status
Simulation time 601757202 ps
CPU time 15.38 seconds
Started Jul 17 06:58:25 PM PDT 24
Finished Jul 17 06:58:41 PM PDT 24
Peak memory 197628 kb
Host smart-c81dd148-d853-4761-a897-61f8f3cb58cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260616984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3260616984
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.339131269
Short name T304
Test name
Test status
Simulation time 73308341 ps
CPU time 0.98 seconds
Started Jul 17 06:58:36 PM PDT 24
Finished Jul 17 06:58:39 PM PDT 24
Peak memory 197864 kb
Host smart-fac1fc01-7d85-487b-b9d4-07ff49da8eef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339131269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.339131269
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3694044444
Short name T159
Test name
Test status
Simulation time 28543680 ps
CPU time 0.89 seconds
Started Jul 17 06:58:30 PM PDT 24
Finished Jul 17 06:58:32 PM PDT 24
Peak memory 197404 kb
Host smart-7ec8a719-0bd9-4b58-b2b3-2dca692fc296
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694044444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3694044444
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1392931189
Short name T354
Test name
Test status
Simulation time 93807284 ps
CPU time 1.96 seconds
Started Jul 17 06:58:33 PM PDT 24
Finished Jul 17 06:58:36 PM PDT 24
Peak memory 198732 kb
Host smart-c4f782c4-98de-484c-8029-abb5aeb61383
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392931189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1392931189
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1471546816
Short name T552
Test name
Test status
Simulation time 759269516 ps
CPU time 2.71 seconds
Started Jul 17 06:58:37 PM PDT 24
Finished Jul 17 06:58:43 PM PDT 24
Peak memory 197000 kb
Host smart-20892862-1c3a-444d-bfea-b5f750593ecc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471546816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1471546816
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2573722123
Short name T259
Test name
Test status
Simulation time 217013118 ps
CPU time 0.74 seconds
Started Jul 17 06:58:24 PM PDT 24
Finished Jul 17 06:58:26 PM PDT 24
Peak memory 196112 kb
Host smart-a89b0efb-c123-4056-88c6-1be8ef8aef16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573722123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2573722123
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.4033587324
Short name T633
Test name
Test status
Simulation time 83600527 ps
CPU time 0.92 seconds
Started Jul 17 06:58:26 PM PDT 24
Finished Jul 17 06:58:28 PM PDT 24
Peak memory 196468 kb
Host smart-9fd5f16a-9729-413a-bd29-870ad3fdaa23
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033587324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.4033587324
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1256643614
Short name T615
Test name
Test status
Simulation time 96592841 ps
CPU time 1.56 seconds
Started Jul 17 06:58:30 PM PDT 24
Finished Jul 17 06:58:33 PM PDT 24
Peak memory 198620 kb
Host smart-5486ae50-84c7-4b9c-9cda-63558a1519f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256643614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1256643614
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.746738723
Short name T396
Test name
Test status
Simulation time 87228759 ps
CPU time 1.25 seconds
Started Jul 17 06:58:37 PM PDT 24
Finished Jul 17 06:58:40 PM PDT 24
Peak memory 197060 kb
Host smart-b4f80f9d-4aa4-4d24-b164-2492cad95f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746738723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.746738723
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3489778791
Short name T162
Test name
Test status
Simulation time 37653403 ps
CPU time 0.88 seconds
Started Jul 17 06:58:24 PM PDT 24
Finished Jul 17 06:58:26 PM PDT 24
Peak memory 197052 kb
Host smart-c1c19d80-b2aa-486a-93f7-16716e0de9ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489778791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3489778791
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.911262706
Short name T428
Test name
Test status
Simulation time 2326091504 ps
CPU time 31.75 seconds
Started Jul 17 06:58:23 PM PDT 24
Finished Jul 17 06:58:55 PM PDT 24
Peak memory 198832 kb
Host smart-bb30c1f1-c2d5-4703-99e7-b00526769920
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911262706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.911262706
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.341922791
Short name T70
Test name
Test status
Simulation time 195015370411 ps
CPU time 864.69 seconds
Started Jul 17 06:58:37 PM PDT 24
Finished Jul 17 07:13:04 PM PDT 24
Peak memory 198748 kb
Host smart-240ec028-dc1d-401c-b3cb-aa8f3e016533
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=341922791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.341922791
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.4043046105
Short name T692
Test name
Test status
Simulation time 18065210 ps
CPU time 0.62 seconds
Started Jul 17 06:58:33 PM PDT 24
Finished Jul 17 06:58:35 PM PDT 24
Peak memory 194828 kb
Host smart-98e08cfe-7b56-4cd8-b0e8-e02b8188c42c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043046105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.4043046105
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.4136171536
Short name T305
Test name
Test status
Simulation time 48496555 ps
CPU time 0.62 seconds
Started Jul 17 06:58:40 PM PDT 24
Finished Jul 17 06:58:42 PM PDT 24
Peak memory 194552 kb
Host smart-2dabc32b-dba3-4d74-be51-1874a04a65c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136171536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.4136171536
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2282095630
Short name T469
Test name
Test status
Simulation time 909773117 ps
CPU time 8.28 seconds
Started Jul 17 06:58:33 PM PDT 24
Finished Jul 17 06:58:42 PM PDT 24
Peak memory 197420 kb
Host smart-7a140fa2-7e34-4657-be5e-b5592a7b3486
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282095630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2282095630
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.901621995
Short name T606
Test name
Test status
Simulation time 45778437 ps
CPU time 0.85 seconds
Started Jul 17 06:58:40 PM PDT 24
Finished Jul 17 06:58:42 PM PDT 24
Peak memory 196692 kb
Host smart-eb1dc5a0-a2aa-4575-9ffb-e3d5999b4643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901621995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.901621995
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2808494402
Short name T426
Test name
Test status
Simulation time 61421661 ps
CPU time 1.11 seconds
Started Jul 17 06:58:33 PM PDT 24
Finished Jul 17 06:58:35 PM PDT 24
Peak memory 197176 kb
Host smart-10f28a2b-d49a-4195-8885-05f89539f043
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808494402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2808494402
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1678304713
Short name T593
Test name
Test status
Simulation time 50424522 ps
CPU time 2.25 seconds
Started Jul 17 06:58:40 PM PDT 24
Finished Jul 17 06:58:44 PM PDT 24
Peak memory 198596 kb
Host smart-0dfb27a6-a8b3-4ca5-91a9-3e22f0e66c4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678304713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1678304713
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1476990925
Short name T438
Test name
Test status
Simulation time 338470708 ps
CPU time 2.93 seconds
Started Jul 17 06:58:40 PM PDT 24
Finished Jul 17 06:58:45 PM PDT 24
Peak memory 197708 kb
Host smart-bf5fee60-3aaf-47f7-822a-c2d9f1d7b5ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476990925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1476990925
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3102079197
Short name T573
Test name
Test status
Simulation time 31852174 ps
CPU time 1.24 seconds
Started Jul 17 06:58:37 PM PDT 24
Finished Jul 17 06:58:40 PM PDT 24
Peak memory 197688 kb
Host smart-c5ff432f-100d-4e5a-ac64-b0d55d1d5d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102079197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3102079197
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2691935475
Short name T76
Test name
Test status
Simulation time 280270136 ps
CPU time 1.31 seconds
Started Jul 17 06:58:39 PM PDT 24
Finished Jul 17 06:58:42 PM PDT 24
Peak memory 197716 kb
Host smart-e8ead33a-c10c-488a-864c-ecd56db1c4e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691935475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2691935475
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2667117223
Short name T257
Test name
Test status
Simulation time 145139798 ps
CPU time 3.54 seconds
Started Jul 17 06:58:32 PM PDT 24
Finished Jul 17 06:58:37 PM PDT 24
Peak memory 198600 kb
Host smart-f9db7a35-0a03-44c4-b476-049b6b7f60af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667117223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2667117223
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.4152988919
Short name T352
Test name
Test status
Simulation time 66119880 ps
CPU time 1.03 seconds
Started Jul 17 06:58:36 PM PDT 24
Finished Jul 17 06:58:39 PM PDT 24
Peak memory 196988 kb
Host smart-5a6c730b-435d-479f-9cf0-159249cd1ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152988919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.4152988919
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1096640193
Short name T429
Test name
Test status
Simulation time 73768577 ps
CPU time 1.13 seconds
Started Jul 17 06:58:37 PM PDT 24
Finished Jul 17 06:58:40 PM PDT 24
Peak memory 196476 kb
Host smart-76dbb54d-7144-4e7a-a702-97ed7d9c7739
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096640193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1096640193
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1485595472
Short name T361
Test name
Test status
Simulation time 12542794313 ps
CPU time 77.78 seconds
Started Jul 17 06:58:40 PM PDT 24
Finished Jul 17 06:59:59 PM PDT 24
Peak memory 198824 kb
Host smart-d5a0092a-e915-426d-88ef-dd169f4eedb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485595472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1485595472
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1787107186
Short name T183
Test name
Test status
Simulation time 61274971 ps
CPU time 0.56 seconds
Started Jul 17 06:58:30 PM PDT 24
Finished Jul 17 06:58:32 PM PDT 24
Peak memory 194616 kb
Host smart-e88b983f-87b3-4094-9e2d-22a7fc8e41e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787107186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1787107186
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2978232658
Short name T357
Test name
Test status
Simulation time 187522166 ps
CPU time 0.91 seconds
Started Jul 17 06:58:37 PM PDT 24
Finished Jul 17 06:58:40 PM PDT 24
Peak memory 197208 kb
Host smart-dfa39682-c54a-4405-a0e2-57215658b36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978232658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2978232658
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1221693361
Short name T584
Test name
Test status
Simulation time 2192098867 ps
CPU time 22.14 seconds
Started Jul 17 06:58:29 PM PDT 24
Finished Jul 17 06:58:52 PM PDT 24
Peak memory 197788 kb
Host smart-300edb80-6527-430b-b64a-815b99f7ca32
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221693361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1221693361
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2711129009
Short name T215
Test name
Test status
Simulation time 197274071 ps
CPU time 0.75 seconds
Started Jul 17 06:58:36 PM PDT 24
Finished Jul 17 06:58:37 PM PDT 24
Peak memory 197284 kb
Host smart-bdf0a0e1-72f3-417a-a566-03504605aaa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711129009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2711129009
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3377106942
Short name T547
Test name
Test status
Simulation time 207137439 ps
CPU time 1.44 seconds
Started Jul 17 06:58:36 PM PDT 24
Finished Jul 17 06:58:38 PM PDT 24
Peak memory 197740 kb
Host smart-c3504b37-8fce-4e28-82af-f402032dff3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377106942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3377106942
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.451565111
Short name T452
Test name
Test status
Simulation time 89318261 ps
CPU time 3.44 seconds
Started Jul 17 06:58:36 PM PDT 24
Finished Jul 17 06:58:42 PM PDT 24
Peak memory 198720 kb
Host smart-287fd5a9-bf6d-40de-a7d9-95a25ced46d3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451565111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.451565111
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3399740091
Short name T59
Test name
Test status
Simulation time 413219053 ps
CPU time 1.56 seconds
Started Jul 17 06:58:37 PM PDT 24
Finished Jul 17 06:58:41 PM PDT 24
Peak memory 196724 kb
Host smart-73007b77-1d36-4192-bd9e-c2919eeb81a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399740091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3399740091
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.721465129
Short name T677
Test name
Test status
Simulation time 370453249 ps
CPU time 1.15 seconds
Started Jul 17 06:58:26 PM PDT 24
Finished Jul 17 06:58:28 PM PDT 24
Peak memory 197808 kb
Host smart-fd493710-f656-418f-b3ef-8299be2cb2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721465129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.721465129
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.412583097
Short name T474
Test name
Test status
Simulation time 48942699 ps
CPU time 0.63 seconds
Started Jul 17 06:58:26 PM PDT 24
Finished Jul 17 06:58:27 PM PDT 24
Peak memory 195616 kb
Host smart-96318b53-d875-4019-bd34-01ed5e05359b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412583097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.412583097
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3844434766
Short name T679
Test name
Test status
Simulation time 77536647 ps
CPU time 1.51 seconds
Started Jul 17 06:58:26 PM PDT 24
Finished Jul 17 06:58:29 PM PDT 24
Peak memory 198652 kb
Host smart-57cc8dbd-283e-4723-8c48-67195ba0332d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844434766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3844434766
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.19946471
Short name T140
Test name
Test status
Simulation time 277492745 ps
CPU time 1.16 seconds
Started Jul 17 06:58:40 PM PDT 24
Finished Jul 17 06:58:43 PM PDT 24
Peak memory 196464 kb
Host smart-4bb7d4d9-dc5b-4c3a-8817-d638f8e3bff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19946471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.19946471
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2909292614
Short name T231
Test name
Test status
Simulation time 55342521 ps
CPU time 1.33 seconds
Started Jul 17 06:58:40 PM PDT 24
Finished Jul 17 06:58:43 PM PDT 24
Peak memory 196264 kb
Host smart-acde503e-98a0-42a1-a32f-919415bee4b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909292614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2909292614
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1134449048
Short name T604
Test name
Test status
Simulation time 7937997696 ps
CPU time 111.26 seconds
Started Jul 17 06:58:36 PM PDT 24
Finished Jul 17 07:00:28 PM PDT 24
Peak memory 198840 kb
Host smart-f93c8fc0-e1d3-40f7-a737-a1e4589b62bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134449048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1134449048
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.2847761915
Short name T66
Test name
Test status
Simulation time 45540333928 ps
CPU time 581.18 seconds
Started Jul 17 06:58:36 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 199020 kb
Host smart-0204d56b-7273-4291-b6eb-4f24762bce1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2847761915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.2847761915
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.460981574
Short name T485
Test name
Test status
Simulation time 66037305 ps
CPU time 0.56 seconds
Started Jul 17 06:58:54 PM PDT 24
Finished Jul 17 06:58:55 PM PDT 24
Peak memory 194908 kb
Host smart-655e759c-be2b-4ac8-9e48-6278591f8102
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460981574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.460981574
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1674048262
Short name T294
Test name
Test status
Simulation time 145833844 ps
CPU time 0.96 seconds
Started Jul 17 06:58:36 PM PDT 24
Finished Jul 17 06:58:39 PM PDT 24
Peak memory 197156 kb
Host smart-06252083-3724-42be-b230-862547a8ae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674048262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1674048262
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.881786253
Short name T492
Test name
Test status
Simulation time 142224186 ps
CPU time 6.63 seconds
Started Jul 17 06:58:36 PM PDT 24
Finished Jul 17 06:58:45 PM PDT 24
Peak memory 196208 kb
Host smart-90c60850-6bdd-4b43-90e3-2bcc0b0adfc8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881786253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.881786253
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.969514992
Short name T529
Test name
Test status
Simulation time 301644471 ps
CPU time 1.03 seconds
Started Jul 17 06:58:51 PM PDT 24
Finished Jul 17 06:58:54 PM PDT 24
Peak memory 198732 kb
Host smart-617ee3d9-8674-4063-9428-cf96b2d7b7c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969514992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.969514992
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.4191201392
Short name T379
Test name
Test status
Simulation time 29974360 ps
CPU time 0.95 seconds
Started Jul 17 06:58:28 PM PDT 24
Finished Jul 17 06:58:29 PM PDT 24
Peak memory 197496 kb
Host smart-76c72632-902b-4f97-9c7c-42a85c9cae02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191201392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.4191201392
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2950149509
Short name T453
Test name
Test status
Simulation time 21016462 ps
CPU time 0.98 seconds
Started Jul 17 06:58:36 PM PDT 24
Finished Jul 17 06:58:39 PM PDT 24
Peak memory 196708 kb
Host smart-57e361eb-a4c8-42f7-9b6d-58dd70c487e9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950149509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2950149509
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2367794446
Short name T700
Test name
Test status
Simulation time 559598141 ps
CPU time 2.38 seconds
Started Jul 17 06:58:28 PM PDT 24
Finished Jul 17 06:58:31 PM PDT 24
Peak memory 197260 kb
Host smart-81aa49ec-4967-4661-b614-31d8f9523f5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367794446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2367794446
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.763255917
Short name T701
Test name
Test status
Simulation time 302427049 ps
CPU time 1.4 seconds
Started Jul 17 06:58:36 PM PDT 24
Finished Jul 17 06:58:39 PM PDT 24
Peak memory 197824 kb
Host smart-b2d02d20-ae20-46c1-8508-76a56b1e02dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763255917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.763255917
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1398419944
Short name T509
Test name
Test status
Simulation time 35369121 ps
CPU time 1.28 seconds
Started Jul 17 06:58:36 PM PDT 24
Finished Jul 17 06:58:39 PM PDT 24
Peak memory 197684 kb
Host smart-771775aa-c706-4396-8d8b-eeb6b73cf4e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398419944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1398419944
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.792796086
Short name T612
Test name
Test status
Simulation time 551345434 ps
CPU time 5.97 seconds
Started Jul 17 06:58:47 PM PDT 24
Finished Jul 17 06:58:53 PM PDT 24
Peak memory 198684 kb
Host smart-59a94462-86ab-4866-923e-f63a09fb41cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792796086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.792796086
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.260159750
Short name T166
Test name
Test status
Simulation time 36358785 ps
CPU time 1.15 seconds
Started Jul 17 06:58:37 PM PDT 24
Finished Jul 17 06:58:40 PM PDT 24
Peak memory 197248 kb
Host smart-331be9d5-be21-41b6-b23c-9bfeab7cdfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260159750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.260159750
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3344244424
Short name T225
Test name
Test status
Simulation time 231411211 ps
CPU time 1.14 seconds
Started Jul 17 06:58:52 PM PDT 24
Finished Jul 17 06:58:55 PM PDT 24
Peak memory 196200 kb
Host smart-9362f7ef-e94f-489b-9e04-9b69756929ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344244424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3344244424
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.2382037766
Short name T680
Test name
Test status
Simulation time 65470878496 ps
CPU time 776.2 seconds
Started Jul 17 06:58:49 PM PDT 24
Finished Jul 17 07:11:47 PM PDT 24
Peak memory 198960 kb
Host smart-95eb0c6e-bb06-4dee-aec9-c4b0f396eb17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2382037766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.2382037766
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2007382613
Short name T133
Test name
Test status
Simulation time 17036433 ps
CPU time 0.63 seconds
Started Jul 17 06:58:49 PM PDT 24
Finished Jul 17 06:58:50 PM PDT 24
Peak memory 195536 kb
Host smart-2347d0c3-a3eb-4b73-b1d0-9e964df27948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007382613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2007382613
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2000255617
Short name T510
Test name
Test status
Simulation time 49131396 ps
CPU time 0.69 seconds
Started Jul 17 06:58:53 PM PDT 24
Finished Jul 17 06:58:54 PM PDT 24
Peak memory 194824 kb
Host smart-9631bf99-3e7c-4294-a488-f7e8bc1e44c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000255617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2000255617
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1278183246
Short name T386
Test name
Test status
Simulation time 909713017 ps
CPU time 16.69 seconds
Started Jul 17 06:58:49 PM PDT 24
Finished Jul 17 06:59:07 PM PDT 24
Peak memory 197488 kb
Host smart-0c099b46-12ea-456c-b98b-836c720fd77b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278183246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1278183246
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.4257509601
Short name T168
Test name
Test status
Simulation time 227948700 ps
CPU time 0.93 seconds
Started Jul 17 06:58:51 PM PDT 24
Finished Jul 17 06:58:53 PM PDT 24
Peak memory 197240 kb
Host smart-6fc17604-f7a0-4e72-a6d6-d5d31bc99558
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257509601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.4257509601
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1316056648
Short name T265
Test name
Test status
Simulation time 25455188 ps
CPU time 0.83 seconds
Started Jul 17 06:58:55 PM PDT 24
Finished Jul 17 06:58:57 PM PDT 24
Peak memory 196872 kb
Host smart-2814e4c5-95d1-4d4b-a0f1-fc9030f823e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316056648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1316056648
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.699904256
Short name T671
Test name
Test status
Simulation time 162955526 ps
CPU time 3.55 seconds
Started Jul 17 06:58:49 PM PDT 24
Finished Jul 17 06:58:53 PM PDT 24
Peak memory 197152 kb
Host smart-6a0dc977-bccf-48a9-a742-cc80057dea8e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699904256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.699904256
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.379299681
Short name T149
Test name
Test status
Simulation time 157481221 ps
CPU time 1.47 seconds
Started Jul 17 06:58:53 PM PDT 24
Finished Jul 17 06:58:55 PM PDT 24
Peak memory 197344 kb
Host smart-cce73f89-efb1-44fc-885f-931061f0ab6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379299681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
379299681
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2852240822
Short name T336
Test name
Test status
Simulation time 201167435 ps
CPU time 1.04 seconds
Started Jul 17 06:58:50 PM PDT 24
Finished Jul 17 06:58:52 PM PDT 24
Peak memory 196632 kb
Host smart-365bc209-d7f5-47d8-9297-4e4ece0ceef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852240822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2852240822
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.4092469179
Short name T672
Test name
Test status
Simulation time 20536517 ps
CPU time 0.83 seconds
Started Jul 17 06:58:50 PM PDT 24
Finished Jul 17 06:58:52 PM PDT 24
Peak memory 196920 kb
Host smart-de0f1eae-68d0-44f1-829e-422c4dd5c3b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092469179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.4092469179
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2087988302
Short name T639
Test name
Test status
Simulation time 214113835 ps
CPU time 4.7 seconds
Started Jul 17 06:58:54 PM PDT 24
Finished Jul 17 06:58:59 PM PDT 24
Peak memory 198612 kb
Host smart-87b46017-61c5-4885-a029-aa634938c948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087988302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2087988302
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.733220458
Short name T394
Test name
Test status
Simulation time 103163229 ps
CPU time 1.09 seconds
Started Jul 17 06:58:55 PM PDT 24
Finished Jul 17 06:58:58 PM PDT 24
Peak memory 197232 kb
Host smart-65612afb-fd7b-48b5-8caa-181855bfcd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733220458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.733220458
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2717535817
Short name T347
Test name
Test status
Simulation time 69599685 ps
CPU time 1.31 seconds
Started Jul 17 06:58:48 PM PDT 24
Finished Jul 17 06:58:50 PM PDT 24
Peak memory 196340 kb
Host smart-e53d2d7b-b583-4cbc-bd8e-568abd61765d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717535817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2717535817
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1635658399
Short name T627
Test name
Test status
Simulation time 13699802171 ps
CPU time 191.32 seconds
Started Jul 17 06:58:55 PM PDT 24
Finished Jul 17 07:02:07 PM PDT 24
Peak memory 198764 kb
Host smart-af0c3611-3ab8-4d01-b136-497c417bdc93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635658399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1635658399
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3619469093
Short name T501
Test name
Test status
Simulation time 24798693487 ps
CPU time 645.08 seconds
Started Jul 17 06:58:55 PM PDT 24
Finished Jul 17 07:09:41 PM PDT 24
Peak memory 198912 kb
Host smart-64f9e4b9-a93e-4d3d-98a0-f24121719592
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3619469093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3619469093
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3986849585
Short name T462
Test name
Test status
Simulation time 46461769 ps
CPU time 0.55 seconds
Started Jul 17 06:58:55 PM PDT 24
Finished Jul 17 06:58:56 PM PDT 24
Peak memory 194796 kb
Host smart-79ca5f9b-8029-4f1a-a863-24826eb3119e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986849585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3986849585
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4213083968
Short name T498
Test name
Test status
Simulation time 36230043 ps
CPU time 0.78 seconds
Started Jul 17 06:58:56 PM PDT 24
Finished Jul 17 06:58:58 PM PDT 24
Peak memory 196740 kb
Host smart-0cd7163a-75a5-4e61-882e-dfe1daab41d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213083968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4213083968
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1451563644
Short name T128
Test name
Test status
Simulation time 1975330721 ps
CPU time 14.11 seconds
Started Jul 17 06:58:50 PM PDT 24
Finished Jul 17 06:59:05 PM PDT 24
Peak memory 197568 kb
Host smart-ad5fa419-edad-4a88-9b8a-2be9facbbca0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451563644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1451563644
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.539263535
Short name T18
Test name
Test status
Simulation time 98800871 ps
CPU time 1.01 seconds
Started Jul 17 06:58:50 PM PDT 24
Finished Jul 17 06:58:52 PM PDT 24
Peak memory 197516 kb
Host smart-423e8849-40d2-4e24-af0e-80d079ab0767
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539263535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.539263535
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.968170741
Short name T326
Test name
Test status
Simulation time 970276006 ps
CPU time 0.94 seconds
Started Jul 17 06:58:51 PM PDT 24
Finished Jul 17 06:58:53 PM PDT 24
Peak memory 197448 kb
Host smart-799cd721-11ef-4041-b5a3-6cd395870c51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968170741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.968170741
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.4198836092
Short name T442
Test name
Test status
Simulation time 155886303 ps
CPU time 1.92 seconds
Started Jul 17 06:58:49 PM PDT 24
Finished Jul 17 06:58:52 PM PDT 24
Peak memory 198756 kb
Host smart-e85bd386-cc5e-4f8d-a073-3e63057e89e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198836092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.4198836092
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3612830828
Short name T238
Test name
Test status
Simulation time 136915034 ps
CPU time 3.01 seconds
Started Jul 17 06:58:49 PM PDT 24
Finished Jul 17 06:58:52 PM PDT 24
Peak memory 198744 kb
Host smart-98e26f25-a2b8-4e27-a0ef-51625d8f561c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612830828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3612830828
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2593144224
Short name T506
Test name
Test status
Simulation time 63920198 ps
CPU time 0.89 seconds
Started Jul 17 06:58:47 PM PDT 24
Finished Jul 17 06:58:49 PM PDT 24
Peak memory 197216 kb
Host smart-ba5ba90f-7bb7-433e-ba6e-8741b55a00b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593144224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2593144224
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2765654777
Short name T204
Test name
Test status
Simulation time 176969637 ps
CPU time 1.23 seconds
Started Jul 17 06:58:49 PM PDT 24
Finished Jul 17 06:58:51 PM PDT 24
Peak memory 196808 kb
Host smart-9f63baad-1479-4d25-9dcf-acc681761233
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765654777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2765654777
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1745211724
Short name T295
Test name
Test status
Simulation time 253606134 ps
CPU time 3.81 seconds
Started Jul 17 06:58:49 PM PDT 24
Finished Jul 17 06:58:54 PM PDT 24
Peak memory 198656 kb
Host smart-d02cde9e-69fd-499a-a115-a8d55625e5e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745211724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1745211724
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1341743703
Short name T196
Test name
Test status
Simulation time 341931813 ps
CPU time 1.3 seconds
Started Jul 17 06:58:50 PM PDT 24
Finished Jul 17 06:58:52 PM PDT 24
Peak memory 196248 kb
Host smart-341f6a98-1edc-48f8-9822-6893743922e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341743703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1341743703
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3078877811
Short name T283
Test name
Test status
Simulation time 98126002 ps
CPU time 1.07 seconds
Started Jul 17 06:58:55 PM PDT 24
Finished Jul 17 06:58:57 PM PDT 24
Peak memory 196208 kb
Host smart-94a3aa0b-d5c9-44f6-97d2-c9547f5c6c01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078877811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3078877811
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1731674083
Short name T280
Test name
Test status
Simulation time 3810120184 ps
CPU time 91.44 seconds
Started Jul 17 06:58:54 PM PDT 24
Finished Jul 17 07:00:26 PM PDT 24
Peak memory 198788 kb
Host smart-5bdb8be7-2e1b-4210-b0bc-4b223ad660d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731674083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1731674083
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.2288797753
Short name T468
Test name
Test status
Simulation time 215151793668 ps
CPU time 1362.4 seconds
Started Jul 17 06:58:50 PM PDT 24
Finished Jul 17 07:21:34 PM PDT 24
Peak memory 198968 kb
Host smart-3f7e8a19-417b-45ea-9f7e-aa4fc70658fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2288797753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.2288797753
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.4289751594
Short name T380
Test name
Test status
Simulation time 53243271 ps
CPU time 0.58 seconds
Started Jul 17 06:57:17 PM PDT 24
Finished Jul 17 06:57:19 PM PDT 24
Peak memory 194704 kb
Host smart-80a5e0b1-cb45-4db2-84e4-4f9a1386e7c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289751594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.4289751594
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2187718394
Short name T684
Test name
Test status
Simulation time 24607316 ps
CPU time 0.73 seconds
Started Jul 17 06:57:06 PM PDT 24
Finished Jul 17 06:57:08 PM PDT 24
Peak memory 195492 kb
Host smart-e43d745c-c620-41c5-939c-bc0537d3c635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187718394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2187718394
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.213634861
Short name T331
Test name
Test status
Simulation time 968496312 ps
CPU time 15.32 seconds
Started Jul 17 06:57:06 PM PDT 24
Finished Jul 17 06:57:22 PM PDT 24
Peak memory 198696 kb
Host smart-ce0e7a77-ed14-4466-be5c-56c6a89ffb34
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213634861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.213634861
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2534667148
Short name T178
Test name
Test status
Simulation time 74928490 ps
CPU time 0.99 seconds
Started Jul 17 06:57:06 PM PDT 24
Finished Jul 17 06:57:08 PM PDT 24
Peak memory 197260 kb
Host smart-bbad6806-d177-4e13-9990-aed1772414d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534667148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2534667148
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3094709382
Short name T718
Test name
Test status
Simulation time 130140497 ps
CPU time 1.1 seconds
Started Jul 17 06:57:06 PM PDT 24
Finished Jul 17 06:57:09 PM PDT 24
Peak memory 196536 kb
Host smart-87633953-1ad6-447f-84de-3daba2641b6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094709382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3094709382
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2231509865
Short name T271
Test name
Test status
Simulation time 94631853 ps
CPU time 1.96 seconds
Started Jul 17 06:57:06 PM PDT 24
Finished Jul 17 06:57:09 PM PDT 24
Peak memory 198700 kb
Host smart-c0c763cd-5d63-497c-b07d-cf5b41e73e75
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231509865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2231509865
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1985236600
Short name T583
Test name
Test status
Simulation time 642793935 ps
CPU time 3.27 seconds
Started Jul 17 06:57:06 PM PDT 24
Finished Jul 17 06:57:11 PM PDT 24
Peak memory 197212 kb
Host smart-64c4b56c-11c2-4b83-81de-c2a844c81b29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985236600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1985236600
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3319388328
Short name T625
Test name
Test status
Simulation time 316445483 ps
CPU time 1.21 seconds
Started Jul 17 06:57:06 PM PDT 24
Finished Jul 17 06:57:08 PM PDT 24
Peak memory 197804 kb
Host smart-684acf40-93f6-40fd-a7d9-44db1472b0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319388328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3319388328
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1049124100
Short name T242
Test name
Test status
Simulation time 380768096 ps
CPU time 1.31 seconds
Started Jul 17 06:57:03 PM PDT 24
Finished Jul 17 06:57:06 PM PDT 24
Peak memory 197644 kb
Host smart-68c2c23b-4d25-4811-82c6-bd74885d47d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049124100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1049124100
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3172094961
Short name T449
Test name
Test status
Simulation time 148320480 ps
CPU time 1.99 seconds
Started Jul 17 06:57:03 PM PDT 24
Finished Jul 17 06:57:07 PM PDT 24
Peak memory 198632 kb
Host smart-8987f472-c265-4750-9ae9-2c46e162309e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172094961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3172094961
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1135481112
Short name T42
Test name
Test status
Simulation time 210588161 ps
CPU time 0.83 seconds
Started Jul 17 06:57:15 PM PDT 24
Finished Jul 17 06:57:16 PM PDT 24
Peak memory 214372 kb
Host smart-1097658c-07b2-4fea-960c-763c627377a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135481112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1135481112
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.539373943
Short name T169
Test name
Test status
Simulation time 158376608 ps
CPU time 1.47 seconds
Started Jul 17 06:57:06 PM PDT 24
Finished Jul 17 06:57:09 PM PDT 24
Peak memory 198680 kb
Host smart-e65f9b15-0184-4bc3-a190-8ae1476b2b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539373943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.539373943
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2425128161
Short name T62
Test name
Test status
Simulation time 147779060 ps
CPU time 1.09 seconds
Started Jul 17 06:57:06 PM PDT 24
Finished Jul 17 06:57:09 PM PDT 24
Peak memory 196952 kb
Host smart-4b1dd90b-bce1-4c5c-b3ba-7e015e9165b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425128161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2425128161
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.852900073
Short name T427
Test name
Test status
Simulation time 19554781692 ps
CPU time 98.58 seconds
Started Jul 17 06:57:05 PM PDT 24
Finished Jul 17 06:58:45 PM PDT 24
Peak memory 198864 kb
Host smart-069484d0-d369-4d7f-96dd-425f84e924aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852900073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.852900073
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.1785620424
Short name T537
Test name
Test status
Simulation time 15124164562 ps
CPU time 409.62 seconds
Started Jul 17 06:57:03 PM PDT 24
Finished Jul 17 07:03:54 PM PDT 24
Peak memory 198924 kb
Host smart-c904d2e0-b9e8-403d-9a04-76cf7580cb19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1785620424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.1785620424
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1752575358
Short name T390
Test name
Test status
Simulation time 73574630 ps
CPU time 0.57 seconds
Started Jul 17 06:58:56 PM PDT 24
Finished Jul 17 06:58:57 PM PDT 24
Peak memory 194684 kb
Host smart-d861c88c-8bc2-4277-a062-cd438eeea60f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752575358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1752575358
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1686759125
Short name T638
Test name
Test status
Simulation time 20125143 ps
CPU time 0.73 seconds
Started Jul 17 06:58:48 PM PDT 24
Finished Jul 17 06:58:50 PM PDT 24
Peak memory 195940 kb
Host smart-ea43383b-ef96-485a-b8d3-724625933b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686759125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1686759125
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.456523508
Short name T222
Test name
Test status
Simulation time 761313923 ps
CPU time 13.9 seconds
Started Jul 17 06:58:52 PM PDT 24
Finished Jul 17 06:59:07 PM PDT 24
Peak memory 197120 kb
Host smart-0b51c4d5-ff20-43db-b93e-cea74fa6df99
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456523508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.456523508
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3667891506
Short name T328
Test name
Test status
Simulation time 111461109 ps
CPU time 0.68 seconds
Started Jul 17 06:58:55 PM PDT 24
Finished Jul 17 06:58:56 PM PDT 24
Peak memory 195320 kb
Host smart-ec172e49-a5d6-4d11-8e69-8e2949fea604
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667891506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3667891506
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.320477135
Short name T607
Test name
Test status
Simulation time 135938240 ps
CPU time 1.05 seconds
Started Jul 17 06:58:54 PM PDT 24
Finished Jul 17 06:58:56 PM PDT 24
Peak memory 196728 kb
Host smart-4a0bfb25-9976-41b6-aa78-94d101e98f5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320477135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.320477135
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3455185810
Short name T699
Test name
Test status
Simulation time 25345993 ps
CPU time 1.07 seconds
Started Jul 17 06:58:53 PM PDT 24
Finished Jul 17 06:58:55 PM PDT 24
Peak memory 197780 kb
Host smart-18de9af4-192c-4cef-8ba5-9708773ada71
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455185810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3455185810
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.86770619
Short name T314
Test name
Test status
Simulation time 298176513 ps
CPU time 2.63 seconds
Started Jul 17 06:58:50 PM PDT 24
Finished Jul 17 06:58:54 PM PDT 24
Peak memory 198772 kb
Host smart-2ec61980-a1be-43ee-aa1d-d8d1ed494e57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86770619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.86770619
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.246736945
Short name T224
Test name
Test status
Simulation time 715385401 ps
CPU time 0.94 seconds
Started Jul 17 06:58:50 PM PDT 24
Finished Jul 17 06:58:53 PM PDT 24
Peak memory 196680 kb
Host smart-4add6fab-fb31-487f-a2d4-f2e87e6b68a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246736945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.246736945
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.36993196
Short name T267
Test name
Test status
Simulation time 77333233 ps
CPU time 0.81 seconds
Started Jul 17 06:58:51 PM PDT 24
Finished Jul 17 06:58:53 PM PDT 24
Peak memory 197072 kb
Host smart-098636e6-54ec-4350-b5ea-51935d52e8a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36993196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup_
pulldown.36993196
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.680253598
Short name T413
Test name
Test status
Simulation time 657807433 ps
CPU time 1.8 seconds
Started Jul 17 06:58:50 PM PDT 24
Finished Jul 17 06:58:53 PM PDT 24
Peak memory 198528 kb
Host smart-6dc9b143-a212-4850-91bf-129a150f7336
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680253598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.680253598
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3705737804
Short name T24
Test name
Test status
Simulation time 288505349 ps
CPU time 1.23 seconds
Started Jul 17 06:58:55 PM PDT 24
Finished Jul 17 06:58:58 PM PDT 24
Peak memory 196196 kb
Host smart-7d827ca1-c05c-448a-a36c-ae4f84d6516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705737804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3705737804
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.629629004
Short name T207
Test name
Test status
Simulation time 852748335 ps
CPU time 1.07 seconds
Started Jul 17 06:58:56 PM PDT 24
Finished Jul 17 06:58:58 PM PDT 24
Peak memory 196260 kb
Host smart-151514d0-c2ff-4a3a-b282-d7a9bdfa14f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629629004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.629629004
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2590639577
Short name T170
Test name
Test status
Simulation time 2698031595 ps
CPU time 68.89 seconds
Started Jul 17 06:58:49 PM PDT 24
Finished Jul 17 06:59:59 PM PDT 24
Peak memory 198788 kb
Host smart-40500dda-33f7-4215-bd69-20dbf277c60e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590639577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2590639577
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1841373222
Short name T63
Test name
Test status
Simulation time 202221490 ps
CPU time 0.59 seconds
Started Jul 17 06:59:19 PM PDT 24
Finished Jul 17 06:59:25 PM PDT 24
Peak memory 194636 kb
Host smart-e899c6fb-2bbb-4bcc-a148-5879c6b35c80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841373222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1841373222
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.84852669
Short name T595
Test name
Test status
Simulation time 244440596 ps
CPU time 0.95 seconds
Started Jul 17 06:58:49 PM PDT 24
Finished Jul 17 06:58:52 PM PDT 24
Peak memory 197924 kb
Host smart-40d673d2-1f2a-4f0b-a4fe-b74c6b5712e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84852669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.84852669
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2327274225
Short name T252
Test name
Test status
Simulation time 1238550299 ps
CPU time 11.4 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:30 PM PDT 24
Peak memory 198680 kb
Host smart-bfb1eb94-4156-40ca-b885-08f9859fae02
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327274225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2327274225
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.354639903
Short name T372
Test name
Test status
Simulation time 108568623 ps
CPU time 0.72 seconds
Started Jul 17 06:59:16 PM PDT 24
Finished Jul 17 06:59:18 PM PDT 24
Peak memory 196036 kb
Host smart-094918a3-ddd1-4389-a475-19cb5841b750
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354639903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.354639903
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3864358440
Short name T536
Test name
Test status
Simulation time 168400176 ps
CPU time 0.83 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:28 PM PDT 24
Peak memory 196068 kb
Host smart-0d435f17-f2ec-4720-9dd9-bd1668c5be9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864358440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3864358440
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3323180567
Short name T317
Test name
Test status
Simulation time 136281024 ps
CPU time 1.49 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:29 PM PDT 24
Peak memory 197120 kb
Host smart-88a1d810-aa99-4e98-8a42-3c222d11ecc1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323180567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3323180567
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3710972828
Short name T476
Test name
Test status
Simulation time 109555554 ps
CPU time 2.51 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:25 PM PDT 24
Peak memory 196496 kb
Host smart-78855fde-3d2b-45ca-a715-8a338347dae6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710972828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3710972828
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.332970068
Short name T634
Test name
Test status
Simulation time 130163024 ps
CPU time 1.18 seconds
Started Jul 17 06:58:52 PM PDT 24
Finished Jul 17 06:58:55 PM PDT 24
Peak memory 197524 kb
Host smart-12dddd67-b582-41ad-9bcd-2199042a7895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332970068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.332970068
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1334061830
Short name T325
Test name
Test status
Simulation time 123842633 ps
CPU time 1.23 seconds
Started Jul 17 06:58:48 PM PDT 24
Finished Jul 17 06:58:50 PM PDT 24
Peak memory 197748 kb
Host smart-026a8434-170c-4428-bda7-8952f445c6bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334061830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1334061830
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2025696512
Short name T688
Test name
Test status
Simulation time 1021688189 ps
CPU time 4.64 seconds
Started Jul 17 06:59:15 PM PDT 24
Finished Jul 17 06:59:20 PM PDT 24
Peak memory 198600 kb
Host smart-c3718e3b-b4cc-4307-a09c-d0244415b030
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025696512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2025696512
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.4155310382
Short name T580
Test name
Test status
Simulation time 70132578 ps
CPU time 1.15 seconds
Started Jul 17 06:58:52 PM PDT 24
Finished Jul 17 06:58:54 PM PDT 24
Peak memory 196488 kb
Host smart-cc95b67f-084c-4cfd-820b-8dd58ad20b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155310382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.4155310382
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3434529154
Short name T696
Test name
Test status
Simulation time 248915873 ps
CPU time 1.35 seconds
Started Jul 17 06:58:48 PM PDT 24
Finished Jul 17 06:58:50 PM PDT 24
Peak memory 196204 kb
Host smart-b37e8583-8f79-4d4c-bded-6a81890b837c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434529154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3434529154
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1251874458
Short name T191
Test name
Test status
Simulation time 13336281275 ps
CPU time 48.36 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 07:00:09 PM PDT 24
Peak memory 198828 kb
Host smart-72dcde09-5755-4a2e-90af-3d8f09c1bf0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251874458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1251874458
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.438336401
Short name T71
Test name
Test status
Simulation time 302576014369 ps
CPU time 1295.78 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 07:21:03 PM PDT 24
Peak memory 198896 kb
Host smart-2b7fd37a-6bae-4526-856d-f53d095d933c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=438336401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.438336401
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3303776409
Short name T132
Test name
Test status
Simulation time 41489773 ps
CPU time 0.56 seconds
Started Jul 17 06:59:19 PM PDT 24
Finished Jul 17 06:59:24 PM PDT 24
Peak memory 194696 kb
Host smart-b7626de5-d056-4fa4-843d-ea101e292dd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303776409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3303776409
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1345163002
Short name T151
Test name
Test status
Simulation time 24870392 ps
CPU time 0.63 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:28 PM PDT 24
Peak memory 194724 kb
Host smart-5a6f6710-f931-4b77-8100-9560cc639a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345163002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1345163002
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2494192520
Short name T134
Test name
Test status
Simulation time 353331352 ps
CPU time 5.44 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:28 PM PDT 24
Peak memory 198680 kb
Host smart-004ec755-95bb-48d3-ab2b-cd1a018f6779
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494192520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2494192520
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1903103265
Short name T218
Test name
Test status
Simulation time 178497301 ps
CPU time 0.83 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:25 PM PDT 24
Peak memory 197180 kb
Host smart-1773122f-4fce-4ae0-9c64-b3103ab6fe6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903103265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1903103265
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3480546456
Short name T610
Test name
Test status
Simulation time 199730946 ps
CPU time 1.03 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:22 PM PDT 24
Peak memory 196824 kb
Host smart-c512584a-b8a2-455d-ac8f-bec5fa134271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480546456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3480546456
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1116692430
Short name T568
Test name
Test status
Simulation time 26555192 ps
CPU time 0.97 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:20 PM PDT 24
Peak memory 196684 kb
Host smart-effea137-6522-4455-b39a-b5f08773bbf9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116692430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1116692430
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1902523703
Short name T654
Test name
Test status
Simulation time 376274281 ps
CPU time 2.39 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:23 PM PDT 24
Peak memory 195492 kb
Host smart-51c5f7a7-cbf9-4982-8590-7040dfc6a876
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902523703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1902523703
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3232557955
Short name T175
Test name
Test status
Simulation time 39738504 ps
CPU time 0.69 seconds
Started Jul 17 06:59:16 PM PDT 24
Finished Jul 17 06:59:18 PM PDT 24
Peak memory 195660 kb
Host smart-fd4c4d73-b729-4377-9669-c8c4f180c3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232557955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3232557955
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2056527562
Short name T161
Test name
Test status
Simulation time 75963635 ps
CPU time 1.39 seconds
Started Jul 17 06:59:15 PM PDT 24
Finished Jul 17 06:59:17 PM PDT 24
Peak memory 197660 kb
Host smart-c035b9d9-732b-42fe-adb8-f09b66c64bf7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056527562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2056527562
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3147716427
Short name T463
Test name
Test status
Simulation time 1052335903 ps
CPU time 3.34 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 198652 kb
Host smart-f1db762e-feba-41b6-98d4-4bb57ef7fee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147716427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3147716427
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3678284163
Short name T524
Test name
Test status
Simulation time 40430515 ps
CPU time 1.22 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:20 PM PDT 24
Peak memory 197212 kb
Host smart-251671fa-5772-4a69-b110-12b797f148bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678284163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3678284163
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3504556141
Short name T403
Test name
Test status
Simulation time 40637407 ps
CPU time 0.87 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:22 PM PDT 24
Peak memory 197560 kb
Host smart-e5bbdcda-9157-4e3c-9c53-8541c35277e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504556141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3504556141
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1855983820
Short name T694
Test name
Test status
Simulation time 2367080129 ps
CPU time 25.15 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:44 PM PDT 24
Peak memory 198772 kb
Host smart-9918b9c1-10dc-48b9-a0cb-d79ca4a762c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855983820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1855983820
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.735647926
Short name T504
Test name
Test status
Simulation time 30213206 ps
CPU time 0.57 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:28 PM PDT 24
Peak memory 195324 kb
Host smart-11c4219a-44ce-431f-8418-63a86e687262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735647926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.735647926
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.4071484556
Short name T375
Test name
Test status
Simulation time 51674717 ps
CPU time 0.69 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:19 PM PDT 24
Peak memory 195456 kb
Host smart-382e3bcc-1550-4a90-b04f-61a053f10be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071484556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.4071484556
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3514089509
Short name T482
Test name
Test status
Simulation time 1352457082 ps
CPU time 24.18 seconds
Started Jul 17 06:59:19 PM PDT 24
Finished Jul 17 06:59:49 PM PDT 24
Peak memory 197656 kb
Host smart-55bc1012-d898-4efd-aa51-cced2aca8d9a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514089509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3514089509
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.430986972
Short name T489
Test name
Test status
Simulation time 184061476 ps
CPU time 1.08 seconds
Started Jul 17 06:59:16 PM PDT 24
Finished Jul 17 06:59:18 PM PDT 24
Peak memory 197280 kb
Host smart-561ab77e-b001-4360-b972-e7f2aca99b26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430986972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.430986972
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.4200733755
Short name T690
Test name
Test status
Simulation time 119642620 ps
CPU time 1.1 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:20 PM PDT 24
Peak memory 196776 kb
Host smart-851b5b72-a214-4155-99a3-9edd1ca38d50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200733755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.4200733755
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1267935060
Short name T289
Test name
Test status
Simulation time 581199370 ps
CPU time 3.11 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 198716 kb
Host smart-1a332dc2-8988-4990-83d5-827dfb9fd6d9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267935060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1267935060
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.4279846452
Short name T433
Test name
Test status
Simulation time 1290452707 ps
CPU time 2.91 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:21 PM PDT 24
Peak memory 197908 kb
Host smart-d47e736f-22da-424e-94f4-3c5d7c62538c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279846452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.4279846452
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3317843834
Short name T385
Test name
Test status
Simulation time 51841130 ps
CPU time 1.3 seconds
Started Jul 17 06:59:19 PM PDT 24
Finished Jul 17 06:59:26 PM PDT 24
Peak memory 198768 kb
Host smart-c89e522a-a0b8-4b40-afd8-e7fe5f94a466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317843834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3317843834
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4199785489
Short name T419
Test name
Test status
Simulation time 31702468 ps
CPU time 1.09 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:23 PM PDT 24
Peak memory 197584 kb
Host smart-fad69186-1189-48f5-af89-7f19763c0af8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199785489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4199785489
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.249674579
Short name T465
Test name
Test status
Simulation time 58046739 ps
CPU time 2.63 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:23 PM PDT 24
Peak memory 197608 kb
Host smart-c17adc0d-b2e8-41be-9214-4ed64033d21d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249674579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.249674579
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2175298513
Short name T651
Test name
Test status
Simulation time 161766550 ps
CPU time 1.43 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 196236 kb
Host smart-0799730a-acea-424b-b3ef-ce281d909484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175298513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2175298513
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.824966979
Short name T320
Test name
Test status
Simulation time 43908233 ps
CPU time 1.44 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:25 PM PDT 24
Peak memory 197500 kb
Host smart-ed5cbfad-4c6d-4a8a-8a48-836bf2adebab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824966979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.824966979
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1900743920
Short name T715
Test name
Test status
Simulation time 8759274252 ps
CPU time 166.88 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 07:02:15 PM PDT 24
Peak memory 198632 kb
Host smart-b1578520-42a6-4512-a001-99cb2be5d6c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900743920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1900743920
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.4053534685
Short name T43
Test name
Test status
Simulation time 26819911 ps
CPU time 0.59 seconds
Started Jul 17 06:59:16 PM PDT 24
Finished Jul 17 06:59:17 PM PDT 24
Peak memory 195360 kb
Host smart-befa4de7-625c-47a0-a0cc-302ac36be12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053534685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.4053534685
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1818574900
Short name T342
Test name
Test status
Simulation time 61255375 ps
CPU time 0.68 seconds
Started Jul 17 06:59:11 PM PDT 24
Finished Jul 17 06:59:12 PM PDT 24
Peak memory 196112 kb
Host smart-d1a11b31-d60f-4408-a9bb-192538bce6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818574900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1818574900
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2849132586
Short name T245
Test name
Test status
Simulation time 319285487 ps
CPU time 16.42 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:44 PM PDT 24
Peak memory 196816 kb
Host smart-951331c2-ca88-46c3-9121-2b449b21cf6d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849132586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2849132586
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.173790830
Short name T120
Test name
Test status
Simulation time 68586854 ps
CPU time 0.86 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:21 PM PDT 24
Peak memory 196568 kb
Host smart-ca046920-fee1-4880-be6f-772c1930d422
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173790830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.173790830
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.678780132
Short name T471
Test name
Test status
Simulation time 327759584 ps
CPU time 1.31 seconds
Started Jul 17 06:59:16 PM PDT 24
Finished Jul 17 06:59:19 PM PDT 24
Peak memory 197620 kb
Host smart-0eb78a60-1ec3-4bbf-8b1a-4144cfc016a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678780132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.678780132
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1700930899
Short name T219
Test name
Test status
Simulation time 143085567 ps
CPU time 2.84 seconds
Started Jul 17 07:03:47 PM PDT 24
Finished Jul 17 07:03:51 PM PDT 24
Peak memory 198644 kb
Host smart-02fc4463-29eb-4f35-a623-ab66f88c47ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700930899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1700930899
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2240305237
Short name T611
Test name
Test status
Simulation time 649193298 ps
CPU time 1.47 seconds
Started Jul 17 06:59:19 PM PDT 24
Finished Jul 17 06:59:26 PM PDT 24
Peak memory 196784 kb
Host smart-ed59ce27-f170-414d-b8e5-ed39d31ee68e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240305237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2240305237
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3278746457
Short name T359
Test name
Test status
Simulation time 66569008 ps
CPU time 0.71 seconds
Started Jul 17 06:59:16 PM PDT 24
Finished Jul 17 06:59:17 PM PDT 24
Peak memory 195204 kb
Host smart-39a3731e-e20a-48c2-8e4f-f1617648905a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278746457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3278746457
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3972072191
Short name T123
Test name
Test status
Simulation time 33332872 ps
CPU time 1.15 seconds
Started Jul 17 06:59:16 PM PDT 24
Finished Jul 17 06:59:18 PM PDT 24
Peak memory 198732 kb
Host smart-fd303439-26b3-4f97-93b9-c3c5c2ddc28e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972072191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3972072191
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2100547716
Short name T505
Test name
Test status
Simulation time 88105959 ps
CPU time 3.44 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:25 PM PDT 24
Peak memory 198680 kb
Host smart-9cef53da-0bc8-4b55-bea5-501b30a19f08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100547716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2100547716
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3282449125
Short name T275
Test name
Test status
Simulation time 209752154 ps
CPU time 1.14 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:28 PM PDT 24
Peak memory 196544 kb
Host smart-8c8d3f86-12a1-4fec-a9c0-9623078616ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282449125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3282449125
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2998760488
Short name T34
Test name
Test status
Simulation time 155015092 ps
CPU time 0.92 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:19 PM PDT 24
Peak memory 197628 kb
Host smart-5eb98416-c2f2-4995-a0eb-6f15cfc7b31a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998760488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2998760488
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2050766747
Short name T412
Test name
Test status
Simulation time 1719651172 ps
CPU time 38.29 seconds
Started Jul 17 06:59:19 PM PDT 24
Finished Jul 17 07:00:04 PM PDT 24
Peak memory 198680 kb
Host smart-4ecb5384-b54f-4011-bfee-f763b2bd68c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050766747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2050766747
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.269923795
Short name T329
Test name
Test status
Simulation time 25016810 ps
CPU time 0.56 seconds
Started Jul 17 06:59:19 PM PDT 24
Finished Jul 17 06:59:25 PM PDT 24
Peak memory 194640 kb
Host smart-d7b6b075-cbdf-41da-83cb-6cab58c07345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269923795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.269923795
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.4218530988
Short name T544
Test name
Test status
Simulation time 405806092 ps
CPU time 0.83 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:29 PM PDT 24
Peak memory 196588 kb
Host smart-07d679d8-4983-4b4a-83b9-d4697f05bbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218530988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.4218530988
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1654675458
Short name T530
Test name
Test status
Simulation time 680671703 ps
CPU time 18.36 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 197492 kb
Host smart-d8dc962e-7e06-4a08-a08c-beb3eb7ee5d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654675458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1654675458
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2834562936
Short name T308
Test name
Test status
Simulation time 34495404 ps
CPU time 0.62 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:19 PM PDT 24
Peak memory 195144 kb
Host smart-c1fac4ab-d6cc-44fe-beb3-7749bad23603
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834562936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2834562936
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.520510875
Short name T202
Test name
Test status
Simulation time 182022545 ps
CPU time 0.9 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:25 PM PDT 24
Peak memory 196556 kb
Host smart-9dadda53-6ef8-4ade-b955-345538f23677
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520510875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.520510875
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2844513613
Short name T542
Test name
Test status
Simulation time 149224298 ps
CPU time 1.28 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:28 PM PDT 24
Peak memory 198728 kb
Host smart-009b5167-40e7-431a-873d-8f2936b4ee6a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844513613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2844513613
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3448399198
Short name T287
Test name
Test status
Simulation time 154086230 ps
CPU time 2.85 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 197656 kb
Host smart-0cf2013f-7112-4f3f-8a92-c8c98f3bd5fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448399198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3448399198
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3569735122
Short name T443
Test name
Test status
Simulation time 22864682 ps
CPU time 0.89 seconds
Started Jul 17 06:59:19 PM PDT 24
Finished Jul 17 06:59:28 PM PDT 24
Peak memory 196628 kb
Host smart-7cd85515-12ad-42a2-9dd8-280409d35db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569735122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3569735122
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2262177024
Short name T194
Test name
Test status
Simulation time 43943722 ps
CPU time 1.09 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:20 PM PDT 24
Peak memory 196756 kb
Host smart-f52d7f75-5f75-4445-8e77-2511370e54e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262177024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2262177024
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3249265288
Short name T8
Test name
Test status
Simulation time 1441592072 ps
CPU time 4.44 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:32 PM PDT 24
Peak memory 198408 kb
Host smart-7e94eceb-54e1-4c95-9cd9-d7ffc9706a8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249265288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3249265288
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.460128977
Short name T511
Test name
Test status
Simulation time 98438955 ps
CPU time 1.32 seconds
Started Jul 17 06:59:15 PM PDT 24
Finished Jul 17 06:59:16 PM PDT 24
Peak memory 197396 kb
Host smart-8936395a-072a-4405-85eb-f472a41deed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460128977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.460128977
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3442444642
Short name T284
Test name
Test status
Simulation time 64050386 ps
CPU time 1.01 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:28 PM PDT 24
Peak memory 196244 kb
Host smart-ed6beee5-85f0-4b2e-a5af-4b5878b070dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442444642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3442444642
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.94254878
Short name T608
Test name
Test status
Simulation time 5267573958 ps
CPU time 75.31 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 07:00:39 PM PDT 24
Peak memory 198080 kb
Host smart-9d631200-641c-46df-9533-9df8a796a745
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94254878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gp
io_stress_all.94254878
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2482455752
Short name T560
Test name
Test status
Simulation time 17381624 ps
CPU time 0.57 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:30 PM PDT 24
Peak memory 194684 kb
Host smart-9d529f0a-b7bc-4a3e-ba48-790ffc61d336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482455752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2482455752
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1022079867
Short name T290
Test name
Test status
Simulation time 24893355 ps
CPU time 0.86 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:22 PM PDT 24
Peak memory 196080 kb
Host smart-a81a51c1-a223-4a27-bc06-2b1ca248345d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022079867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1022079867
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.50828230
Short name T406
Test name
Test status
Simulation time 528456867 ps
CPU time 8 seconds
Started Jul 17 06:59:21 PM PDT 24
Finished Jul 17 06:59:37 PM PDT 24
Peak memory 196948 kb
Host smart-2a8fd92a-c6a8-4dad-b135-2183afa7ca5b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50828230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stress
.50828230
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1716263989
Short name T513
Test name
Test status
Simulation time 118398526 ps
CPU time 0.71 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:24 PM PDT 24
Peak memory 196084 kb
Host smart-71d90b85-3e92-4d74-8dd2-e63c104396ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716263989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1716263989
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1143227935
Short name T30
Test name
Test status
Simulation time 210393420 ps
CPU time 0.67 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:20 PM PDT 24
Peak memory 195024 kb
Host smart-f4d7d102-7579-4cf4-beda-e6e805dce92a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143227935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1143227935
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1211899687
Short name T483
Test name
Test status
Simulation time 162397883 ps
CPU time 3.28 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:36 PM PDT 24
Peak memory 198732 kb
Host smart-d9461aed-9e88-465b-b066-b049b7bb7632
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211899687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1211899687
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3625146815
Short name T263
Test name
Test status
Simulation time 318556350 ps
CPU time 1.99 seconds
Started Jul 17 06:59:24 PM PDT 24
Finished Jul 17 06:59:35 PM PDT 24
Peak memory 196772 kb
Host smart-00ffba37-2e73-443d-b1bc-169b3c9d0c1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625146815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3625146815
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1453150514
Short name T248
Test name
Test status
Simulation time 145711926 ps
CPU time 1.41 seconds
Started Jul 17 06:59:24 PM PDT 24
Finished Jul 17 06:59:34 PM PDT 24
Peak memory 198628 kb
Host smart-382d577f-ed5e-4011-a48e-121673ea677d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453150514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1453150514
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2196892600
Short name T564
Test name
Test status
Simulation time 238930480 ps
CPU time 1.2 seconds
Started Jul 17 06:59:19 PM PDT 24
Finished Jul 17 06:59:26 PM PDT 24
Peak memory 197824 kb
Host smart-d0e4407f-5ef1-4502-92b6-2163ac87038e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196892600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2196892600
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_smoke.807694883
Short name T512
Test name
Test status
Simulation time 187619263 ps
CPU time 1.17 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:25 PM PDT 24
Peak memory 197124 kb
Host smart-e45ad32e-8ea4-4fa1-a9ce-720a27236575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807694883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.807694883
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3676633983
Short name T146
Test name
Test status
Simulation time 161809832 ps
CPU time 0.96 seconds
Started Jul 17 06:59:21 PM PDT 24
Finished Jul 17 06:59:30 PM PDT 24
Peak memory 197640 kb
Host smart-d56ade29-0a50-4ec2-81bc-2fcdd9ce1ad8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676633983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3676633983
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3390714940
Short name T516
Test name
Test status
Simulation time 13188679830 ps
CPU time 174.72 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 07:02:22 PM PDT 24
Peak memory 198556 kb
Host smart-f021596b-d6ae-43f9-ad61-ae3ffabebc95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390714940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3390714940
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2123700579
Short name T642
Test name
Test status
Simulation time 18615500 ps
CPU time 0.59 seconds
Started Jul 17 06:59:21 PM PDT 24
Finished Jul 17 06:59:29 PM PDT 24
Peak memory 195392 kb
Host smart-a432a76c-1911-4951-b893-5609de2805b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123700579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2123700579
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2444561537
Short name T340
Test name
Test status
Simulation time 31537540 ps
CPU time 0.92 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:24 PM PDT 24
Peak memory 197120 kb
Host smart-e64334fb-587b-419c-b8af-ada6803cc123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444561537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2444561537
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2923843213
Short name T333
Test name
Test status
Simulation time 2678073509 ps
CPU time 20.78 seconds
Started Jul 17 06:59:24 PM PDT 24
Finished Jul 17 06:59:53 PM PDT 24
Peak memory 197512 kb
Host smart-52ea130b-1da2-4b4f-a67e-e5294212f0d7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923843213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2923843213
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3591346843
Short name T302
Test name
Test status
Simulation time 67025995 ps
CPU time 0.81 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:28 PM PDT 24
Peak memory 196452 kb
Host smart-12744a4c-e109-4708-9994-2271b8e64dc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591346843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3591346843
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2499966019
Short name T597
Test name
Test status
Simulation time 419585859 ps
CPU time 0.77 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:24 PM PDT 24
Peak memory 196900 kb
Host smart-38812064-879d-416c-a15b-3b5d54f5b325
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499966019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2499966019
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2268881504
Short name T416
Test name
Test status
Simulation time 27256486 ps
CPU time 1.15 seconds
Started Jul 17 06:59:24 PM PDT 24
Finished Jul 17 06:59:34 PM PDT 24
Peak memory 198568 kb
Host smart-4996080a-92fe-4bb2-907a-c699a5e544d1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268881504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2268881504
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3957208228
Short name T668
Test name
Test status
Simulation time 98516898 ps
CPU time 2.16 seconds
Started Jul 17 06:59:24 PM PDT 24
Finished Jul 17 06:59:35 PM PDT 24
Peak memory 197720 kb
Host smart-0446c77d-bcdd-4bdb-910b-17b92d41729b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957208228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3957208228
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.512996772
Short name T430
Test name
Test status
Simulation time 382586975 ps
CPU time 1.17 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:23 PM PDT 24
Peak memory 197660 kb
Host smart-e4f90c3e-e10e-4042-b2ce-0f4f611264ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512996772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.512996772
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.4084394611
Short name T232
Test name
Test status
Simulation time 372019300 ps
CPU time 1.2 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 06:59:20 PM PDT 24
Peak memory 198756 kb
Host smart-de31c796-1dea-41dd-9cbb-e7ddf0f6b7b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084394611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.4084394611
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.4179702697
Short name T599
Test name
Test status
Simulation time 453847329 ps
CPU time 6.24 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:36 PM PDT 24
Peak memory 198648 kb
Host smart-d850b6f7-3049-4cd0-9feb-825d390e2499
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179702697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.4179702697
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.217483528
Short name T23
Test name
Test status
Simulation time 46926547 ps
CPU time 1.03 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:22 PM PDT 24
Peak memory 196284 kb
Host smart-9407400d-c6f4-49e2-a040-3bbcc3dee130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217483528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.217483528
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3934664246
Short name T269
Test name
Test status
Simulation time 148612504 ps
CPU time 1.21 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 196468 kb
Host smart-a7581833-23eb-44c5-bbac-146a2cfc7db0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934664246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3934664246
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.782917264
Short name T436
Test name
Test status
Simulation time 25343256234 ps
CPU time 167.11 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 07:02:14 PM PDT 24
Peak memory 198784 kb
Host smart-455f7948-dfd7-4096-8572-f325047ce82a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782917264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.782917264
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2177446362
Short name T381
Test name
Test status
Simulation time 120853054961 ps
CPU time 2442.89 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 07:40:13 PM PDT 24
Peak memory 198948 kb
Host smart-eb36c6de-d547-4edf-819e-0b9bf3f19e4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2177446362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2177446362
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.4004691385
Short name T130
Test name
Test status
Simulation time 43910190 ps
CPU time 0.54 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 194612 kb
Host smart-a3ea05c1-c192-468b-a841-10e8cf17fb87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004691385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.4004691385
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2496562227
Short name T550
Test name
Test status
Simulation time 266531177 ps
CPU time 0.9 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 196580 kb
Host smart-5dc08079-dd35-4d80-a70d-27f3bcde2995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496562227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2496562227
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.561329377
Short name T118
Test name
Test status
Simulation time 7159120840 ps
CPU time 16.85 seconds
Started Jul 17 06:59:24 PM PDT 24
Finished Jul 17 06:59:49 PM PDT 24
Peak memory 198740 kb
Host smart-a653ee77-5081-4780-bfa8-44bb76ab8267
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561329377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.561329377
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3414694909
Short name T588
Test name
Test status
Simulation time 167373804 ps
CPU time 1.05 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 196996 kb
Host smart-4c915c47-50a5-42e4-9013-8c2b6ed5c074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414694909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3414694909
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.540493353
Short name T423
Test name
Test status
Simulation time 176650030 ps
CPU time 1.09 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 197440 kb
Host smart-3a35c4b3-3e6a-463a-86ed-9217c1da7f7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540493353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.540493353
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1361020069
Short name T528
Test name
Test status
Simulation time 359701524 ps
CPU time 3.76 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:36 PM PDT 24
Peak memory 198672 kb
Host smart-ebd7b1b9-80a8-47ba-9e9b-486555f6a75d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361020069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1361020069
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3455310647
Short name T180
Test name
Test status
Simulation time 67201478 ps
CPU time 1.25 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 196176 kb
Host smart-1487302f-0b32-403a-8a73-4581b4f6eda5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455310647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3455310647
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.4064470546
Short name T487
Test name
Test status
Simulation time 101235553 ps
CPU time 0.69 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:32 PM PDT 24
Peak memory 196096 kb
Host smart-f952a264-9618-4bb4-8065-91371a2a1c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064470546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.4064470546
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2683334157
Short name T209
Test name
Test status
Simulation time 113366158 ps
CPU time 1.3 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:34 PM PDT 24
Peak memory 198612 kb
Host smart-03db1df1-5443-4805-94a6-ac78fcd6c6d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683334157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2683334157
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3292230462
Short name T401
Test name
Test status
Simulation time 142269702 ps
CPU time 2.29 seconds
Started Jul 17 06:59:24 PM PDT 24
Finished Jul 17 06:59:35 PM PDT 24
Peak memory 198700 kb
Host smart-facb9e00-ca39-46e5-8a7a-4589d50fe8ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292230462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3292230462
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2986100163
Short name T125
Test name
Test status
Simulation time 63198450 ps
CPU time 0.83 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 197116 kb
Host smart-f7e03b2a-ae3e-492d-ad0c-edcb30624f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986100163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2986100163
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1596247880
Short name T594
Test name
Test status
Simulation time 62235275 ps
CPU time 0.97 seconds
Started Jul 17 06:59:19 PM PDT 24
Finished Jul 17 06:59:26 PM PDT 24
Peak memory 197192 kb
Host smart-dbd67c88-fd18-4177-ae0b-6d4da64b4803
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596247880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1596247880
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2349797582
Short name T221
Test name
Test status
Simulation time 19868813053 ps
CPU time 129.74 seconds
Started Jul 17 06:59:17 PM PDT 24
Finished Jul 17 07:01:29 PM PDT 24
Peak memory 198760 kb
Host smart-08cf668d-ac20-4bc7-a38a-fb2bcb360303
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349797582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2349797582
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1919976222
Short name T686
Test name
Test status
Simulation time 37913258 ps
CPU time 0.57 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:30 PM PDT 24
Peak memory 194712 kb
Host smart-ba43541c-95b0-4866-8168-35113bc417fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919976222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1919976222
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.108870074
Short name T705
Test name
Test status
Simulation time 112914921 ps
CPU time 0.79 seconds
Started Jul 17 06:59:24 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 195924 kb
Host smart-e6ab02e0-b83f-42e7-b2d1-a43ee3518ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108870074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.108870074
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.941678141
Short name T397
Test name
Test status
Simulation time 1081844474 ps
CPU time 9.32 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:40 PM PDT 24
Peak memory 197344 kb
Host smart-681b668e-31ea-42af-80ee-55f0f3998eda
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941678141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.941678141
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2625541098
Short name T712
Test name
Test status
Simulation time 714614643 ps
CPU time 0.85 seconds
Started Jul 17 06:59:21 PM PDT 24
Finished Jul 17 06:59:29 PM PDT 24
Peak memory 196504 kb
Host smart-d1c29a9f-ea7a-49b8-b826-0f9b28ee19ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625541098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2625541098
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2148003539
Short name T415
Test name
Test status
Simulation time 290383466 ps
CPU time 0.97 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 196652 kb
Host smart-6939c778-bce6-4dcd-a0c1-d739e5827891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148003539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2148003539
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3241900507
Short name T596
Test name
Test status
Simulation time 89964510 ps
CPU time 1.89 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:32 PM PDT 24
Peak memory 198728 kb
Host smart-5f32aa8e-a050-4b24-9540-4133fb114f4d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241900507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3241900507
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2286991484
Short name T554
Test name
Test status
Simulation time 146569890 ps
CPU time 0.97 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:32 PM PDT 24
Peak memory 196912 kb
Host smart-b64f4375-96c4-47a8-a1ec-3c85c5c586a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286991484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2286991484
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3017619775
Short name T565
Test name
Test status
Simulation time 139105667 ps
CPU time 1.07 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:32 PM PDT 24
Peak memory 196700 kb
Host smart-98d57d17-8bbb-4370-a75a-62810e270cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017619775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3017619775
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1095051451
Short name T587
Test name
Test status
Simulation time 22795048 ps
CPU time 0.96 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 197316 kb
Host smart-f784cde8-e189-4f9a-8d3f-5eeb7221498a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095051451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1095051451
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1856447699
Short name T383
Test name
Test status
Simulation time 466417220 ps
CPU time 5.21 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:36 PM PDT 24
Peak memory 198696 kb
Host smart-56f434fa-e7f0-4706-b86b-6a53463a6235
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856447699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1856447699
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1394129525
Short name T335
Test name
Test status
Simulation time 86045680 ps
CPU time 0.95 seconds
Started Jul 17 06:59:27 PM PDT 24
Finished Jul 17 06:59:35 PM PDT 24
Peak memory 196060 kb
Host smart-d8bb9cba-49d4-4cd1-a7b0-16ae78a1fb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394129525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1394129525
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2969904618
Short name T360
Test name
Test status
Simulation time 43905959 ps
CPU time 1.3 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 197112 kb
Host smart-f7896f71-fad8-4000-8d7f-923364c41fad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969904618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2969904618
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3300923389
Short name T603
Test name
Test status
Simulation time 15952671225 ps
CPU time 101.55 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 07:01:11 PM PDT 24
Peak memory 198796 kb
Host smart-c0959281-6d2b-483e-9dff-66a3dc8128e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300923389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3300923389
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1041724335
Short name T605
Test name
Test status
Simulation time 14477789 ps
CPU time 0.6 seconds
Started Jul 17 06:57:21 PM PDT 24
Finished Jul 17 06:57:23 PM PDT 24
Peak memory 194856 kb
Host smart-59061337-a87d-4584-8be4-5efda514ae1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041724335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1041724335
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.98593054
Short name T409
Test name
Test status
Simulation time 38711132 ps
CPU time 0.82 seconds
Started Jul 17 06:57:20 PM PDT 24
Finished Jul 17 06:57:22 PM PDT 24
Peak memory 196048 kb
Host smart-9d9c6be7-f431-48cd-b730-fe02d176d445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98593054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.98593054
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2297547137
Short name T557
Test name
Test status
Simulation time 322569472 ps
CPU time 10.81 seconds
Started Jul 17 06:57:17 PM PDT 24
Finished Jul 17 06:57:29 PM PDT 24
Peak memory 197504 kb
Host smart-1d443887-1a34-4ae4-a3c2-d078c73be7b4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297547137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2297547137
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.4237163
Short name T258
Test name
Test status
Simulation time 428729713 ps
CPU time 1.04 seconds
Started Jul 17 06:57:15 PM PDT 24
Finished Jul 17 06:57:18 PM PDT 24
Peak memory 197316 kb
Host smart-3d79535e-7fc9-4bf1-ae68-b83a37db4db7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.4237163
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.254256194
Short name T653
Test name
Test status
Simulation time 69838689 ps
CPU time 1.22 seconds
Started Jul 17 06:57:18 PM PDT 24
Finished Jul 17 06:57:21 PM PDT 24
Peak memory 196560 kb
Host smart-304838e1-e578-4ba1-8edd-f21ab16f2f12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254256194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.254256194
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.423746707
Short name T33
Test name
Test status
Simulation time 27876789 ps
CPU time 1.24 seconds
Started Jul 17 06:57:19 PM PDT 24
Finished Jul 17 06:57:22 PM PDT 24
Peak memory 197860 kb
Host smart-829fa495-2d66-4602-9765-f33c2db669b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423746707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.423746707
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3790962785
Short name T578
Test name
Test status
Simulation time 25320531 ps
CPU time 0.91 seconds
Started Jul 17 06:57:20 PM PDT 24
Finished Jul 17 06:57:22 PM PDT 24
Peak memory 196944 kb
Host smart-9696df6b-bb05-45a4-a3b0-c99de2b8ebb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790962785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3790962785
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2872291595
Short name T674
Test name
Test status
Simulation time 77500450 ps
CPU time 1.35 seconds
Started Jul 17 06:57:16 PM PDT 24
Finished Jul 17 06:57:19 PM PDT 24
Peak memory 196564 kb
Host smart-b372ba16-94f2-49b9-924b-cef324e9846b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872291595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2872291595
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2094282188
Short name T136
Test name
Test status
Simulation time 275822538 ps
CPU time 1.26 seconds
Started Jul 17 06:57:18 PM PDT 24
Finished Jul 17 06:57:21 PM PDT 24
Peak memory 198784 kb
Host smart-567a32c1-f57d-43ea-8d43-e9581e482176
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094282188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2094282188
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.629281748
Short name T623
Test name
Test status
Simulation time 437533539 ps
CPU time 1.61 seconds
Started Jul 17 06:57:20 PM PDT 24
Finished Jul 17 06:57:23 PM PDT 24
Peak memory 198512 kb
Host smart-140db79a-9678-4295-8ba5-993174a75435
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629281748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.629281748
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2094203374
Short name T40
Test name
Test status
Simulation time 214808980 ps
CPU time 0.81 seconds
Started Jul 17 06:57:19 PM PDT 24
Finished Jul 17 06:57:22 PM PDT 24
Peak memory 214356 kb
Host smart-e66250bd-aa63-45ae-8f6f-a3da89965c75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094203374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2094203374
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3119325104
Short name T637
Test name
Test status
Simulation time 238148349 ps
CPU time 1.3 seconds
Started Jul 17 06:57:18 PM PDT 24
Finished Jul 17 06:57:21 PM PDT 24
Peak memory 197328 kb
Host smart-63f7ff6f-de2f-431b-8905-79d77f00d1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119325104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3119325104
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1031182680
Short name T451
Test name
Test status
Simulation time 121430094 ps
CPU time 0.71 seconds
Started Jul 17 06:57:17 PM PDT 24
Finished Jul 17 06:57:19 PM PDT 24
Peak memory 194752 kb
Host smart-1dc09f84-96f2-4c97-a007-3991c8fb4745
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031182680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1031182680
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.592190210
Short name T285
Test name
Test status
Simulation time 68641906780 ps
CPU time 147.8 seconds
Started Jul 17 06:57:15 PM PDT 24
Finished Jul 17 06:59:44 PM PDT 24
Peak memory 199048 kb
Host smart-4f5a0e40-5d3b-4e54-a2ce-a2636988178a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592190210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.592190210
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1638398629
Short name T36
Test name
Test status
Simulation time 35367299656 ps
CPU time 277.94 seconds
Started Jul 17 06:57:16 PM PDT 24
Finished Jul 17 07:01:55 PM PDT 24
Peak memory 198932 kb
Host smart-4a9aa155-58ef-4fd0-8a4a-2cd474e948c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1638398629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1638398629
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2984070645
Short name T220
Test name
Test status
Simulation time 21405355 ps
CPU time 0.59 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:22 PM PDT 24
Peak memory 195544 kb
Host smart-5e5bb5a3-0193-4828-b25e-ae0a70aac8d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984070645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2984070645
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.773616011
Short name T495
Test name
Test status
Simulation time 26915417 ps
CPU time 0.89 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:25 PM PDT 24
Peak memory 196800 kb
Host smart-ebd1b0d5-577c-42a0-ba59-2a6a2a12aeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773616011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.773616011
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2814891442
Short name T13
Test name
Test status
Simulation time 262996272 ps
CPU time 7.8 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 196980 kb
Host smart-ad1f2ba1-85e3-449a-95a9-cc4dff23b664
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814891442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2814891442
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3089122887
Short name T649
Test name
Test status
Simulation time 27513098 ps
CPU time 0.7 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:24 PM PDT 24
Peak memory 196016 kb
Host smart-d8ca17e7-2155-4ef1-890a-74f259f64b26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089122887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3089122887
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.17049295
Short name T466
Test name
Test status
Simulation time 84845952 ps
CPU time 1.3 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:23 PM PDT 24
Peak memory 197876 kb
Host smart-2591e1b6-2280-4648-a841-a899ca1442ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17049295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.17049295
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3193735868
Short name T441
Test name
Test status
Simulation time 22817174 ps
CPU time 0.95 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:21 PM PDT 24
Peak memory 197408 kb
Host smart-162e081f-f4ef-4c8c-98e3-075799c9fff4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193735868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3193735868
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2353588059
Short name T286
Test name
Test status
Simulation time 392128465 ps
CPU time 2.95 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:25 PM PDT 24
Peak memory 197556 kb
Host smart-b9a96147-be91-4676-8b06-1d8af85bf99c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353588059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2353588059
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2361048310
Short name T143
Test name
Test status
Simulation time 85881817 ps
CPU time 0.68 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:28 PM PDT 24
Peak memory 195008 kb
Host smart-da4480c5-5400-421c-be04-0262bfcb446b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361048310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2361048310
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.114326236
Short name T613
Test name
Test status
Simulation time 69310503 ps
CPU time 0.9 seconds
Started Jul 17 06:59:21 PM PDT 24
Finished Jul 17 06:59:30 PM PDT 24
Peak memory 196672 kb
Host smart-949da41d-7928-4138-9ba4-2e312c07e9d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114326236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.114326236
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.500002812
Short name T189
Test name
Test status
Simulation time 1789946708 ps
CPU time 5.77 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:26 PM PDT 24
Peak memory 198600 kb
Host smart-b9a61983-859b-401c-868d-5dd086ca970e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500002812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.500002812
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2740339665
Short name T322
Test name
Test status
Simulation time 46996390 ps
CPU time 1.3 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:48 PM PDT 24
Peak memory 197524 kb
Host smart-750355f9-e621-4e3d-acd2-5ba0e4310953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740339665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2740339665
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3171999758
Short name T455
Test name
Test status
Simulation time 68996904 ps
CPU time 1.15 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 196564 kb
Host smart-aea8aacd-c139-4703-8993-ee7127dc1802
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171999758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3171999758
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1514812483
Short name T405
Test name
Test status
Simulation time 6074671328 ps
CPU time 63.7 seconds
Started Jul 17 06:59:19 PM PDT 24
Finished Jul 17 07:00:28 PM PDT 24
Peak memory 198808 kb
Host smart-2424ebd6-ca12-40ba-badd-da8d1df21fd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514812483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1514812483
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.754155710
Short name T176
Test name
Test status
Simulation time 243110861 ps
CPU time 0.58 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 195608 kb
Host smart-34d6580f-5b25-4228-88f4-32ee187e61f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754155710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.754155710
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1608194720
Short name T619
Test name
Test status
Simulation time 240783885 ps
CPU time 0.63 seconds
Started Jul 17 06:59:21 PM PDT 24
Finished Jul 17 06:59:30 PM PDT 24
Peak memory 194756 kb
Host smart-c7b1fa33-2b08-457c-a04b-28377ecd6b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608194720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1608194720
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2822548102
Short name T139
Test name
Test status
Simulation time 939280302 ps
CPU time 24.82 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:54 PM PDT 24
Peak memory 197860 kb
Host smart-f241db68-0dc9-446d-ab99-85f0661549eb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822548102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2822548102
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.293866928
Short name T561
Test name
Test status
Simulation time 136405864 ps
CPU time 0.75 seconds
Started Jul 17 06:59:24 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 196472 kb
Host smart-34eb305d-544e-4d12-a7c6-efbfddc37f3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293866928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.293866928
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.864155261
Short name T579
Test name
Test status
Simulation time 98731320 ps
CPU time 1.27 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:25 PM PDT 24
Peak memory 198728 kb
Host smart-5de1534d-9d0e-4357-95b0-1e00ffb47d26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864155261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.864155261
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3455951513
Short name T656
Test name
Test status
Simulation time 51653436 ps
CPU time 2.07 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 198768 kb
Host smart-7566e722-27ab-4e84-a998-2c6df9a29810
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455951513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3455951513
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3288743847
Short name T181
Test name
Test status
Simulation time 110676999 ps
CPU time 2.3 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:35 PM PDT 24
Peak memory 196864 kb
Host smart-3f56194b-8275-49ab-b672-bf241ea917b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288743847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3288743847
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1689470884
Short name T521
Test name
Test status
Simulation time 74192573 ps
CPU time 0.76 seconds
Started Jul 17 06:59:21 PM PDT 24
Finished Jul 17 06:59:30 PM PDT 24
Peak memory 195984 kb
Host smart-3984f3b0-5664-4a6f-809d-20b8da60a05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689470884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1689470884
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3011768078
Short name T185
Test name
Test status
Simulation time 112207423 ps
CPU time 0.97 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 197212 kb
Host smart-a59f8909-0d95-4aef-ac8f-e8b211f7c5ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011768078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3011768078
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.4081365346
Short name T665
Test name
Test status
Simulation time 303048613 ps
CPU time 3.94 seconds
Started Jul 17 06:59:19 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 198624 kb
Host smart-d255b8f8-1b93-44fc-9efb-636f52d7e44e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081365346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.4081365346
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3810445047
Short name T11
Test name
Test status
Simulation time 180005507 ps
CPU time 1.36 seconds
Started Jul 17 06:59:21 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 196312 kb
Host smart-a3283c8f-ad8a-4c1d-961e-71f1340510e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810445047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3810445047
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1608497179
Short name T266
Test name
Test status
Simulation time 105503007 ps
CPU time 1.17 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 196228 kb
Host smart-405e260b-6649-4f86-b1f8-beb7f889960d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608497179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1608497179
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.4186638457
Short name T9
Test name
Test status
Simulation time 28841609468 ps
CPU time 124.04 seconds
Started Jul 17 06:59:21 PM PDT 24
Finished Jul 17 07:01:33 PM PDT 24
Peak memory 198808 kb
Host smart-42d24ea8-250a-412d-add2-fc9eb47bf4e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186638457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.4186638457
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3547174505
Short name T44
Test name
Test status
Simulation time 32700988 ps
CPU time 0.54 seconds
Started Jul 17 06:59:24 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 195308 kb
Host smart-ffd79bc4-a6c8-4080-983c-6ad2632b5ace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547174505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3547174505
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.4109396199
Short name T685
Test name
Test status
Simulation time 428354292 ps
CPU time 0.81 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 195976 kb
Host smart-9cbb7b66-b7e7-4f27-bc04-eff1015507b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109396199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.4109396199
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3282330600
Short name T675
Test name
Test status
Simulation time 322118741 ps
CPU time 10.39 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:43 PM PDT 24
Peak memory 197628 kb
Host smart-6a1d525d-52c0-4410-a0ae-40e0c5bb41d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282330600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3282330600
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1216403321
Short name T706
Test name
Test status
Simulation time 56821921 ps
CPU time 0.89 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 198284 kb
Host smart-d09e0b68-c300-4463-a4b2-1ed829cd1169
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216403321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1216403321
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2030931745
Short name T124
Test name
Test status
Simulation time 135180972 ps
CPU time 0.92 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:32 PM PDT 24
Peak memory 197324 kb
Host smart-4b13e63c-9946-4681-8f50-e5913a8adc1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030931745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2030931745
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3523165966
Short name T264
Test name
Test status
Simulation time 22527654 ps
CPU time 1.12 seconds
Started Jul 17 06:59:24 PM PDT 24
Finished Jul 17 06:59:34 PM PDT 24
Peak memory 196952 kb
Host smart-dc361af2-c945-4d40-a19d-d9c41132f8d0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523165966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3523165966
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2990610069
Short name T710
Test name
Test status
Simulation time 125598293 ps
CPU time 2.76 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:35 PM PDT 24
Peak memory 198724 kb
Host smart-7aac2f65-f835-494a-b220-07a7efcdd8e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990610069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2990610069
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2372428691
Short name T525
Test name
Test status
Simulation time 56597970 ps
CPU time 0.67 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 195024 kb
Host smart-27c18ac5-2a56-473c-b3c2-dfca0b922e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372428691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2372428691
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1310038052
Short name T437
Test name
Test status
Simulation time 326631998 ps
CPU time 1.31 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 198700 kb
Host smart-c3ca319d-2b3d-4513-b053-53a749ed168e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310038052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1310038052
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3223159547
Short name T570
Test name
Test status
Simulation time 150909951 ps
CPU time 1.93 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:32 PM PDT 24
Peak memory 198548 kb
Host smart-c2f39fe0-020e-4285-8a1a-6d9b3fca86cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223159547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3223159547
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2213659341
Short name T179
Test name
Test status
Simulation time 71654388 ps
CPU time 1.23 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:23 PM PDT 24
Peak memory 196212 kb
Host smart-5e6f7e45-189c-49c6-800b-68d5499b8930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213659341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2213659341
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2461681576
Short name T520
Test name
Test status
Simulation time 41094611 ps
CPU time 1.15 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 196384 kb
Host smart-48b156d0-4585-453e-87e4-121ab1c1c885
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461681576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2461681576
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2159800961
Short name T470
Test name
Test status
Simulation time 203407289934 ps
CPU time 136.72 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 07:01:47 PM PDT 24
Peak memory 198768 kb
Host smart-5eea829b-0f34-4d3e-8520-4bb202b91774
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159800961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2159800961
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1626157600
Short name T598
Test name
Test status
Simulation time 13289930 ps
CPU time 0.58 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:23 PM PDT 24
Peak memory 195384 kb
Host smart-75d20b75-1483-42aa-a41c-ab57e8ae7b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626157600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1626157600
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2275576076
Short name T545
Test name
Test status
Simulation time 52607503 ps
CPU time 0.91 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:32 PM PDT 24
Peak memory 196448 kb
Host smart-a502faa7-1aae-40d9-a097-1ff2ccd407b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275576076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2275576076
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2568091642
Short name T210
Test name
Test status
Simulation time 440119405 ps
CPU time 20.36 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 06:59:44 PM PDT 24
Peak memory 196244 kb
Host smart-270a31b8-dab0-4b1d-b779-6c444b4c5cb5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568091642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2568091642
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2013171084
Short name T526
Test name
Test status
Simulation time 147845930 ps
CPU time 1 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 198776 kb
Host smart-3bc4a744-d668-44c6-919d-c7ab92224ba4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013171084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2013171084
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.134236131
Short name T81
Test name
Test status
Simulation time 147610599 ps
CPU time 1.3 seconds
Started Jul 17 06:59:27 PM PDT 24
Finished Jul 17 06:59:35 PM PDT 24
Peak memory 197924 kb
Host smart-d709bb1c-0ad9-4a21-a653-6469839ab2ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134236131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.134236131
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1651881691
Short name T80
Test name
Test status
Simulation time 47640238 ps
CPU time 1.89 seconds
Started Jul 17 06:59:28 PM PDT 24
Finished Jul 17 06:59:36 PM PDT 24
Peak memory 198696 kb
Host smart-9024326c-f8ab-40cc-9b0e-1fdcad91991d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651881691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1651881691
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.212180970
Short name T65
Test name
Test status
Simulation time 534874352 ps
CPU time 3.37 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 196516 kb
Host smart-2bd9d5b2-d43e-43f0-be1c-528ae01e5e59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212180970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
212180970
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2205602189
Short name T635
Test name
Test status
Simulation time 65819279 ps
CPU time 1.13 seconds
Started Jul 17 06:59:27 PM PDT 24
Finished Jul 17 06:59:34 PM PDT 24
Peak memory 197856 kb
Host smart-d06b644a-224e-49a1-a0f7-6f7bdd901558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205602189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2205602189
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2501217154
Short name T87
Test name
Test status
Simulation time 116922779 ps
CPU time 0.93 seconds
Started Jul 17 06:59:27 PM PDT 24
Finished Jul 17 06:59:34 PM PDT 24
Peak memory 196704 kb
Host smart-12196153-44cd-4572-a113-56e3c3382e6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501217154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2501217154
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.900740471
Short name T508
Test name
Test status
Simulation time 40771172 ps
CPU time 1.76 seconds
Started Jul 17 06:59:20 PM PDT 24
Finished Jul 17 06:59:30 PM PDT 24
Peak memory 198632 kb
Host smart-17f14ad4-e098-44be-9b9b-17f3cc4e635e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900740471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.900740471
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1523621182
Short name T460
Test name
Test status
Simulation time 73756263 ps
CPU time 1.14 seconds
Started Jul 17 06:59:23 PM PDT 24
Finished Jul 17 06:59:33 PM PDT 24
Peak memory 196368 kb
Host smart-a00db395-c6ce-4a0f-bb33-8d9a7b80c73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523621182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1523621182
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.584932777
Short name T673
Test name
Test status
Simulation time 72203062 ps
CPU time 1.14 seconds
Started Jul 17 06:59:28 PM PDT 24
Finished Jul 17 06:59:35 PM PDT 24
Peak memory 196240 kb
Host smart-b60d0ce9-fad9-40b3-8dda-0a61d9775d5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584932777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.584932777
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.4248798020
Short name T709
Test name
Test status
Simulation time 21248701566 ps
CPU time 69.65 seconds
Started Jul 17 06:59:18 PM PDT 24
Finished Jul 17 07:00:32 PM PDT 24
Peak memory 198772 kb
Host smart-717ac8da-71cc-4d4c-8793-b198f4595b3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248798020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.4248798020
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2104115112
Short name T57
Test name
Test status
Simulation time 65358484 ps
CPU time 0.58 seconds
Started Jul 17 06:59:34 PM PDT 24
Finished Jul 17 06:59:38 PM PDT 24
Peak memory 194872 kb
Host smart-bb2b62b5-f4f7-4010-89d1-93ac2af2256c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104115112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2104115112
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2351525618
Short name T582
Test name
Test status
Simulation time 43670101 ps
CPU time 0.74 seconds
Started Jul 17 06:59:33 PM PDT 24
Finished Jul 17 06:59:37 PM PDT 24
Peak memory 196660 kb
Host smart-ef2ae2a9-8350-4fc4-ac5c-f385ac466c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351525618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2351525618
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2815032395
Short name T576
Test name
Test status
Simulation time 524229727 ps
CPU time 13.87 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 06:59:53 PM PDT 24
Peak memory 197448 kb
Host smart-41e778c1-9739-4428-9483-c0a52a44b9a1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815032395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2815032395
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.555065358
Short name T445
Test name
Test status
Simulation time 147115152 ps
CPU time 1.12 seconds
Started Jul 17 06:59:31 PM PDT 24
Finished Jul 17 06:59:36 PM PDT 24
Peak memory 198640 kb
Host smart-df9809af-e019-4c31-b0f6-67d1ed66d26d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555065358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.555065358
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.4283866528
Short name T399
Test name
Test status
Simulation time 313553821 ps
CPU time 1.31 seconds
Started Jul 17 06:59:31 PM PDT 24
Finished Jul 17 06:59:36 PM PDT 24
Peak memory 198004 kb
Host smart-d35f7dcf-7f81-4c4e-ba62-0204783d01f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283866528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.4283866528
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1309156570
Short name T323
Test name
Test status
Simulation time 67041495 ps
CPU time 2.51 seconds
Started Jul 17 06:59:35 PM PDT 24
Finished Jul 17 06:59:41 PM PDT 24
Peak memory 198696 kb
Host smart-4f198fe7-6020-4eec-9d0e-0e6f10904d87
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309156570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1309156570
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.871650246
Short name T682
Test name
Test status
Simulation time 43143629 ps
CPU time 1.08 seconds
Started Jul 17 06:59:37 PM PDT 24
Finished Jul 17 06:59:42 PM PDT 24
Peak memory 196168 kb
Host smart-0eae2278-dd24-4008-a563-e8f2eb6932cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871650246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
871650246
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1564531280
Short name T667
Test name
Test status
Simulation time 19952058 ps
CPU time 0.66 seconds
Started Jul 17 06:59:32 PM PDT 24
Finished Jul 17 06:59:36 PM PDT 24
Peak memory 195620 kb
Host smart-3468f134-84df-4707-a4f0-d7eea376128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564531280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1564531280
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2271839463
Short name T353
Test name
Test status
Simulation time 94413276 ps
CPU time 0.89 seconds
Started Jul 17 06:59:35 PM PDT 24
Finished Jul 17 06:59:39 PM PDT 24
Peak memory 196648 kb
Host smart-52ccf683-e0aa-4db9-ad06-e98ad669c545
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271839463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2271839463
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1655972511
Short name T321
Test name
Test status
Simulation time 607405389 ps
CPU time 3.86 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 06:59:43 PM PDT 24
Peak memory 198680 kb
Host smart-9d48679b-a005-4e84-af9b-5630400466f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655972511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1655972511
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.691120402
Short name T676
Test name
Test status
Simulation time 154545556 ps
CPU time 1.1 seconds
Started Jul 17 06:59:22 PM PDT 24
Finished Jul 17 06:59:30 PM PDT 24
Peak memory 197248 kb
Host smart-9b40638d-ce6e-4b77-ac77-bd6cdc7e18a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691120402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.691120402
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1855758501
Short name T341
Test name
Test status
Simulation time 35767392 ps
CPU time 1.15 seconds
Started Jul 17 06:59:35 PM PDT 24
Finished Jul 17 06:59:39 PM PDT 24
Peak memory 197148 kb
Host smart-73a5d6c8-76db-4269-87b6-6f364eefbc46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855758501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1855758501
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.284895223
Short name T7
Test name
Test status
Simulation time 219538776523 ps
CPU time 198.47 seconds
Started Jul 17 06:59:33 PM PDT 24
Finished Jul 17 07:02:54 PM PDT 24
Peak memory 198840 kb
Host smart-1a8bfb71-72bb-43be-89c3-c1326d2e8cc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284895223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.284895223
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.491054800
Short name T391
Test name
Test status
Simulation time 11211479 ps
CPU time 0.58 seconds
Started Jul 17 06:59:38 PM PDT 24
Finished Jul 17 06:59:42 PM PDT 24
Peak memory 195368 kb
Host smart-4c2eac20-0614-475a-a0f9-bb00df4c1d39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491054800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.491054800
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2355863861
Short name T448
Test name
Test status
Simulation time 83726317 ps
CPU time 0.92 seconds
Started Jul 17 06:59:32 PM PDT 24
Finished Jul 17 06:59:36 PM PDT 24
Peak memory 196472 kb
Host smart-5828106a-58e4-4ed2-93a4-1037597d64f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355863861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2355863861
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3479647225
Short name T278
Test name
Test status
Simulation time 243244021 ps
CPU time 12.57 seconds
Started Jul 17 06:59:37 PM PDT 24
Finished Jul 17 06:59:54 PM PDT 24
Peak memory 197388 kb
Host smart-0567efdb-f488-4e25-9eaa-6f8779c4889a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479647225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3479647225
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1630145837
Short name T477
Test name
Test status
Simulation time 60232064 ps
CPU time 0.96 seconds
Started Jul 17 06:59:35 PM PDT 24
Finished Jul 17 06:59:39 PM PDT 24
Peak memory 197316 kb
Host smart-b4b50cc3-cd52-42b5-a925-c2ab79c538ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630145837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1630145837
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.4251155883
Short name T282
Test name
Test status
Simulation time 1071114042 ps
CPU time 1.41 seconds
Started Jul 17 06:59:31 PM PDT 24
Finished Jul 17 06:59:36 PM PDT 24
Peak memory 197552 kb
Host smart-57b55467-1b20-44a4-b104-c45006269ba9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251155883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.4251155883
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3697194821
Short name T655
Test name
Test status
Simulation time 473803233 ps
CPU time 3.43 seconds
Started Jul 17 06:59:35 PM PDT 24
Finished Jul 17 06:59:42 PM PDT 24
Peak memory 197788 kb
Host smart-6d27e06c-c973-443f-a0b5-79ade98e5004
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697194821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3697194821
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1405229674
Short name T82
Test name
Test status
Simulation time 46511912 ps
CPU time 0.71 seconds
Started Jul 17 06:59:31 PM PDT 24
Finished Jul 17 06:59:36 PM PDT 24
Peak memory 196072 kb
Host smart-f542feab-4811-432e-9d2a-2e4c8f074ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405229674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1405229674
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.4262526472
Short name T201
Test name
Test status
Simulation time 96412449 ps
CPU time 0.78 seconds
Started Jul 17 06:59:35 PM PDT 24
Finished Jul 17 06:59:39 PM PDT 24
Peak memory 196208 kb
Host smart-d8188381-4f0d-4c80-8c01-5b37ad7e02e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262526472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.4262526472
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3878149769
Short name T17
Test name
Test status
Simulation time 432312763 ps
CPU time 4.87 seconds
Started Jul 17 06:59:37 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 198640 kb
Host smart-899bf360-4378-4b75-b4d7-e1aff2b86826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878149769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3878149769
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.80937907
Short name T369
Test name
Test status
Simulation time 162961916 ps
CPU time 1.02 seconds
Started Jul 17 06:59:34 PM PDT 24
Finished Jul 17 06:59:37 PM PDT 24
Peak memory 196984 kb
Host smart-242841ef-216e-4e1e-82e3-6ff9c9b328a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80937907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.80937907
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3492412869
Short name T640
Test name
Test status
Simulation time 47607725 ps
CPU time 1.16 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 06:59:40 PM PDT 24
Peak memory 196508 kb
Host smart-c2f6cdd2-5d97-4bc6-87d0-de9161f3d90e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492412869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3492412869
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1487389569
Short name T418
Test name
Test status
Simulation time 6200682842 ps
CPU time 81.49 seconds
Started Jul 17 06:59:35 PM PDT 24
Finished Jul 17 07:01:00 PM PDT 24
Peak memory 198736 kb
Host smart-28ef3895-987a-457c-8c29-3b1661e1fa06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487389569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1487389569
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.3236962258
Short name T407
Test name
Test status
Simulation time 26605876533 ps
CPU time 547.63 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 07:08:47 PM PDT 24
Peak memory 198948 kb
Host smart-dca87ea4-c37f-4fdd-a22e-141849e08925
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3236962258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.3236962258
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.344672385
Short name T620
Test name
Test status
Simulation time 38792038 ps
CPU time 0.54 seconds
Started Jul 17 06:59:35 PM PDT 24
Finished Jul 17 06:59:39 PM PDT 24
Peak memory 193420 kb
Host smart-a99c095f-9613-4028-9aab-f60d808b850f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344672385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.344672385
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.15185334
Short name T358
Test name
Test status
Simulation time 21598267 ps
CPU time 0.71 seconds
Started Jul 17 06:59:35 PM PDT 24
Finished Jul 17 06:59:38 PM PDT 24
Peak memory 195988 kb
Host smart-8b52249c-717d-4b5b-a58b-70af44253ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15185334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.15185334
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.95240455
Short name T187
Test name
Test status
Simulation time 1080036399 ps
CPU time 16.78 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 06:59:57 PM PDT 24
Peak memory 196184 kb
Host smart-6b547ea9-c086-4b1e-bdc0-0f9b30b2cf61
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95240455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stress
.95240455
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2039514255
Short name T480
Test name
Test status
Simulation time 60535419 ps
CPU time 0.83 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 06:59:40 PM PDT 24
Peak memory 196688 kb
Host smart-3d1135d8-6496-455c-b552-a54bb2813015
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039514255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2039514255
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2207186878
Short name T273
Test name
Test status
Simulation time 20368733 ps
CPU time 0.68 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 06:59:40 PM PDT 24
Peak memory 194976 kb
Host smart-a99dcbb3-e9cc-4bd3-990e-51b39dc595d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207186878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2207186878
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.114746667
Short name T362
Test name
Test status
Simulation time 63473696 ps
CPU time 2.41 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 06:59:42 PM PDT 24
Peak memory 198644 kb
Host smart-0e951cb5-61d0-4b11-909a-09946b35751e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114746667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.114746667
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3403113541
Short name T312
Test name
Test status
Simulation time 46633312 ps
CPU time 1.48 seconds
Started Jul 17 06:59:33 PM PDT 24
Finished Jul 17 06:59:38 PM PDT 24
Peak memory 197352 kb
Host smart-584b933c-e4d7-41a0-80f9-c7a3a90022ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403113541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3403113541
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2632900077
Short name T228
Test name
Test status
Simulation time 64830817 ps
CPU time 1.18 seconds
Started Jul 17 06:59:34 PM PDT 24
Finished Jul 17 06:59:38 PM PDT 24
Peak memory 196504 kb
Host smart-6c2f5733-ea49-4b8e-9880-9f6e4fb67ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632900077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2632900077
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1515987279
Short name T311
Test name
Test status
Simulation time 78091321 ps
CPU time 0.83 seconds
Started Jul 17 06:59:33 PM PDT 24
Finished Jul 17 06:59:37 PM PDT 24
Peak memory 197972 kb
Host smart-f9ee7ab2-fdb7-4290-ae59-c722e7cf2ef8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515987279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1515987279
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1639194078
Short name T297
Test name
Test status
Simulation time 3862633651 ps
CPU time 4 seconds
Started Jul 17 06:59:34 PM PDT 24
Finished Jul 17 06:59:42 PM PDT 24
Peak memory 198716 kb
Host smart-4fed6341-182c-445d-9ce6-9b5892f8b890
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639194078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1639194078
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3587695181
Short name T499
Test name
Test status
Simulation time 97091138 ps
CPU time 1.27 seconds
Started Jul 17 06:59:37 PM PDT 24
Finished Jul 17 06:59:42 PM PDT 24
Peak memory 197272 kb
Host smart-76eab4d1-cb90-4a70-ab73-fd5a73e6ffc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587695181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3587695181
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1789956590
Short name T669
Test name
Test status
Simulation time 37951678 ps
CPU time 1.04 seconds
Started Jul 17 06:59:33 PM PDT 24
Finished Jul 17 06:59:37 PM PDT 24
Peak memory 196260 kb
Host smart-fa77414f-624d-49b2-aa19-d47e6c62ded7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789956590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1789956590
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.627172747
Short name T6
Test name
Test status
Simulation time 11745576470 ps
CPU time 120.45 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 07:01:40 PM PDT 24
Peak memory 198800 kb
Host smart-4b6959e4-a4d0-4a74-8a33-8c96aca6fd72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627172747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.627172747
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.305812588
Short name T531
Test name
Test status
Simulation time 17618378 ps
CPU time 0.58 seconds
Started Jul 17 06:59:43 PM PDT 24
Finished Jul 17 06:59:47 PM PDT 24
Peak memory 194852 kb
Host smart-08bee8c0-2cf7-41a9-bc94-fd39c9fa0f16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305812588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.305812588
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.996442118
Short name T591
Test name
Test status
Simulation time 42756750 ps
CPU time 0.59 seconds
Started Jul 17 06:59:39 PM PDT 24
Finished Jul 17 06:59:43 PM PDT 24
Peak memory 194488 kb
Host smart-c426ecac-b199-489d-9fe3-0e95d3f408ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996442118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.996442118
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3898020986
Short name T344
Test name
Test status
Simulation time 2879486357 ps
CPU time 20.22 seconds
Started Jul 17 06:59:39 PM PDT 24
Finished Jul 17 07:00:03 PM PDT 24
Peak memory 197668 kb
Host smart-a3e7fe4e-d689-4aac-99b4-2a2e2bd50aec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898020986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3898020986
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.387925312
Short name T268
Test name
Test status
Simulation time 234377572 ps
CPU time 1.05 seconds
Started Jul 17 06:59:43 PM PDT 24
Finished Jul 17 06:59:48 PM PDT 24
Peak memory 198492 kb
Host smart-355dd2f0-c40f-42a1-b851-e33cef4a5f44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387925312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.387925312
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2065598483
Short name T527
Test name
Test status
Simulation time 24405680 ps
CPU time 0.71 seconds
Started Jul 17 06:59:39 PM PDT 24
Finished Jul 17 06:59:43 PM PDT 24
Peak memory 196820 kb
Host smart-08a66519-4b76-4aa3-9971-98850b7691ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065598483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2065598483
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3601461289
Short name T664
Test name
Test status
Simulation time 24859508 ps
CPU time 1.04 seconds
Started Jul 17 06:59:39 PM PDT 24
Finished Jul 17 06:59:44 PM PDT 24
Peak memory 197020 kb
Host smart-987284d6-ab50-4725-8d59-63681dea21db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601461289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3601461289
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3430261752
Short name T473
Test name
Test status
Simulation time 59444688 ps
CPU time 1.4 seconds
Started Jul 17 06:59:43 PM PDT 24
Finished Jul 17 06:59:48 PM PDT 24
Peak memory 198224 kb
Host smart-1b35846b-27b3-4154-ac8d-18ded5948890
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430261752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3430261752
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1273937540
Short name T15
Test name
Test status
Simulation time 29631448 ps
CPU time 1.13 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 06:59:41 PM PDT 24
Peak memory 197740 kb
Host smart-c4bd4baf-a3b4-4f7e-a382-3bd223801dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273937540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1273937540
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.476589261
Short name T549
Test name
Test status
Simulation time 26754807 ps
CPU time 0.84 seconds
Started Jul 17 06:59:43 PM PDT 24
Finished Jul 17 06:59:48 PM PDT 24
Peak memory 196856 kb
Host smart-56ed1c9e-d64b-4535-a748-7c342e20afb8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476589261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.476589261
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2060425634
Short name T190
Test name
Test status
Simulation time 2213361722 ps
CPU time 5.46 seconds
Started Jul 17 06:59:43 PM PDT 24
Finished Jul 17 06:59:51 PM PDT 24
Peak memory 198684 kb
Host smart-083a07f5-2176-49f2-9f5b-569fdd68e175
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060425634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2060425634
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.487689224
Short name T188
Test name
Test status
Simulation time 75647808 ps
CPU time 1.22 seconds
Started Jul 17 06:59:37 PM PDT 24
Finished Jul 17 06:59:42 PM PDT 24
Peak memory 196488 kb
Host smart-2d58bb5d-e491-4724-bef1-d64a89ee55bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487689224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.487689224
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1338141213
Short name T288
Test name
Test status
Simulation time 158097206 ps
CPU time 1 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 06:59:41 PM PDT 24
Peak memory 197132 kb
Host smart-80957439-a51a-490b-9f42-91732d5dc690
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338141213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1338141213
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.4009823418
Short name T10
Test name
Test status
Simulation time 25262921313 ps
CPU time 69.98 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 07:00:50 PM PDT 24
Peak memory 198792 kb
Host smart-1baa2293-ee83-4df5-9547-cd7fd805dd73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009823418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.4009823418
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.4186562536
Short name T251
Test name
Test status
Simulation time 48894651 ps
CPU time 0.56 seconds
Started Jul 17 06:59:42 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 195384 kb
Host smart-38f6daf8-4667-4ecc-a80d-ae68b13425a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186562536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.4186562536
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3656466874
Short name T235
Test name
Test status
Simulation time 89124973 ps
CPU time 0.79 seconds
Started Jul 17 06:59:43 PM PDT 24
Finished Jul 17 06:59:47 PM PDT 24
Peak memory 196092 kb
Host smart-e10d55ee-8ceb-499a-b40c-6b395c1ecb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656466874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3656466874
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3192341865
Short name T683
Test name
Test status
Simulation time 311223380 ps
CPU time 8.44 seconds
Started Jul 17 06:59:43 PM PDT 24
Finished Jul 17 06:59:55 PM PDT 24
Peak memory 196204 kb
Host smart-81615a62-7d40-46e6-ae69-34dc90646583
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192341865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3192341865
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.4021472873
Short name T206
Test name
Test status
Simulation time 294374100 ps
CPU time 0.96 seconds
Started Jul 17 06:59:34 PM PDT 24
Finished Jul 17 06:59:37 PM PDT 24
Peak memory 198320 kb
Host smart-49e78049-34ff-4041-aeed-5f8d1da6ceb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021472873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.4021472873
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1609727126
Short name T559
Test name
Test status
Simulation time 61380423 ps
CPU time 0.89 seconds
Started Jul 17 06:59:41 PM PDT 24
Finished Jul 17 06:59:45 PM PDT 24
Peak memory 196680 kb
Host smart-8236726f-cefb-4567-94cc-cd8942fcc96d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609727126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1609727126
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2112914335
Short name T454
Test name
Test status
Simulation time 240808578 ps
CPU time 2.6 seconds
Started Jul 17 06:59:41 PM PDT 24
Finished Jul 17 06:59:47 PM PDT 24
Peak memory 198556 kb
Host smart-9e9d3093-8a18-43fa-83d8-f47501dbce8f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112914335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2112914335
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.897246233
Short name T349
Test name
Test status
Simulation time 55630654 ps
CPU time 1.29 seconds
Started Jul 17 06:59:42 PM PDT 24
Finished Jul 17 06:59:47 PM PDT 24
Peak memory 196480 kb
Host smart-41672493-ac93-4e38-b7f1-562e286885f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897246233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
897246233
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.158556136
Short name T301
Test name
Test status
Simulation time 33414228 ps
CPU time 0.83 seconds
Started Jul 17 06:59:34 PM PDT 24
Finished Jul 17 06:59:38 PM PDT 24
Peak memory 197068 kb
Host smart-9958ac35-28f2-40ac-bef4-37a03f1a6c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158556136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.158556136
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.323142814
Short name T310
Test name
Test status
Simulation time 30834133 ps
CPU time 0.77 seconds
Started Jul 17 06:59:42 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 196196 kb
Host smart-5935061a-ce42-4cd8-a40a-50a824aa6944
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323142814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.323142814
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.4162697032
Short name T389
Test name
Test status
Simulation time 331788016 ps
CPU time 4.2 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:52 PM PDT 24
Peak memory 198680 kb
Host smart-43aeb371-96a2-4568-b4e6-66253496ad88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162697032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.4162697032
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2571249565
Short name T693
Test name
Test status
Simulation time 51016259 ps
CPU time 1.35 seconds
Started Jul 17 06:59:43 PM PDT 24
Finished Jul 17 06:59:48 PM PDT 24
Peak memory 197396 kb
Host smart-c8172aa0-ea78-4065-b14d-e656184c85c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571249565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2571249565
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1660592978
Short name T20
Test name
Test status
Simulation time 135704017 ps
CPU time 0.99 seconds
Started Jul 17 06:59:42 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 197128 kb
Host smart-0dee015a-6bd2-495a-9120-03ff918d88f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660592978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1660592978
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2713778847
Short name T641
Test name
Test status
Simulation time 15268926087 ps
CPU time 166.69 seconds
Started Jul 17 06:59:41 PM PDT 24
Finished Jul 17 07:02:30 PM PDT 24
Peak memory 198800 kb
Host smart-36046e7a-831d-4084-b918-1a340ec7fed7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713778847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2713778847
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3178367481
Short name T364
Test name
Test status
Simulation time 16715504 ps
CPU time 0.57 seconds
Started Jul 17 06:59:33 PM PDT 24
Finished Jul 17 06:59:36 PM PDT 24
Peak memory 196404 kb
Host smart-bbe870c3-0c6f-4abc-8c90-099264e3aa09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178367481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3178367481
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.217915859
Short name T697
Test name
Test status
Simulation time 28828311 ps
CPU time 0.91 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 06:59:41 PM PDT 24
Peak memory 197244 kb
Host smart-874d269a-b9a1-4c10-9993-2396ef5a902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217915859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.217915859
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2337565997
Short name T306
Test name
Test status
Simulation time 1681099903 ps
CPU time 10.04 seconds
Started Jul 17 06:59:38 PM PDT 24
Finished Jul 17 06:59:52 PM PDT 24
Peak memory 197604 kb
Host smart-4218d84a-92b6-40f5-ba6d-d1895904cf22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337565997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2337565997
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2040804988
Short name T239
Test name
Test status
Simulation time 197051751 ps
CPU time 1.03 seconds
Started Jul 17 06:59:37 PM PDT 24
Finished Jul 17 06:59:42 PM PDT 24
Peak memory 198520 kb
Host smart-bf2a274c-e026-4c5b-ba4b-41eb83787525
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040804988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2040804988
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3163289957
Short name T351
Test name
Test status
Simulation time 100508338 ps
CPU time 0.85 seconds
Started Jul 17 06:59:43 PM PDT 24
Finished Jul 17 06:59:48 PM PDT 24
Peak memory 197452 kb
Host smart-438caaf5-c38f-459b-bde3-25bc9122b82e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163289957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3163289957
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.4110964828
Short name T211
Test name
Test status
Simulation time 281952278 ps
CPU time 2.86 seconds
Started Jul 17 06:59:36 PM PDT 24
Finished Jul 17 06:59:43 PM PDT 24
Peak memory 198832 kb
Host smart-f856221d-f959-499f-99b8-dd72e6a17142
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110964828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.4110964828
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.681939738
Short name T571
Test name
Test status
Simulation time 365496899 ps
CPU time 2.1 seconds
Started Jul 17 06:59:41 PM PDT 24
Finished Jul 17 06:59:46 PM PDT 24
Peak memory 196532 kb
Host smart-37060018-6029-4329-8027-93f916a55854
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681939738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
681939738
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1044196236
Short name T249
Test name
Test status
Simulation time 126547598 ps
CPU time 0.88 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:49 PM PDT 24
Peak memory 197232 kb
Host smart-6f0ece62-7399-4fff-825d-483a93f9ce00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044196236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1044196236
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.4151576650
Short name T393
Test name
Test status
Simulation time 136277108 ps
CPU time 1.01 seconds
Started Jul 17 06:59:35 PM PDT 24
Finished Jul 17 06:59:39 PM PDT 24
Peak memory 196668 kb
Host smart-755b4081-4e36-4195-81e7-f30cb89ae8ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151576650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.4151576650
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.4215021145
Short name T585
Test name
Test status
Simulation time 112069892 ps
CPU time 2.61 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:50 PM PDT 24
Peak memory 198756 kb
Host smart-4030e157-8d4b-4666-9ea2-ae3ad340f955
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215021145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.4215021145
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3704599179
Short name T408
Test name
Test status
Simulation time 29037958 ps
CPU time 0.82 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:49 PM PDT 24
Peak memory 195968 kb
Host smart-f73ce618-9c04-4ee0-89ac-f7e0438bd292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704599179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3704599179
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1577775890
Short name T515
Test name
Test status
Simulation time 60361204 ps
CPU time 1.2 seconds
Started Jul 17 06:59:44 PM PDT 24
Finished Jul 17 06:59:49 PM PDT 24
Peak memory 196464 kb
Host smart-3e679443-0d74-4273-8c86-52d7e2d69438
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577775890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1577775890
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2497400199
Short name T420
Test name
Test status
Simulation time 35020489255 ps
CPU time 96.38 seconds
Started Jul 17 06:59:38 PM PDT 24
Finished Jul 17 07:01:19 PM PDT 24
Peak memory 198800 kb
Host smart-e4de5416-bee3-42a8-a3cb-defe030d6643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497400199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2497400199
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.4145749838
Short name T126
Test name
Test status
Simulation time 13937662 ps
CPU time 0.57 seconds
Started Jul 17 06:57:18 PM PDT 24
Finished Jul 17 06:57:21 PM PDT 24
Peak memory 194620 kb
Host smart-5b2016cb-4e12-43a6-a959-0c70985109ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145749838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.4145749838
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.360325924
Short name T237
Test name
Test status
Simulation time 20462707 ps
CPU time 0.66 seconds
Started Jul 17 06:57:15 PM PDT 24
Finished Jul 17 06:57:16 PM PDT 24
Peak memory 195452 kb
Host smart-681a44f8-e91e-4848-8d65-6ab29cd96633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360325924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.360325924
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.4000631716
Short name T657
Test name
Test status
Simulation time 1036927363 ps
CPU time 8.9 seconds
Started Jul 17 06:57:15 PM PDT 24
Finished Jul 17 06:57:25 PM PDT 24
Peak memory 198904 kb
Host smart-1141ea62-4b4f-41f0-a555-bb6e9a9c92ca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000631716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.4000631716
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1200208496
Short name T569
Test name
Test status
Simulation time 156387342 ps
CPU time 0.67 seconds
Started Jul 17 06:57:17 PM PDT 24
Finished Jul 17 06:57:19 PM PDT 24
Peak memory 195320 kb
Host smart-d984e4d4-6d86-4b50-9447-2525996079a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200208496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1200208496
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3337559719
Short name T86
Test name
Test status
Simulation time 40907891 ps
CPU time 0.91 seconds
Started Jul 17 06:57:20 PM PDT 24
Finished Jul 17 06:57:22 PM PDT 24
Peak memory 197320 kb
Host smart-c73a263d-a580-44d3-8622-4b1d0c0ddf43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337559719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3337559719
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.691884768
Short name T398
Test name
Test status
Simulation time 40992043 ps
CPU time 1.59 seconds
Started Jul 17 06:57:15 PM PDT 24
Finished Jul 17 06:57:18 PM PDT 24
Peak memory 196932 kb
Host smart-5b13263a-95f3-4f25-b9a3-5d4c3ce112dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691884768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.691884768
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1392687407
Short name T212
Test name
Test status
Simulation time 48702438 ps
CPU time 1.5 seconds
Started Jul 17 06:57:16 PM PDT 24
Finished Jul 17 06:57:18 PM PDT 24
Peak memory 196484 kb
Host smart-31cda5f3-02de-4891-87b9-0e682c2dbb3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392687407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1392687407
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.4076680222
Short name T233
Test name
Test status
Simulation time 113131226 ps
CPU time 1.38 seconds
Started Jul 17 06:57:19 PM PDT 24
Finished Jul 17 06:57:22 PM PDT 24
Peak memory 197712 kb
Host smart-b5c54e66-095e-4281-a514-16de8e563836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076680222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.4076680222
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2559637677
Short name T702
Test name
Test status
Simulation time 437847748 ps
CPU time 1.18 seconds
Started Jul 17 06:57:15 PM PDT 24
Finished Jul 17 06:57:17 PM PDT 24
Peak memory 196560 kb
Host smart-a8c8f448-f4da-4d9c-a916-1988ecbf6c07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559637677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2559637677
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.4139531111
Short name T378
Test name
Test status
Simulation time 999789959 ps
CPU time 6.25 seconds
Started Jul 17 06:57:17 PM PDT 24
Finished Jul 17 06:57:25 PM PDT 24
Peak memory 198604 kb
Host smart-1438549b-e752-48da-ab1a-b9dc0c9ec9ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139531111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.4139531111
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.175614775
Short name T439
Test name
Test status
Simulation time 136840540 ps
CPU time 1.35 seconds
Started Jul 17 06:57:18 PM PDT 24
Finished Jul 17 06:57:20 PM PDT 24
Peak memory 196256 kb
Host smart-b276dcd7-b3b5-4742-8d2b-8c0415878ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175614775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.175614775
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1990076229
Short name T74
Test name
Test status
Simulation time 248987361 ps
CPU time 1.42 seconds
Started Jul 17 06:57:19 PM PDT 24
Finished Jul 17 06:57:22 PM PDT 24
Peak memory 198696 kb
Host smart-79e80b4f-e200-4f24-a92c-2591d6266ba2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990076229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1990076229
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.441850213
Short name T410
Test name
Test status
Simulation time 24917347620 ps
CPU time 147.67 seconds
Started Jul 17 06:57:19 PM PDT 24
Finished Jul 17 06:59:49 PM PDT 24
Peak memory 198828 kb
Host smart-4fb498b3-ed27-45b1-868c-ea97bd6ae468
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441850213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.441850213
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2366986830
Short name T711
Test name
Test status
Simulation time 19960100 ps
CPU time 0.59 seconds
Started Jul 17 06:57:49 PM PDT 24
Finished Jul 17 06:57:51 PM PDT 24
Peak memory 195600 kb
Host smart-8820b4e9-9a22-4e85-9dd9-ec009ed1de86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366986830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2366986830
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2899441519
Short name T256
Test name
Test status
Simulation time 141539752 ps
CPU time 0.96 seconds
Started Jul 17 06:57:18 PM PDT 24
Finished Jul 17 06:57:21 PM PDT 24
Peak memory 197284 kb
Host smart-d26bd63e-5012-4aed-94d0-3c5ae5e695f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899441519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2899441519
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2344611364
Short name T119
Test name
Test status
Simulation time 1863409879 ps
CPU time 26.03 seconds
Started Jul 17 06:57:49 PM PDT 24
Finished Jul 17 06:58:17 PM PDT 24
Peak memory 197148 kb
Host smart-c64d2d34-f5c4-4d9f-bec9-547d272c87df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344611364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2344611364
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1317202615
Short name T650
Test name
Test status
Simulation time 65691989 ps
CPU time 0.96 seconds
Started Jul 17 06:57:53 PM PDT 24
Finished Jul 17 06:57:57 PM PDT 24
Peak memory 197108 kb
Host smart-28b6a691-115e-4750-9817-a172fc939807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317202615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1317202615
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3025883439
Short name T600
Test name
Test status
Simulation time 54809116 ps
CPU time 1.02 seconds
Started Jul 17 06:57:16 PM PDT 24
Finished Jul 17 06:57:19 PM PDT 24
Peak memory 196656 kb
Host smart-6f0fc6f0-4c19-4d6d-be9e-720f7fbe3997
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025883439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3025883439
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3807945892
Short name T411
Test name
Test status
Simulation time 59391253 ps
CPU time 2.33 seconds
Started Jul 17 06:57:16 PM PDT 24
Finished Jul 17 06:57:20 PM PDT 24
Peak memory 198688 kb
Host smart-bbbe29d3-5fca-4c91-b8f6-767e8cc94a4f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807945892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3807945892
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3214375829
Short name T240
Test name
Test status
Simulation time 154796250 ps
CPU time 3.05 seconds
Started Jul 17 06:57:17 PM PDT 24
Finished Jul 17 06:57:21 PM PDT 24
Peak memory 197548 kb
Host smart-d760f466-c39c-4337-a829-86d1ed827f85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214375829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3214375829
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2829252657
Short name T200
Test name
Test status
Simulation time 266569691 ps
CPU time 1.23 seconds
Started Jul 17 06:57:17 PM PDT 24
Finished Jul 17 06:57:20 PM PDT 24
Peak memory 198708 kb
Host smart-91642313-0781-42b6-8911-51ee80b44ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829252657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2829252657
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.891163578
Short name T277
Test name
Test status
Simulation time 136767867 ps
CPU time 0.71 seconds
Started Jul 17 06:57:19 PM PDT 24
Finished Jul 17 06:57:21 PM PDT 24
Peak memory 196024 kb
Host smart-bd82d818-d3c4-4f1d-9e09-21d4bc64b6e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891163578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.891163578
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.579683044
Short name T229
Test name
Test status
Simulation time 885241935 ps
CPU time 7.07 seconds
Started Jul 17 06:57:51 PM PDT 24
Finished Jul 17 06:58:01 PM PDT 24
Peak memory 198684 kb
Host smart-01f351a0-c4a2-428c-a87e-834d1de38ff3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579683044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.579683044
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1028953517
Short name T303
Test name
Test status
Simulation time 70895520 ps
CPU time 1.21 seconds
Started Jul 17 06:57:15 PM PDT 24
Finished Jul 17 06:57:18 PM PDT 24
Peak memory 198644 kb
Host smart-9c2d1a73-b041-49a9-8186-e06d784c3675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028953517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1028953517
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.570921407
Short name T293
Test name
Test status
Simulation time 130106413 ps
CPU time 1.09 seconds
Started Jul 17 06:57:16 PM PDT 24
Finished Jul 17 06:57:19 PM PDT 24
Peak memory 196308 kb
Host smart-2a0aa514-671b-4176-aa6a-d8aa41a631d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570921407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.570921407
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3821056617
Short name T450
Test name
Test status
Simulation time 33602024954 ps
CPU time 221.82 seconds
Started Jul 17 06:57:50 PM PDT 24
Finished Jul 17 07:01:35 PM PDT 24
Peak memory 199008 kb
Host smart-60ad2e8b-4f9d-42a7-929c-2b6d2f5edc5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821056617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3821056617
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3288759009
Short name T35
Test name
Test status
Simulation time 167351379445 ps
CPU time 878.19 seconds
Started Jul 17 06:57:45 PM PDT 24
Finished Jul 17 07:12:25 PM PDT 24
Peak memory 198968 kb
Host smart-40716394-18b4-4da1-9613-2fd58f4881f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3288759009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.3288759009
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.935174398
Short name T148
Test name
Test status
Simulation time 37922618 ps
CPU time 0.94 seconds
Started Jul 17 06:57:53 PM PDT 24
Finished Jul 17 06:57:56 PM PDT 24
Peak memory 197724 kb
Host smart-409f7923-a6a9-474f-b7a4-49d4b1de39cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935174398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.935174398
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2017743065
Short name T197
Test name
Test status
Simulation time 2012426132 ps
CPU time 25.48 seconds
Started Jul 17 06:57:51 PM PDT 24
Finished Jul 17 06:58:19 PM PDT 24
Peak memory 196224 kb
Host smart-f103ffd3-fa68-4c17-81d6-322738537274
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017743065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2017743065
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.426360070
Short name T546
Test name
Test status
Simulation time 46778511 ps
CPU time 0.65 seconds
Started Jul 17 06:57:49 PM PDT 24
Finished Jul 17 06:57:52 PM PDT 24
Peak memory 195196 kb
Host smart-932fb802-0564-4a45-b636-314c6bf9338e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426360070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.426360070
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2949121220
Short name T422
Test name
Test status
Simulation time 34706186 ps
CPU time 0.99 seconds
Started Jul 17 06:57:53 PM PDT 24
Finished Jul 17 06:57:56 PM PDT 24
Peak memory 196724 kb
Host smart-40c5d2c6-ae35-4a73-b832-602342c90247
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949121220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2949121220
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3601154760
Short name T703
Test name
Test status
Simulation time 46362907 ps
CPU time 1.75 seconds
Started Jul 17 06:57:58 PM PDT 24
Finished Jul 17 06:58:04 PM PDT 24
Peak memory 197928 kb
Host smart-5c1e8642-e7ae-4dcb-9dce-0859d864e37b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601154760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3601154760
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2787732104
Short name T402
Test name
Test status
Simulation time 492719610 ps
CPU time 2.52 seconds
Started Jul 17 06:57:54 PM PDT 24
Finished Jul 17 06:57:59 PM PDT 24
Peak memory 197860 kb
Host smart-dff10c64-c716-48f2-afc0-9288f05dcc48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787732104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2787732104
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3110485277
Short name T247
Test name
Test status
Simulation time 123956319 ps
CPU time 1.16 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:58:01 PM PDT 24
Peak memory 197800 kb
Host smart-080be4ed-1f21-4256-94e2-ede51798e638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110485277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3110485277
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3792829210
Short name T330
Test name
Test status
Simulation time 119216059 ps
CPU time 0.95 seconds
Started Jul 17 06:57:52 PM PDT 24
Finished Jul 17 06:57:56 PM PDT 24
Peak memory 198004 kb
Host smart-521a5308-d26e-48c3-a38d-e9af7dd798d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792829210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3792829210
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.560861756
Short name T616
Test name
Test status
Simulation time 398577412 ps
CPU time 1.97 seconds
Started Jul 17 06:57:46 PM PDT 24
Finished Jul 17 06:57:49 PM PDT 24
Peak memory 198680 kb
Host smart-d0ce89e1-75fe-4a11-8b58-807774ce3ca3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560861756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.560861756
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2501133694
Short name T26
Test name
Test status
Simulation time 76079139 ps
CPU time 1.08 seconds
Started Jul 17 06:57:54 PM PDT 24
Finished Jul 17 06:57:58 PM PDT 24
Peak memory 196512 kb
Host smart-589f723d-8df1-46c2-85c7-db42eee7b76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501133694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2501133694
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1019554790
Short name T404
Test name
Test status
Simulation time 283749729 ps
CPU time 1.04 seconds
Started Jul 17 06:57:53 PM PDT 24
Finished Jul 17 06:57:56 PM PDT 24
Peak memory 196264 kb
Host smart-58873e37-f609-4dd0-b411-d535a2e80e72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019554790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1019554790
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2107438428
Short name T216
Test name
Test status
Simulation time 8804192200 ps
CPU time 124.8 seconds
Started Jul 17 06:57:57 PM PDT 24
Finished Jul 17 07:00:05 PM PDT 24
Peak memory 198788 kb
Host smart-cfbafe1f-7f59-42a1-9bee-1e1ca45553fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107438428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2107438428
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.3507939174
Short name T551
Test name
Test status
Simulation time 138400992211 ps
CPU time 745.07 seconds
Started Jul 17 06:57:49 PM PDT 24
Finished Jul 17 07:10:17 PM PDT 24
Peak memory 199128 kb
Host smart-8a1c8878-2a30-4167-97ad-71b8801bff3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3507939174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.3507939174
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3340898628
Short name T332
Test name
Test status
Simulation time 25435356 ps
CPU time 0.6 seconds
Started Jul 17 06:57:49 PM PDT 24
Finished Jul 17 06:57:51 PM PDT 24
Peak memory 195320 kb
Host smart-f24bdb97-778b-4aae-8ea7-9898e3cd7b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340898628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3340898628
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3980571695
Short name T523
Test name
Test status
Simulation time 95897875 ps
CPU time 0.91 seconds
Started Jul 17 06:57:54 PM PDT 24
Finished Jul 17 06:57:57 PM PDT 24
Peak memory 196984 kb
Host smart-4aaeccdc-5f76-4a7e-8823-5230db4c96c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980571695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3980571695
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2103310986
Short name T22
Test name
Test status
Simulation time 1406264402 ps
CPU time 12.66 seconds
Started Jul 17 06:57:48 PM PDT 24
Finished Jul 17 06:58:02 PM PDT 24
Peak memory 197444 kb
Host smart-8c7632ab-a68f-43a2-8f62-7b9e6ad7d5b6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103310986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2103310986
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2893489122
Short name T421
Test name
Test status
Simulation time 35033067 ps
CPU time 0.82 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:58:00 PM PDT 24
Peak memory 196304 kb
Host smart-c4adda9b-1e08-48d3-bd06-c8e9b2ada560
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893489122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2893489122
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2380592
Short name T647
Test name
Test status
Simulation time 61448968 ps
CPU time 2.36 seconds
Started Jul 17 06:57:49 PM PDT 24
Finished Jul 17 06:57:54 PM PDT 24
Peak memory 198928 kb
Host smart-be6a2fd8-9520-423a-824b-ec33eb2d5862
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_intr_with_filter_rand_intr_event.2380592
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2182095803
Short name T500
Test name
Test status
Simulation time 83350381 ps
CPU time 2.53 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:58:01 PM PDT 24
Peak memory 196488 kb
Host smart-1b21ce0f-a890-414c-9fc6-c4d7e10beff5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182095803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2182095803
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3062066922
Short name T199
Test name
Test status
Simulation time 19661318 ps
CPU time 0.75 seconds
Started Jul 17 06:57:50 PM PDT 24
Finished Jul 17 06:57:53 PM PDT 24
Peak memory 196184 kb
Host smart-27502565-2020-431c-a4a4-394caba5e414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062066922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3062066922
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2692046742
Short name T602
Test name
Test status
Simulation time 100871755 ps
CPU time 0.77 seconds
Started Jul 17 06:57:57 PM PDT 24
Finished Jul 17 06:58:01 PM PDT 24
Peak memory 195616 kb
Host smart-2f2b4ce9-f740-4511-b2b6-693bfcb7b60f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692046742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2692046742
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.767438268
Short name T122
Test name
Test status
Simulation time 463451636 ps
CPU time 5.55 seconds
Started Jul 17 06:57:54 PM PDT 24
Finished Jul 17 06:58:01 PM PDT 24
Peak memory 198636 kb
Host smart-d06f26e8-477c-4876-8441-3d7c1741958b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767438268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.767438268
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.507881708
Short name T691
Test name
Test status
Simulation time 249236662 ps
CPU time 1.16 seconds
Started Jul 17 06:57:49 PM PDT 24
Finished Jul 17 06:57:53 PM PDT 24
Peak memory 196492 kb
Host smart-eefabf02-8a8c-4d18-a9e6-94e8ec93cd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507881708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.507881708
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.443309536
Short name T371
Test name
Test status
Simulation time 60855707 ps
CPU time 1.14 seconds
Started Jul 17 06:57:52 PM PDT 24
Finished Jul 17 06:57:55 PM PDT 24
Peak memory 197136 kb
Host smart-955dcf03-5872-4d51-9291-2326c2f84518
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443309536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.443309536
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3868516316
Short name T424
Test name
Test status
Simulation time 15192773675 ps
CPU time 151.27 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 07:00:30 PM PDT 24
Peak memory 198568 kb
Host smart-08ef5847-de8f-4a5e-8be4-97394a3b4f10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868516316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3868516316
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2250667123
Short name T475
Test name
Test status
Simulation time 21279114 ps
CPU time 0.54 seconds
Started Jul 17 06:57:49 PM PDT 24
Finished Jul 17 06:57:52 PM PDT 24
Peak memory 194676 kb
Host smart-29311dd6-8797-44c0-987a-4f6a76387152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250667123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2250667123
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.884183476
Short name T298
Test name
Test status
Simulation time 525262645 ps
CPU time 0.93 seconds
Started Jul 17 06:57:52 PM PDT 24
Finished Jul 17 06:57:56 PM PDT 24
Peak memory 197320 kb
Host smart-4432a6e9-c6d5-4271-83af-f4c032eef0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884183476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.884183476
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3535783047
Short name T296
Test name
Test status
Simulation time 778234942 ps
CPU time 24.37 seconds
Started Jul 17 06:57:50 PM PDT 24
Finished Jul 17 06:58:17 PM PDT 24
Peak memory 198652 kb
Host smart-39a6a42b-6759-41c4-b686-639182f09a6d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535783047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3535783047
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2894165048
Short name T541
Test name
Test status
Simulation time 49869217 ps
CPU time 0.79 seconds
Started Jul 17 06:57:48 PM PDT 24
Finished Jul 17 06:57:51 PM PDT 24
Peak memory 197348 kb
Host smart-338ff7cc-6b42-4f19-990a-b0a4cd61535c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894165048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2894165048
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3508065957
Short name T230
Test name
Test status
Simulation time 71018928 ps
CPU time 1.15 seconds
Started Jul 17 06:57:49 PM PDT 24
Finished Jul 17 06:57:52 PM PDT 24
Peak memory 196848 kb
Host smart-e789a938-82a7-4d9c-9e4e-8077dd6d162c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508065957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3508065957
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.366691386
Short name T660
Test name
Test status
Simulation time 266337909 ps
CPU time 2.55 seconds
Started Jul 17 06:57:50 PM PDT 24
Finished Jul 17 06:57:55 PM PDT 24
Peak memory 197016 kb
Host smart-36f533e7-272d-45a3-a5cb-0ea527cb83ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366691386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.366691386
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.293338268
Short name T540
Test name
Test status
Simulation time 372493084 ps
CPU time 2.73 seconds
Started Jul 17 06:57:48 PM PDT 24
Finished Jul 17 06:57:52 PM PDT 24
Peak memory 196524 kb
Host smart-7c382b7f-3342-4527-bbe7-a5aa7dcf8af7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293338268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.293338268
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2603467936
Short name T198
Test name
Test status
Simulation time 49584469 ps
CPU time 1.02 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 06:57:59 PM PDT 24
Peak memory 196560 kb
Host smart-e42776eb-1172-4560-a157-7657a4712382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603467936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2603467936
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2612189580
Short name T25
Test name
Test status
Simulation time 34847783 ps
CPU time 1.21 seconds
Started Jul 17 06:57:48 PM PDT 24
Finished Jul 17 06:57:50 PM PDT 24
Peak memory 197696 kb
Host smart-514b44e4-18c4-4f29-a232-71e8fcde7729
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612189580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2612189580
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1206691372
Short name T666
Test name
Test status
Simulation time 819873624 ps
CPU time 4.91 seconds
Started Jul 17 06:57:55 PM PDT 24
Finished Jul 17 06:58:03 PM PDT 24
Peak memory 198684 kb
Host smart-05fc4f5f-8a87-4fd7-b1f3-b96b49ab9312
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206691372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1206691372
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3843846288
Short name T192
Test name
Test status
Simulation time 84974946 ps
CPU time 1.28 seconds
Started Jul 17 06:57:50 PM PDT 24
Finished Jul 17 06:57:54 PM PDT 24
Peak memory 196520 kb
Host smart-e2a9b9be-2c4e-443f-ad08-b6309565a7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843846288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3843846288
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3019078880
Short name T167
Test name
Test status
Simulation time 73857979 ps
CPU time 1.31 seconds
Started Jul 17 06:57:53 PM PDT 24
Finished Jul 17 06:57:56 PM PDT 24
Peak memory 198716 kb
Host smart-92491265-643a-43ce-af0c-63c7e669b2a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019078880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3019078880
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.4218224279
Short name T299
Test name
Test status
Simulation time 19526207247 ps
CPU time 23.3 seconds
Started Jul 17 06:57:54 PM PDT 24
Finished Jul 17 06:58:19 PM PDT 24
Peak memory 198812 kb
Host smart-c1f45bc2-f780-48cc-bbce-89f113456816
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218224279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.4218224279
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.4222522297
Short name T707
Test name
Test status
Simulation time 197465155909 ps
CPU time 1007.52 seconds
Started Jul 17 06:57:56 PM PDT 24
Finished Jul 17 07:14:47 PM PDT 24
Peak memory 198940 kb
Host smart-40f2b07d-2ad0-4a5a-80ae-4cbb5f8aa276
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4222522297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.4222522297
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.799222464
Short name T867
Test name
Test status
Simulation time 223282818 ps
CPU time 1.1 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:26 PM PDT 24
Peak memory 196232 kb
Host smart-cda0128b-656f-43ab-a7e4-4b7fa7d62606
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=799222464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.799222464
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3125790098
Short name T896
Test name
Test status
Simulation time 69942617 ps
CPU time 0.82 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:25 PM PDT 24
Peak memory 196620 kb
Host smart-e67f7e96-7222-4b14-9b75-ac268ecf315a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125790098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3125790098
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.193394138
Short name T844
Test name
Test status
Simulation time 1063717412 ps
CPU time 1.1 seconds
Started Jul 17 06:56:24 PM PDT 24
Finished Jul 17 06:56:33 PM PDT 24
Peak memory 198600 kb
Host smart-187f6d80-2759-4cd3-a0e2-d3dbab77bbf9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=193394138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.193394138
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2148545951
Short name T861
Test name
Test status
Simulation time 202452132 ps
CPU time 1.11 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 196352 kb
Host smart-ea8487c9-5e21-4c64-836b-e1447dbb686a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148545951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2148545951
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3071176280
Short name T897
Test name
Test status
Simulation time 1084477574 ps
CPU time 1.13 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:26 PM PDT 24
Peak memory 196908 kb
Host smart-50ca6789-a586-4f7d-af3b-7054a1e119c1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3071176280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3071176280
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2036475863
Short name T932
Test name
Test status
Simulation time 48016742 ps
CPU time 1.2 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:31 PM PDT 24
Peak memory 197208 kb
Host smart-e89f7654-d64d-46f1-a3de-537bf4c24911
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036475863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2036475863
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.539204721
Short name T934
Test name
Test status
Simulation time 68079506 ps
CPU time 1.2 seconds
Started Jul 17 06:56:20 PM PDT 24
Finished Jul 17 06:56:25 PM PDT 24
Peak memory 196872 kb
Host smart-f5065474-eedb-4d1c-846c-fb072781907e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=539204721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.539204721
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4158286269
Short name T882
Test name
Test status
Simulation time 69920393 ps
CPU time 1.09 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:26 PM PDT 24
Peak memory 198484 kb
Host smart-0e95c282-43c5-45d0-aba7-67a39855bf89
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158286269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4158286269
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.138431874
Short name T877
Test name
Test status
Simulation time 443590800 ps
CPU time 0.97 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 196872 kb
Host smart-9948e797-cfa8-4b22-a13c-c051c26c9c93
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=138431874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.138431874
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4026037098
Short name T901
Test name
Test status
Simulation time 123369726 ps
CPU time 0.83 seconds
Started Jul 17 06:56:28 PM PDT 24
Finished Jul 17 06:56:36 PM PDT 24
Peak memory 195816 kb
Host smart-5dc640c3-1544-4336-9973-e10de98900ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026037098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4026037098
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3428191804
Short name T942
Test name
Test status
Simulation time 94521916 ps
CPU time 1.06 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:28 PM PDT 24
Peak memory 196800 kb
Host smart-d86e10da-c971-4d9e-9935-eb44b728fc82
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3428191804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3428191804
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1040776292
Short name T888
Test name
Test status
Simulation time 164622171 ps
CPU time 1.41 seconds
Started Jul 17 06:56:28 PM PDT 24
Finished Jul 17 06:56:37 PM PDT 24
Peak memory 197164 kb
Host smart-cb68e71e-e98f-4fbd-920e-e8e1c1704fef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040776292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1040776292
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3088100074
Short name T893
Test name
Test status
Simulation time 43867673 ps
CPU time 0.96 seconds
Started Jul 17 06:56:27 PM PDT 24
Finished Jul 17 06:56:36 PM PDT 24
Peak memory 196940 kb
Host smart-d5d75130-5976-449f-a3ae-92e7bda924f1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3088100074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3088100074
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1935563610
Short name T865
Test name
Test status
Simulation time 66076063 ps
CPU time 1.15 seconds
Started Jul 17 06:56:25 PM PDT 24
Finished Jul 17 06:56:34 PM PDT 24
Peak memory 196828 kb
Host smart-3280312f-9c6b-4228-9cf2-a187b828e3da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935563610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1935563610
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.555262888
Short name T851
Test name
Test status
Simulation time 150768189 ps
CPU time 1.18 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:28 PM PDT 24
Peak memory 196556 kb
Host smart-aef882ec-a5cb-439c-be24-22d55cbc81e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=555262888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.555262888
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4224100014
Short name T849
Test name
Test status
Simulation time 317962557 ps
CPU time 1.43 seconds
Started Jul 17 06:56:24 PM PDT 24
Finished Jul 17 06:56:33 PM PDT 24
Peak memory 196988 kb
Host smart-b9060c31-686a-4eee-920d-8f4abb085a82
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224100014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4224100014
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2234454448
Short name T872
Test name
Test status
Simulation time 211768059 ps
CPU time 1.2 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:28 PM PDT 24
Peak memory 196116 kb
Host smart-78e7bc16-c4f4-45d7-8944-5dc7aa139cdc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2234454448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2234454448
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2727932557
Short name T924
Test name
Test status
Simulation time 127588855 ps
CPU time 1.26 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 198432 kb
Host smart-c48acf62-77ce-432b-a00f-00b1feea9988
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727932557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2727932557
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.890754864
Short name T933
Test name
Test status
Simulation time 70730582 ps
CPU time 0.94 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:28 PM PDT 24
Peak memory 197024 kb
Host smart-cba7cbde-5555-4f11-a4da-8fc220ea8e03
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=890754864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.890754864
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2517679018
Short name T939
Test name
Test status
Simulation time 83113796 ps
CPU time 1.34 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:26 PM PDT 24
Peak memory 197356 kb
Host smart-a0388a5e-3d27-4c7f-8795-1de48c24095f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517679018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2517679018
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.972097743
Short name T915
Test name
Test status
Simulation time 117222531 ps
CPU time 1.01 seconds
Started Jul 17 06:56:27 PM PDT 24
Finished Jul 17 06:56:35 PM PDT 24
Peak memory 196328 kb
Host smart-17ccef92-6a3c-4050-932f-e11bc5ae96f1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=972097743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.972097743
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2518654743
Short name T904
Test name
Test status
Simulation time 78700424 ps
CPU time 0.99 seconds
Started Jul 17 06:56:20 PM PDT 24
Finished Jul 17 06:56:24 PM PDT 24
Peak memory 197040 kb
Host smart-dcc943b4-b65e-48b2-91e7-4f6253a81993
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518654743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2518654743
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3173003358
Short name T860
Test name
Test status
Simulation time 337248466 ps
CPU time 1.45 seconds
Started Jul 17 06:56:24 PM PDT 24
Finished Jul 17 06:56:33 PM PDT 24
Peak memory 198652 kb
Host smart-00a32292-76e2-41e3-9c05-f251c9cb5082
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3173003358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3173003358
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1375926239
Short name T853
Test name
Test status
Simulation time 42756729 ps
CPU time 1.14 seconds
Started Jul 17 06:56:28 PM PDT 24
Finished Jul 17 06:56:37 PM PDT 24
Peak memory 198376 kb
Host smart-9bf6e526-e509-4c80-ba79-5e4de4d78891
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375926239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1375926239
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3874013291
Short name T859
Test name
Test status
Simulation time 104615036 ps
CPU time 1.09 seconds
Started Jul 17 06:56:27 PM PDT 24
Finished Jul 17 06:56:35 PM PDT 24
Peak memory 197096 kb
Host smart-774f3154-02e5-42bf-9462-74be9dcc1bde
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3874013291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3874013291
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1694595417
Short name T937
Test name
Test status
Simulation time 31015423 ps
CPU time 0.76 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:29 PM PDT 24
Peak memory 196516 kb
Host smart-382a89a4-b87e-4817-be1a-5e285c9c7985
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694595417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1694595417
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1911729659
Short name T912
Test name
Test status
Simulation time 379437551 ps
CPU time 0.85 seconds
Started Jul 17 06:56:24 PM PDT 24
Finished Jul 17 06:56:32 PM PDT 24
Peak memory 195852 kb
Host smart-d3214317-841c-4c00-b5ef-0bb7bd5de3df
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1911729659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1911729659
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2506528951
Short name T878
Test name
Test status
Simulation time 74382191 ps
CPU time 1.27 seconds
Started Jul 17 06:56:26 PM PDT 24
Finished Jul 17 06:56:35 PM PDT 24
Peak memory 197036 kb
Host smart-01dd9628-b4bd-4f7f-b081-4df8bcde62b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506528951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2506528951
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4051905927
Short name T914
Test name
Test status
Simulation time 54394436 ps
CPU time 1.36 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:32 PM PDT 24
Peak memory 198412 kb
Host smart-884b28d7-c051-409f-a4fd-748a7743557b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4051905927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.4051905927
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1827894089
Short name T943
Test name
Test status
Simulation time 145368838 ps
CPU time 0.83 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 195732 kb
Host smart-35a6c38a-3d02-49fc-abc6-b30a757a856f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827894089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1827894089
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3149262509
Short name T941
Test name
Test status
Simulation time 103705826 ps
CPU time 0.87 seconds
Started Jul 17 06:56:24 PM PDT 24
Finished Jul 17 06:56:32 PM PDT 24
Peak memory 197752 kb
Host smart-67e7c770-ed44-418b-bc56-c0509cbf49f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3149262509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3149262509
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1737585211
Short name T875
Test name
Test status
Simulation time 44044488 ps
CPU time 1.18 seconds
Started Jul 17 06:56:25 PM PDT 24
Finished Jul 17 06:56:34 PM PDT 24
Peak memory 197128 kb
Host smart-a9db3ca3-e5d6-4333-b4e6-23272eae9839
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737585211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1737585211
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2044347648
Short name T929
Test name
Test status
Simulation time 241899069 ps
CPU time 1.25 seconds
Started Jul 17 06:56:25 PM PDT 24
Finished Jul 17 06:56:33 PM PDT 24
Peak memory 198280 kb
Host smart-2de1a7f9-ed7a-48bc-828e-587986cf30ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2044347648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2044347648
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3305650694
Short name T863
Test name
Test status
Simulation time 60540967 ps
CPU time 1.1 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:31 PM PDT 24
Peak memory 196804 kb
Host smart-afa71f85-cea4-4ad1-9e66-6f20a26fc9b9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305650694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3305650694
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.180169040
Short name T854
Test name
Test status
Simulation time 52137550 ps
CPU time 1.35 seconds
Started Jul 17 06:56:26 PM PDT 24
Finished Jul 17 06:56:34 PM PDT 24
Peak memory 198388 kb
Host smart-6bb1314a-8217-4ed5-9581-e5a72a975a97
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=180169040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.180169040
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2595091641
Short name T920
Test name
Test status
Simulation time 58563122 ps
CPU time 0.91 seconds
Started Jul 17 06:56:26 PM PDT 24
Finished Jul 17 06:56:34 PM PDT 24
Peak memory 197748 kb
Host smart-4e167e2b-bb47-4cd8-933d-95c6f59f2470
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595091641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2595091641
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3773423044
Short name T899
Test name
Test status
Simulation time 145952709 ps
CPU time 1.11 seconds
Started Jul 17 06:56:29 PM PDT 24
Finished Jul 17 06:56:37 PM PDT 24
Peak memory 197900 kb
Host smart-81fa4d6f-f85b-4b28-84f0-e1a4110e9880
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3773423044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3773423044
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.988294003
Short name T885
Test name
Test status
Simulation time 127220333 ps
CPU time 1.34 seconds
Started Jul 17 06:56:28 PM PDT 24
Finished Jul 17 06:56:36 PM PDT 24
Peak memory 196812 kb
Host smart-27d14ce0-c1a1-4e31-a876-21894b68c169
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988294003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.988294003
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1363975753
Short name T905
Test name
Test status
Simulation time 296050854 ps
CPU time 1 seconds
Started Jul 17 06:56:28 PM PDT 24
Finished Jul 17 06:56:36 PM PDT 24
Peak memory 197052 kb
Host smart-52c5f029-3874-4939-8736-3510a7d6303f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1363975753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1363975753
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2087651026
Short name T894
Test name
Test status
Simulation time 58096082 ps
CPU time 1.12 seconds
Started Jul 17 06:56:32 PM PDT 24
Finished Jul 17 06:56:38 PM PDT 24
Peak memory 198344 kb
Host smart-83efe4db-78f5-43b5-aa53-521c935eec6c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087651026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2087651026
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2271507173
Short name T910
Test name
Test status
Simulation time 309095364 ps
CPU time 1.31 seconds
Started Jul 17 06:56:26 PM PDT 24
Finished Jul 17 06:56:35 PM PDT 24
Peak memory 197332 kb
Host smart-bc8ac9e9-a4f3-4bc6-96b8-90426a07cd3b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2271507173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2271507173
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4024823857
Short name T881
Test name
Test status
Simulation time 87119063 ps
CPU time 1.34 seconds
Started Jul 17 06:56:32 PM PDT 24
Finished Jul 17 06:56:39 PM PDT 24
Peak memory 197256 kb
Host smart-72caa2df-be09-4446-afef-d01d63262550
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024823857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4024823857
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2060635187
Short name T847
Test name
Test status
Simulation time 32856438 ps
CPU time 0.92 seconds
Started Jul 17 06:56:28 PM PDT 24
Finished Jul 17 06:56:36 PM PDT 24
Peak memory 196868 kb
Host smart-7f5a6a5d-0967-43ee-a748-b35257e4c7aa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2060635187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2060635187
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2684426799
Short name T868
Test name
Test status
Simulation time 55141846 ps
CPU time 1.02 seconds
Started Jul 17 06:56:29 PM PDT 24
Finished Jul 17 06:56:37 PM PDT 24
Peak memory 196876 kb
Host smart-b438af3e-b512-44fe-987a-607b5c086200
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684426799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2684426799
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.225057356
Short name T869
Test name
Test status
Simulation time 65042149 ps
CPU time 1.1 seconds
Started Jul 17 06:56:29 PM PDT 24
Finished Jul 17 06:56:37 PM PDT 24
Peak memory 197100 kb
Host smart-fb3897a1-384f-4bac-9f5d-452e841af865
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=225057356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.225057356
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4235690272
Short name T873
Test name
Test status
Simulation time 37822948 ps
CPU time 0.8 seconds
Started Jul 17 06:56:27 PM PDT 24
Finished Jul 17 06:56:36 PM PDT 24
Peak memory 196492 kb
Host smart-f0786d24-2c9e-4d6f-9beb-ae4414430d67
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235690272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4235690272
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1589144984
Short name T886
Test name
Test status
Simulation time 60939521 ps
CPU time 1.29 seconds
Started Jul 17 06:56:25 PM PDT 24
Finished Jul 17 06:56:34 PM PDT 24
Peak memory 198352 kb
Host smart-6ff811b3-c5d6-47cb-ba85-f0aa0759985b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1589144984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1589144984
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3979699646
Short name T887
Test name
Test status
Simulation time 75975472 ps
CPU time 1.28 seconds
Started Jul 17 06:56:25 PM PDT 24
Finished Jul 17 06:56:33 PM PDT 24
Peak memory 196860 kb
Host smart-c48288c8-d403-4238-8a8e-614752fb75c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979699646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3979699646
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1901575719
Short name T870
Test name
Test status
Simulation time 60428511 ps
CPU time 1 seconds
Started Jul 17 06:56:27 PM PDT 24
Finished Jul 17 06:56:35 PM PDT 24
Peak memory 196228 kb
Host smart-5835502d-2961-4bd3-bfd2-0424c3278357
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1901575719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1901575719
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.89522740
Short name T906
Test name
Test status
Simulation time 61935339 ps
CPU time 0.97 seconds
Started Jul 17 06:56:37 PM PDT 24
Finished Jul 17 06:56:41 PM PDT 24
Peak memory 196968 kb
Host smart-f1f00bba-f6f1-4795-b8ff-b02603117d99
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89522740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.89522740
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3365576315
Short name T913
Test name
Test status
Simulation time 288801210 ps
CPU time 0.97 seconds
Started Jul 17 06:56:27 PM PDT 24
Finished Jul 17 06:56:35 PM PDT 24
Peak memory 196796 kb
Host smart-ab78f26b-7259-42ed-acde-568c14f5a872
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3365576315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3365576315
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4064324640
Short name T926
Test name
Test status
Simulation time 107389215 ps
CPU time 1.01 seconds
Started Jul 17 06:56:26 PM PDT 24
Finished Jul 17 06:56:35 PM PDT 24
Peak memory 196940 kb
Host smart-3e3cd908-7ce0-4a8f-8bf7-e828d13d8267
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064324640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4064324640
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2977995949
Short name T918
Test name
Test status
Simulation time 179525983 ps
CPU time 1.23 seconds
Started Jul 17 06:56:26 PM PDT 24
Finished Jul 17 06:56:35 PM PDT 24
Peak memory 198464 kb
Host smart-f54c6bca-fd0a-4403-b380-fdd5c5163dfc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2977995949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2977995949
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1213704913
Short name T928
Test name
Test status
Simulation time 43514585 ps
CPU time 1.19 seconds
Started Jul 17 06:56:28 PM PDT 24
Finished Jul 17 06:56:36 PM PDT 24
Peak memory 196392 kb
Host smart-53cd70f4-6e7b-45ab-b1ec-bc5bf5f67b0f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213704913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1213704913
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3986893317
Short name T922
Test name
Test status
Simulation time 31833820 ps
CPU time 0.8 seconds
Started Jul 17 06:56:30 PM PDT 24
Finished Jul 17 06:56:37 PM PDT 24
Peak memory 195824 kb
Host smart-f78263e0-a036-4b63-9623-8ada14aaf88d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3986893317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3986893317
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1077219473
Short name T889
Test name
Test status
Simulation time 303811269 ps
CPU time 1.32 seconds
Started Jul 17 06:56:28 PM PDT 24
Finished Jul 17 06:56:37 PM PDT 24
Peak memory 197080 kb
Host smart-7d435e81-54f4-4d5c-8c79-ed46f195d889
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077219473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1077219473
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3446004231
Short name T883
Test name
Test status
Simulation time 367434614 ps
CPU time 1.33 seconds
Started Jul 17 06:56:26 PM PDT 24
Finished Jul 17 06:56:35 PM PDT 24
Peak memory 197312 kb
Host smart-be706c7a-3622-49d2-9e07-3c1688032dca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3446004231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3446004231
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1702727098
Short name T864
Test name
Test status
Simulation time 150875033 ps
CPU time 0.86 seconds
Started Jul 17 06:56:26 PM PDT 24
Finished Jul 17 06:56:34 PM PDT 24
Peak memory 196540 kb
Host smart-4b6fc824-f2ac-4a61-b2d6-b5d6971135ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702727098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1702727098
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3730148712
Short name T891
Test name
Test status
Simulation time 98028122 ps
CPU time 1.09 seconds
Started Jul 17 06:56:28 PM PDT 24
Finished Jul 17 06:56:36 PM PDT 24
Peak memory 198424 kb
Host smart-299f80e9-04bc-460d-8a89-2f9318e6fc10
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3730148712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3730148712
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3091919727
Short name T908
Test name
Test status
Simulation time 26429370 ps
CPU time 0.86 seconds
Started Jul 17 06:56:26 PM PDT 24
Finished Jul 17 06:56:34 PM PDT 24
Peak memory 195896 kb
Host smart-ed72bc0a-c5a8-474a-bbc4-f9cc47f4c267
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091919727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3091919727
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1776033508
Short name T895
Test name
Test status
Simulation time 117788480 ps
CPU time 1.01 seconds
Started Jul 17 06:56:26 PM PDT 24
Finished Jul 17 06:56:35 PM PDT 24
Peak memory 196176 kb
Host smart-c89060f1-9594-4cc9-b0f0-3f039b0b67f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1776033508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1776033508
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3998238936
Short name T923
Test name
Test status
Simulation time 104081456 ps
CPU time 0.93 seconds
Started Jul 17 06:56:26 PM PDT 24
Finished Jul 17 06:56:34 PM PDT 24
Peak memory 197760 kb
Host smart-0d0dce5e-ed4e-4ccf-ab77-2b084cbaad66
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998238936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3998238936
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.622082435
Short name T900
Test name
Test status
Simulation time 50912779 ps
CPU time 1.35 seconds
Started Jul 17 06:56:29 PM PDT 24
Finished Jul 17 06:56:37 PM PDT 24
Peak memory 197308 kb
Host smart-0a862c33-ea1c-442d-ba50-5fdfe46dd0c8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=622082435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.622082435
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1046288750
Short name T846
Test name
Test status
Simulation time 44452597 ps
CPU time 1.24 seconds
Started Jul 17 06:56:29 PM PDT 24
Finished Jul 17 06:56:37 PM PDT 24
Peak memory 196932 kb
Host smart-3b08214c-f8d2-4883-92f5-c8097165bbae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046288750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1046288750
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.792569836
Short name T862
Test name
Test status
Simulation time 130309066 ps
CPU time 0.85 seconds
Started Jul 17 06:56:27 PM PDT 24
Finished Jul 17 06:56:36 PM PDT 24
Peak memory 195868 kb
Host smart-2b417242-e608-4ff7-91fe-367f372b2d62
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=792569836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.792569836
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4144250929
Short name T866
Test name
Test status
Simulation time 51026718 ps
CPU time 0.95 seconds
Started Jul 17 06:56:27 PM PDT 24
Finished Jul 17 06:56:35 PM PDT 24
Peak memory 196588 kb
Host smart-bd709187-aa60-4f92-aaee-07df078292f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144250929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4144250929
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2432584577
Short name T938
Test name
Test status
Simulation time 120958766 ps
CPU time 1.29 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:26 PM PDT 24
Peak memory 196896 kb
Host smart-07b33f9b-dc9f-4e27-8f7d-32348d7fe3b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2432584577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2432584577
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1067759795
Short name T930
Test name
Test status
Simulation time 38009553 ps
CPU time 0.87 seconds
Started Jul 17 06:56:29 PM PDT 24
Finished Jul 17 06:56:37 PM PDT 24
Peak memory 195800 kb
Host smart-4a3f077b-7b63-4b0d-9cf9-8a5deaed0b0b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067759795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1067759795
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2324491177
Short name T911
Test name
Test status
Simulation time 30865454 ps
CPU time 0.97 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:27 PM PDT 24
Peak memory 196316 kb
Host smart-4f73fa78-12a7-441f-8430-53e5d48e1648
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2324491177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2324491177
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1086285938
Short name T927
Test name
Test status
Simulation time 127570101 ps
CPU time 1.12 seconds
Started Jul 17 06:56:24 PM PDT 24
Finished Jul 17 06:56:33 PM PDT 24
Peak memory 196416 kb
Host smart-60fca55c-919b-40ed-b6c6-d144e2a0bb34
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086285938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1086285938
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.743097944
Short name T848
Test name
Test status
Simulation time 78548896 ps
CPU time 1.45 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 197120 kb
Host smart-1d3431d5-dcb9-4396-85d2-c52ee0259347
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=743097944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.743097944
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3725224046
Short name T876
Test name
Test status
Simulation time 57808631 ps
CPU time 1.1 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 198432 kb
Host smart-41976132-2fbd-45f0-ae25-e5c5a2969607
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725224046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3725224046
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3438966595
Short name T871
Test name
Test status
Simulation time 76323361 ps
CPU time 1.26 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:31 PM PDT 24
Peak memory 198420 kb
Host smart-09709b97-3dd4-4ade-bf47-90d72cd70e28
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3438966595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3438966595
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3118522254
Short name T925
Test name
Test status
Simulation time 83724992 ps
CPU time 0.73 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:28 PM PDT 24
Peak memory 194784 kb
Host smart-ee16b3e9-a26b-40cc-82a7-a623ad5b0f17
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118522254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3118522254
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1340585216
Short name T890
Test name
Test status
Simulation time 320455618 ps
CPU time 1.44 seconds
Started Jul 17 06:56:24 PM PDT 24
Finished Jul 17 06:56:33 PM PDT 24
Peak memory 197508 kb
Host smart-ecd54717-1c84-4793-9436-a7945488dbf5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1340585216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1340585216
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2537381426
Short name T855
Test name
Test status
Simulation time 153392871 ps
CPU time 0.95 seconds
Started Jul 17 06:56:25 PM PDT 24
Finished Jul 17 06:56:34 PM PDT 24
Peak memory 197016 kb
Host smart-0e565a5e-7d11-4c25-a007-f051fbddac34
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537381426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2537381426
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1393807808
Short name T852
Test name
Test status
Simulation time 58354948 ps
CPU time 1.13 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 196944 kb
Host smart-5ecd119e-ef91-4acb-89f3-244072e6f845
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1393807808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1393807808
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1569786574
Short name T903
Test name
Test status
Simulation time 36761592 ps
CPU time 0.85 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 196620 kb
Host smart-75441b3a-d796-482a-ae08-9a9bac3ba972
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569786574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1569786574
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2057970053
Short name T931
Test name
Test status
Simulation time 32637279 ps
CPU time 0.84 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 195488 kb
Host smart-d8a86312-d920-4ded-a4bb-8d8967fc8583
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2057970053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2057970053
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3342287682
Short name T902
Test name
Test status
Simulation time 511335211 ps
CPU time 1.24 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:31 PM PDT 24
Peak memory 197432 kb
Host smart-bc6c7e1a-c3e9-4fa8-b2cf-bbaca5accd2b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342287682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3342287682
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1208613092
Short name T850
Test name
Test status
Simulation time 241392554 ps
CPU time 0.97 seconds
Started Jul 17 06:56:25 PM PDT 24
Finished Jul 17 06:56:33 PM PDT 24
Peak memory 197032 kb
Host smart-4f0e05f3-a586-4631-a628-f22d314d31f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1208613092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1208613092
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3459380593
Short name T916
Test name
Test status
Simulation time 108165974 ps
CPU time 1.02 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:29 PM PDT 24
Peak memory 197000 kb
Host smart-188efa58-1522-4e18-a810-1c356aff62c0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459380593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3459380593
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4285604486
Short name T856
Test name
Test status
Simulation time 39147854 ps
CPU time 0.99 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 197204 kb
Host smart-64b1c474-bcc3-4e2c-b933-6cf9c15d6fc5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4285604486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.4285604486
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2388353407
Short name T921
Test name
Test status
Simulation time 118319314 ps
CPU time 1.01 seconds
Started Jul 17 06:56:25 PM PDT 24
Finished Jul 17 06:56:33 PM PDT 24
Peak memory 198080 kb
Host smart-d3a68c12-7460-43bf-8bb3-2a98fd78fcc9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388353407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2388353407
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2335734489
Short name T935
Test name
Test status
Simulation time 515048228 ps
CPU time 0.91 seconds
Started Jul 17 06:56:24 PM PDT 24
Finished Jul 17 06:56:32 PM PDT 24
Peak memory 196004 kb
Host smart-360c4ead-8d37-40f1-852f-ac4bd81a5836
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2335734489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2335734489
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4128613268
Short name T845
Test name
Test status
Simulation time 74506188 ps
CPU time 1.08 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:31 PM PDT 24
Peak memory 197168 kb
Host smart-0841b2e4-17ef-46e7-aa5c-8f3f6392893a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128613268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4128613268
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2577765051
Short name T909
Test name
Test status
Simulation time 653162948 ps
CPU time 0.96 seconds
Started Jul 17 06:56:27 PM PDT 24
Finished Jul 17 06:56:35 PM PDT 24
Peak memory 196872 kb
Host smart-545e7cc7-d7fd-475b-9ab9-c8fbfc70bcd3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2577765051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2577765051
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2043940802
Short name T892
Test name
Test status
Simulation time 268264336 ps
CPU time 1.08 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:31 PM PDT 24
Peak memory 197040 kb
Host smart-aaf9f2c8-9227-48a9-9060-46ef1b2d8d8f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043940802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2043940802
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2502898039
Short name T884
Test name
Test status
Simulation time 100035019 ps
CPU time 1.36 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:32 PM PDT 24
Peak memory 196060 kb
Host smart-c8ebf2fe-8bc3-4b33-843b-85bba716d10d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2502898039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2502898039
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2087328732
Short name T936
Test name
Test status
Simulation time 83397022 ps
CPU time 1.39 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 198404 kb
Host smart-c52c2c9f-1b90-4b44-9934-ed08a6461d7a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087328732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2087328732
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.407976902
Short name T907
Test name
Test status
Simulation time 322522088 ps
CPU time 1.55 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:28 PM PDT 24
Peak memory 198444 kb
Host smart-19155072-ca67-4e56-af6c-885d2fdbe272
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=407976902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.407976902
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2044815122
Short name T940
Test name
Test status
Simulation time 169927228 ps
CPU time 1.3 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:26 PM PDT 24
Peak memory 197036 kb
Host smart-c21ea40b-0b3b-4e01-b5f3-f2b926334e5a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044815122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2044815122
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1273918626
Short name T874
Test name
Test status
Simulation time 176651483 ps
CPU time 1.27 seconds
Started Jul 17 06:56:26 PM PDT 24
Finished Jul 17 06:56:35 PM PDT 24
Peak memory 197484 kb
Host smart-75c39d30-88d2-4582-bbb3-ea86a46447e0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1273918626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1273918626
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2089230126
Short name T880
Test name
Test status
Simulation time 97695158 ps
CPU time 1.59 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:32 PM PDT 24
Peak memory 198432 kb
Host smart-f66a8620-508b-4547-815c-349972635d72
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089230126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2089230126
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.701870529
Short name T879
Test name
Test status
Simulation time 95014031 ps
CPU time 0.86 seconds
Started Jul 17 06:56:23 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 197048 kb
Host smart-07f2b7a2-cf96-48ad-87c5-60b7e5e33486
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=701870529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.701870529
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.838724674
Short name T919
Test name
Test status
Simulation time 61235567 ps
CPU time 1.22 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:26 PM PDT 24
Peak memory 197224 kb
Host smart-13c9586b-8461-4fb8-b47d-47d645d314e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838724674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.838724674
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.4035824242
Short name T917
Test name
Test status
Simulation time 64765299 ps
CPU time 1.09 seconds
Started Jul 17 06:56:21 PM PDT 24
Finished Jul 17 06:56:27 PM PDT 24
Peak memory 198484 kb
Host smart-30519129-a2a2-43c5-a2c3-950128071ed5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4035824242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.4035824242
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2695153827
Short name T858
Test name
Test status
Simulation time 186911138 ps
CPU time 1.32 seconds
Started Jul 17 06:56:19 PM PDT 24
Finished Jul 17 06:56:22 PM PDT 24
Peak memory 196996 kb
Host smart-d0453eb7-4b1a-427b-a434-f2dd832ae21c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695153827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2695153827
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3996140708
Short name T898
Test name
Test status
Simulation time 101351345 ps
CPU time 1.32 seconds
Started Jul 17 06:56:22 PM PDT 24
Finished Jul 17 06:56:28 PM PDT 24
Peak memory 198436 kb
Host smart-c0bcb015-4ba5-46eb-8ae7-2bf0cb30a877
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3996140708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3996140708
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.166731820
Short name T857
Test name
Test status
Simulation time 35246383 ps
CPU time 0.96 seconds
Started Jul 17 06:56:27 PM PDT 24
Finished Jul 17 06:56:36 PM PDT 24
Peak memory 197096 kb
Host smart-6a0a4b1e-05f3-4030-8637-af787fbc665a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166731820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.166731820
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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