Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3844606	1			T21	1		T1	29938		T11	1
all_pins[1]	3844606	1			T21	1		T1	29938		T11	1
all_pins[2]	3844606	1			T21	1		T1	29938		T11	1
all_pins[3]	3844606	1			T21	1		T1	29938		T11	1
all_pins[4]	3844606	1			T21	1		T1	29938		T11	1
all_pins[5]	3844606	1			T21	1		T1	29938		T11	1
all_pins[6]	3844606	1			T21	1		T1	29938		T11	1
all_pins[7]	3844606	1			T21	1		T1	29938		T11	1
all_pins[8]	3844606	1			T21	1		T1	29938		T11	1
all_pins[9]	3844606	1			T21	1		T1	29938		T11	1
all_pins[10]	3844606	1			T21	1		T1	29938		T11	1
all_pins[11]	3844606	1			T21	1		T1	29938		T11	1
all_pins[12]	3844606	1			T21	1		T1	29938		T11	1
all_pins[13]	3844606	1			T21	1		T1	29938		T11	1
all_pins[14]	3844606	1			T21	1		T1	29938		T11	1
all_pins[15]	3844606	1			T21	1		T1	29938		T11	1
all_pins[16]	3844606	1			T21	1		T1	29938		T11	1
all_pins[17]	3844606	1			T21	1		T1	29938		T11	1
all_pins[18]	3844606	1			T21	1		T1	29938		T11	1
all_pins[19]	3844606	1			T21	1		T1	29938		T11	1
all_pins[20]	3844606	1			T21	1		T1	29938		T11	1
all_pins[21]	3844606	1			T21	1		T1	29938		T11	1
all_pins[22]	3844606	1			T21	1		T1	29938		T11	1
all_pins[23]	3844606	1			T21	1		T1	29938		T11	1
all_pins[24]	3844606	1			T21	1		T1	29938		T11	1
all_pins[25]	3844606	1			T21	1		T1	29938		T11	1
all_pins[26]	3844606	1			T21	1		T1	29938		T11	1
all_pins[27]	3844606	1			T21	1		T1	29938		T11	1
all_pins[28]	3844606	1			T21	1		T1	29938		T11	1
all_pins[29]	3844606	1			T21	1		T1	29938		T11	1
all_pins[30]	3844606	1			T21	1		T1	29938		T11	1
all_pins[31]	3844606	1			T21	1		T1	29938		T11	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	76439669	1			T21	32		T1	592818		T11	32
values[0x1]	46587723	1			T1	365198		T13	89		T16	16343
transitions[0x0=>0x1]	27912582	1			T1	218770		T13	56		T16	9669
transitions[0x1=>0x0]	27912430	1			T1	218770		T13	56		T16	9669

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2389421	1			T21	1		T1	18607		T11	1
all_pins[0]	values[0x1]	1455185	1			T1	11331		T16	460		T17	19
all_pins[0]	transitions[0x0=>0x1]	899876	1			T1	6802		T16	263		T17	11
all_pins[0]	transitions[0x1=>0x0]	900615	1			T1	6899		T16	269		T17	18
all_pins[1]	values[0x0]	2386985	1			T21	1		T1	18136		T11	1
all_pins[1]	values[0x1]	1457621	1			T1	11802		T13	4		T16	470
all_pins[1]	transitions[0x0=>0x1]	872412	1			T1	6873		T13	4		T16	334
all_pins[1]	transitions[0x1=>0x0]	869976	1			T1	6402		T16	324		T17	17
all_pins[2]	values[0x0]	2387381	1			T21	1		T1	18734		T11	1
all_pins[2]	values[0x1]	1457225	1			T1	11204		T16	567		T17	39
all_pins[2]	transitions[0x0=>0x1]	872983	1			T1	6625		T16	408		T17	30
all_pins[2]	transitions[0x1=>0x0]	873379	1			T1	7223		T13	4		T16	311
all_pins[3]	values[0x0]	2393198	1			T21	1		T1	18332		T11	1
all_pins[3]	values[0x1]	1451408	1			T1	11606		T16	381		T17	16
all_pins[3]	transitions[0x0=>0x1]	866066	1			T1	6941		T16	219		T17	10
all_pins[3]	transitions[0x1=>0x0]	871883	1			T1	6539		T16	405		T17	33
all_pins[4]	values[0x0]	2388533	1			T21	1		T1	18181		T11	1
all_pins[4]	values[0x1]	1456073	1			T1	11757		T13	4		T16	491
all_pins[4]	transitions[0x0=>0x1]	872752	1			T1	6832		T13	4		T16	303
all_pins[4]	transitions[0x1=>0x0]	868087	1			T1	6681		T16	193		T17	12
all_pins[5]	values[0x0]	2390834	1			T21	1		T1	18704		T11	1
all_pins[5]	values[0x1]	1453772	1			T1	11234		T13	1		T16	518
all_pins[5]	transitions[0x0=>0x1]	871396	1			T1	6878		T16	295		T17	20
all_pins[5]	transitions[0x1=>0x0]	873697	1			T1	7401		T13	3		T16	268
all_pins[6]	values[0x0]	2389349	1			T21	1		T1	18668		T11	1
all_pins[6]	values[0x1]	1455257	1			T1	11270		T13	6		T16	482
all_pins[6]	transitions[0x0=>0x1]	870902	1			T1	6929		T13	6		T16	271
all_pins[6]	transitions[0x1=>0x0]	869417	1			T1	6893		T13	1		T16	307
all_pins[7]	values[0x0]	2383196	1			T21	1		T1	18511		T11	1
all_pins[7]	values[0x1]	1461410	1			T1	11427		T16	537		T17	23
all_pins[7]	transitions[0x0=>0x1]	873891	1			T1	6937		T16	344		T17	15
all_pins[7]	transitions[0x1=>0x0]	867738	1			T1	6780		T13	6		T16	289
all_pins[8]	values[0x0]	2389402	1			T21	1		T1	18421		T11	1
all_pins[8]	values[0x1]	1455204	1			T1	11517		T13	1		T16	510
all_pins[8]	transitions[0x0=>0x1]	868634	1			T1	6953		T13	1		T16	266
all_pins[8]	transitions[0x1=>0x0]	874840	1			T1	6863		T16	293		T17	13
all_pins[9]	values[0x0]	2393604	1			T21	1		T1	18614		T11	1
all_pins[9]	values[0x1]	1451002	1			T1	11324		T16	564		T17	26
all_pins[9]	transitions[0x0=>0x1]	869057	1			T1	6758		T16	311		T17	11
all_pins[9]	transitions[0x1=>0x0]	873259	1			T1	6951		T13	1		T16	257
all_pins[10]	values[0x0]	2385278	1			T21	1		T1	18198		T11	1
all_pins[10]	values[0x1]	1459328	1			T1	11740		T13	6		T16	519
all_pins[10]	transitions[0x0=>0x1]	876328	1			T1	7257		T13	6		T16	313
all_pins[10]	transitions[0x1=>0x0]	868002	1			T1	6841		T16	358		T17	17
all_pins[11]	values[0x0]	2389135	1			T21	1		T1	18779		T11	1
all_pins[11]	values[0x1]	1455471	1			T1	11159		T13	8		T16	423
all_pins[11]	transitions[0x0=>0x1]	870140	1			T1	6493		T13	3		T16	241
all_pins[11]	transitions[0x1=>0x0]	873997	1			T1	7074		T13	1		T16	337
all_pins[12]	values[0x0]	2389641	1			T21	1		T1	18624		T11	1
all_pins[12]	values[0x1]	1454965	1			T1	11314		T13	6		T16	453
all_pins[12]	transitions[0x0=>0x1]	870252	1			T1	6714		T13	1		T16	295
all_pins[12]	transitions[0x1=>0x0]	870758	1			T1	6559		T13	3		T16	265
all_pins[13]	values[0x0]	2389004	1			T21	1		T1	18719		T11	1
all_pins[13]	values[0x1]	1455602	1			T1	11219		T13	6		T16	397
all_pins[13]	transitions[0x0=>0x1]	871496	1			T1	6842		T13	1		T16	300
all_pins[13]	transitions[0x1=>0x0]	870859	1			T1	6937		T13	1		T16	356
all_pins[14]	values[0x0]	2386928	1			T21	1		T1	18462		T11	1
all_pins[14]	values[0x1]	1457678	1			T1	11476		T13	5		T16	459
all_pins[14]	transitions[0x0=>0x1]	871259	1			T1	6908		T13	2		T16	310
all_pins[14]	transitions[0x1=>0x0]	869183	1			T1	6651		T13	3		T16	248
all_pins[15]	values[0x0]	2388140	1			T21	1		T1	18939		T11	1
all_pins[15]	values[0x1]	1456466	1			T1	10999		T13	1		T16	526
all_pins[15]	transitions[0x0=>0x1]	871077	1			T1	6387		T16	296		T17	15
all_pins[15]	transitions[0x1=>0x0]	872289	1			T1	6864		T13	4		T16	229
all_pins[16]	values[0x0]	2385224	1			T21	1		T1	18713		T11	1
all_pins[16]	values[0x1]	1459382	1			T1	11225		T16	600		T17	17
all_pins[16]	transitions[0x0=>0x1]	873268	1			T1	6865		T16	372		T17	10
all_pins[16]	transitions[0x1=>0x0]	870352	1			T1	6639		T13	1		T16	298
all_pins[17]	values[0x0]	2393245	1			T21	1		T1	18891		T11	1
all_pins[17]	values[0x1]	1451361	1			T1	11047		T13	3		T16	648
all_pins[17]	transitions[0x0=>0x1]	867302	1			T1	6778		T13	3		T16	320
all_pins[17]	transitions[0x1=>0x0]	875323	1			T1	6956		T16	272		T17	9
all_pins[18]	values[0x0]	2385362	1			T21	1		T1	18581		T11	1
all_pins[18]	values[0x1]	1459244	1			T1	11357		T13	3		T16	430
all_pins[18]	transitions[0x0=>0x1]	875443	1			T1	7050		T16	214		T17	18
all_pins[18]	transitions[0x1=>0x0]	867560	1			T1	6740		T16	432		T17	9
all_pins[19]	values[0x0]	2390239	1			T21	1		T1	18433		T11	1
all_pins[19]	values[0x1]	1454367	1			T1	11505		T16	608		T17	14
all_pins[19]	transitions[0x0=>0x1]	868157	1			T1	6953		T16	419		T17	13
all_pins[19]	transitions[0x1=>0x0]	873034	1			T1	6805		T13	3		T16	241
all_pins[20]	values[0x0]	2389388	1			T21	1		T1	18404		T11	1
all_pins[20]	values[0x1]	1455218	1			T1	11534		T13	8		T16	620
all_pins[20]	transitions[0x0=>0x1]	870946	1			T1	6875		T13	8		T16	292
all_pins[20]	transitions[0x1=>0x0]	870095	1			T1	6846		T16	280		T17	11
all_pins[21]	values[0x0]	2389505	1			T21	1		T1	18405		T11	1
all_pins[21]	values[0x1]	1455101	1			T1	11533		T13	5		T16	439
all_pins[21]	transitions[0x0=>0x1]	870693	1			T1	6798		T16	238		T17	16
all_pins[21]	transitions[0x1=>0x0]	870810	1			T1	6799		T13	3		T16	419
all_pins[22]	values[0x0]	2389355	1			T21	1		T1	18625		T11	1
all_pins[22]	values[0x1]	1455251	1			T1	11313		T16	426		T17	14
all_pins[22]	transitions[0x0=>0x1]	872852	1			T1	6790		T16	276		T17	11
all_pins[22]	transitions[0x1=>0x0]	872702	1			T1	7010		T13	5		T16	289
all_pins[23]	values[0x0]	2388237	1			T21	1		T1	18572		T11	1
all_pins[23]	values[0x1]	1456369	1			T1	11366		T13	4		T16	582
all_pins[23]	transitions[0x0=>0x1]	871517	1			T1	6739		T13	4		T16	370
all_pins[23]	transitions[0x1=>0x0]	870399	1			T1	6686		T16	214		T17	11
all_pins[24]	values[0x0]	2386419	1			T21	1		T1	18424		T11	1
all_pins[24]	values[0x1]	1458187	1			T1	11514		T13	3		T16	561
all_pins[24]	transitions[0x0=>0x1]	872087	1			T1	6659		T13	3		T16	325
all_pins[24]	transitions[0x1=>0x0]	870269	1			T1	6511		T13	4		T16	346
all_pins[25]	values[0x0]	2392376	1			T21	1		T1	18160		T11	1
all_pins[25]	values[0x1]	1452230	1			T1	11778		T13	6		T16	494
all_pins[25]	transitions[0x0=>0x1]	870671	1			T1	7022		T13	3		T16	232
all_pins[25]	transitions[0x1=>0x0]	876628	1			T1	6758		T16	299		T17	13
all_pins[26]	values[0x0]	2382582	1			T21	1		T1	18460		T11	1
all_pins[26]	values[0x1]	1462024	1			T1	11478		T13	2		T16	414
all_pins[26]	transitions[0x0=>0x1]	876810	1			T1	6691		T13	2		T16	300
all_pins[26]	transitions[0x1=>0x0]	867016	1			T1	6991		T13	6		T16	380
all_pins[27]	values[0x0]	2391187	1			T21	1		T1	18145		T11	1
all_pins[27]	values[0x1]	1453419	1			T1	11793		T13	4		T16	567
all_pins[27]	transitions[0x0=>0x1]	867905	1			T1	7210		T13	2		T16	389
all_pins[27]	transitions[0x1=>0x0]	876510	1			T1	6895		T16	236		T17	26
all_pins[28]	values[0x0]	2388855	1			T21	1		T1	18807		T11	1
all_pins[28]	values[0x1]	1455751	1			T1	11131		T16	573		T17	14
all_pins[28]	transitions[0x0=>0x1]	873415	1			T1	6561		T16	294		T17	13
all_pins[28]	transitions[0x1=>0x0]	871083	1			T1	7223		T13	4		T16	288
all_pins[29]	values[0x0]	2385955	1			T21	1		T1	18398		T11	1
all_pins[29]	values[0x1]	1458651	1			T1	11540		T13	3		T16	557
all_pins[29]	transitions[0x0=>0x1]	873461	1			T1	6911		T13	3		T16	333
all_pins[29]	transitions[0x1=>0x0]	870561	1			T1	6502		T16	349		T17	9
all_pins[30]	values[0x0]	2393181	1			T21	1		T1	18661		T11	1
all_pins[30]	values[0x1]	1451425	1			T1	11277		T16	601		T17	14
all_pins[30]	transitions[0x0=>0x1]	868400	1			T1	6863		T16	348		T17	7
all_pins[30]	transitions[0x1=>0x0]	875626	1			T1	7126		T13	3		T16	304
all_pins[31]	values[0x0]	2388530	1			T21	1		T1	18510		T11	1
all_pins[31]	values[0x1]	1456076	1			T1	11428		T16	466		T17	26
all_pins[31]	transitions[0x0=>0x1]	871134	1			T1	6876		T16	178		T17	19
all_pins[31]	transitions[0x1=>0x0]	866483	1			T1	6725		T16	313		T17	7