Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[1]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[2]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[3]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[4]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[5]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[6]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[7]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[8]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[9]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[10]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[11]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[12]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[13]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[14]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[15]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[16]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[17]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[18]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[19]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[20]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[21]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[22]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[23]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[24]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[25]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[26]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[27]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[28]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[29]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[30]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[31]	12788157	1			T21	263		T1	100587		T11	822

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

243440356

1

T21

6497

T1

118355

T11

20597

auto[1]

165780668

1

T21

1919

T1

203523

T11

5707

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

327971372

1

T21

6652

T1

262697

T11

19024

auto[1]

81249652

1

T21

1764

T1

591814

T11

7280

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

304110843

1

T21

4492

T1

243312

T11

13252

auto[1]

105110181

1

T21

3924

T1

785664

T11

13052

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4725843	1			T21	116		T1	26410		T11	200
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3500758	1			T21	27		T1	40239		T11	13
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1276922	1			T21	38		T1	9437		T11	91
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1602217	1			T21	55		T1	1091		T11	321
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	413902	1			T21	9		T1	13842		T11	50
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1268515	1			T21	18		T1	9568		T11	147
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4726249	1			T21	115		T1	26148		T11	276
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3501104	1			T21	16		T1	40239		T11	42
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1275288	1			T21	27		T1	9069		T11	96
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1603455	1			T21	86		T1	1198		T11	244
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	417001	1			T21	7		T1	14640		T11	29
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1265060	1			T21	12		T1	9293		T11	135
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4728273	1			T21	94		T1	26713		T11	240
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3498645	1			T21	23		T1	40254		T11	38
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1278388	1			T21	29		T1	9080		T11	113
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1602377	1			T21	87		T1	1146		T11	273
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	418244	1			T21	11		T1	14266		T11	24
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1262230	1			T21	19		T1	9128		T11	134
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4719785	1			T21	81		T1	26763		T11	322
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3502163	1			T21	26		T1	40077		T11	45
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1278061	1			T21	34		T1	9316		T11	73
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1604907	1			T21	74		T1	970		T11	254
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	418592	1			T21	13		T1	14013		T11	27
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1264649	1			T21	35		T1	9448		T11	101
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4728566	1			T21	147		T1	26532		T11	278
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3497782	1			T21	24		T1	40036		T11	34
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1271585	1			T21	24		T1	9530		T11	118
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1606993	1			T21	56		T1	1152		T11	245
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	419344	1			T21	8		T1	14096		T11	21
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1263887	1			T21	4		T1	9241		T11	126
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4720808	1			T21	103		T1	26468		T11	305
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3506798	1			T21	25		T1	40243		T11	25
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1276405	1			T21	37		T1	9489		T11	97
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1607010	1			T21	63		T1	1024		T11	264
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	416417	1			T21	9		T1	14098		T11	36
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1260719	1			T21	26		T1	9265		T11	95
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4716329	1			T21	86		T1	26621		T11	209
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3506335	1			T21	24		T1	40387		T11	34
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1276784	1			T21	37		T1	9010		T11	116
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1607303	1			T21	78		T1	1144		T11	319
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	415185	1			T21	8		T1	14313		T11	34
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1266221	1			T21	30		T1	9112		T11	110
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4715975	1			T21	135		T1	26834		T11	321
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3505989	1			T21	24		T1	39571		T11	35
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1278461	1			T21	26		T1	9485		T11	140
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1603207	1			T21	55		T1	1105		T11	213
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	415109	1			T21	7		T1	14319		T11	35
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1269416	1			T21	16		T1	9273		T11	78
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4734025	1			T21	62		T1	26554		T11	216
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3489950	1			T21	4		T1	40551		T11	25
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1275709	1			T21	14		T1	9241		T11	94
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1602419	1			T21	128		T1	1174		T11	306
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	416218	1			T21	25		T1	14001		T11	32
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1269836	1			T21	30		T1	9066		T11	149
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4725347	1			T21	65		T1	26420		T11	263
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3504780	1			T21	11		T1	40227		T11	33
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1279452	1			T21	41		T1	9460		T11	144
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1601258	1			T21	89		T1	1119		T11	238
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	412597	1			T21	22		T1	14222		T11	29
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1264723	1			T21	35		T1	9139		T11	115
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4731238	1			T21	104		T1	26325		T11	303
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3493427	1			T21	23		T1	40171		T11	51
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1279536	1			T21	32		T1	9310		T11	121
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1602230	1			T21	55		T1	1190		T11	206
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	416288	1			T21	13		T1	14335		T11	22
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1265438	1			T21	36		T1	9256		T11	119
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4717744	1			T21	123		T1	26573		T11	295
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3510269	1			T21	21		T1	40167		T11	21
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1276045	1			T21	34		T1	9067		T11	109
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1599773	1			T21	55		T1	1144		T11	253
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	415768	1			T21	3		T1	14418		T11	40
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1268558	1			T21	27		T1	9218		T11	104
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4723316	1			T21	49		T1	26713		T11	303
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3507253	1			T21	5		T1	40033		T11	46
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1279435	1			T21	4		T1	9280		T11	136
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1599812	1			T21	142		T1	1171		T11	191
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	416365	1			T21	24		T1	14388		T11	13
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1261976	1			T21	39		T1	9002		T11	133
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4719730	1			T21	142		T1	26643		T11	263
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3508751	1			T21	15		T1	39861		T11	20
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1281574	1			T21	39		T1	9332		T11	106
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1598688	1			T21	47		T1	1163		T11	252
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	415450	1			T21	5		T1	14160		T11	41
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1263964	1			T21	15		T1	9428		T11	140
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4729113	1			T21	69		T1	26456		T11	224
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3498083	1			T21	11		T1	40059		T11	31
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1274501	1			T21	18		T1	9427		T11	155
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1606593	1			T21	90		T1	1081		T11	284
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	412955	1			T21	19		T1	14481		T11	31
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1266912	1			T21	56		T1	9083		T11	97
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4724384	1			T21	94		T1	26393		T11	256
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3492022	1			T21	16		T1	40082		T11	19
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1281646	1			T21	29		T1	9137		T11	102
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1603961	1			T21	85		T1	1182		T11	314
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	417026	1			T21	13		T1	14347		T11	26
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1269118	1			T21	26		T1	9446		T11	105
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4732666	1			T21	108		T1	26425		T11	309
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3495644	1			T21	22		T1	40229		T11	44
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1276588	1			T21	12		T1	9319		T11	112
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1601690	1			T21	62		T1	1168		T11	236
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	417745	1			T21	16		T1	14288		T11	32
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1263824	1			T21	43		T1	9158		T11	89
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4728732	1			T21	85		T1	26416		T11	244
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3498732	1			T21	13		T1	40297		T11	40
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1271512	1			T21	30		T1	9773		T11	110
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1607407	1			T21	99		T1	1163		T11	271
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	417955	1			T21	15		T1	14388		T11	26
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1263819	1			T21	21		T1	8550		T11	131
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4731762	1			T21	77		T1	26527		T11	283
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3499800	1			T21	17		T1	40276		T11	43
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1266370	1			T21	32		T1	9300		T11	117
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1607044	1			T21	76		T1	1026		T11	241
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	417564	1			T21	15		T1	13923		T11	25
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1265617	1			T21	46		T1	9535		T11	113
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4726553	1			T21	45		T1	26761		T11	245
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3500240	1			T21	7		T1	39669		T11	15
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1272997	1			T21	13		T1	9463		T11	122
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1608482	1			T21	107		T1	1178		T11	277
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	417075	1			T21	32		T1	14379		T11	34
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1262810	1			T21	59		T1	9137		T11	129
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4733631	1			T21	116		T1	26670		T11	259
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3503198	1			T21	43		T1	40374		T11	38
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1280026	1			T21	33		T1	9389		T11	105
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1601601	1			T21	26		T1	1080		T11	247
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	413897	1			T21	8		T1	14064		T11	29
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1255804	1			T21	37		T1	9010		T11	144
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4723544	1			T21	105		T1	26291		T11	257
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3504080	1			T21	28		T1	40110		T11	26
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1275833	1			T21	36		T1	9243		T11	85
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1604886	1			T21	67		T1	1127		T11	312
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	416386	1			T21	13		T1	14614		T11	38
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1263428	1			T21	14		T1	9202		T11	104
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4746420	1			T21	100		T1	26750		T11	256
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3494020	1			T21	19		T1	40042		T11	19
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1272313	1			T21	38		T1	9070		T11	78
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1604806	1			T21	86		T1	1064		T11	312
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	414749	1			T21	6		T1	14106		T11	52
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1255849	1			T21	14		T1	9555		T11	105
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4726388	1			T21	91		T1	26846		T11	289
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3502315	1			T21	22		T1	40535		T11	44
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1272037	1			T21	35		T1	9768		T11	141
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1609070	1			T21	72		T1	984		T11	224
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	416407	1			T21	13		T1	13574		T11	27
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1261940	1			T21	30		T1	8880		T11	97
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4735654	1			T21	83		T1	26563		T11	291
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3495513	1			T21	23		T1	39713		T11	35
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1276202	1			T21	21		T1	9459		T11	117
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1604220	1			T21	95		T1	1149		T11	257
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	417391	1			T21	19		T1	14371		T11	32
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1259177	1			T21	22		T1	9332		T11	90
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4731648	1			T21	64		T1	26593		T11	219
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3491599	1			T21	15		T1	40264		T11	36
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1277758	1			T21	20		T1	9182		T11	115
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1608619	1			T21	132		T1	1145		T11	281
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	416322	1			T21	18		T1	14260		T11	36
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1262211	1			T21	14		T1	9143		T11	135
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4725094	1			T21	69		T1	26538		T11	205
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3506922	1			T21	13		T1	39860		T11	19
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1271789	1			T21	26		T1	9382		T11	112
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1605932	1			T21	101		T1	1089		T11	328
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	417459	1			T21	32		T1	14209		T11	42
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1260961	1			T21	22		T1	9509		T11	116
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4717306	1			T21	75		T1	26518		T11	359
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3508401	1			T21	17		T1	40094		T11	32
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1270676	1			T21	22		T1	9457		T11	84
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1610571	1			T21	107		T1	1125		T11	227
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	418360	1			T21	16		T1	14605		T11	25
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1262843	1			T21	26		T1	8788		T11	95
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4724708	1			T21	65		T1	26564		T11	271
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3504633	1			T21	15		T1	39946		T11	31
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1273057	1			T21	21		T1	8853		T11	123
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1606981	1			T21	125		T1	1187		T11	260
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	416746	1			T21	18		T1	14896		T11	33
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1262032	1			T21	19		T1	9141		T11	104
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4731147	1			T21	113		T1	26532		T11	269
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3502027	1			T21	24		T1	40825		T11	44
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1272613	1			T21	38		T1	9570		T11	127
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1607490	1			T21	54		T1	1012		T11	242
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	417254	1			T21	9		T1	13915		T11	33
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1257626	1			T21	25		T1	8733		T11	107
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4730418	1			T21	123		T1	26461		T11	231
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3496542	1			T21	14		T1	40182		T11	23
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1273957	1			T21	33		T1	9237		T11	122
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1609285	1			T21	55		T1	1128		T11	299
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	417863	1			T21	12		T1	14620		T11	39
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1260092	1			T21	26		T1	8959		T11	108
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4735098	1			T21	89		T1	26657		T11	318
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3496524	1			T21	14		T1	40618		T11	42
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1275530	1			T21	25		T1	9076		T11	149
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1603525	1			T21	97		T1	984		T11	197
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	416133	1			T21	14		T1	14247		T11	21
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1261347	1			T21	24		T1	9005		T11	95

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal