Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[1]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[2]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[3]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[4]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[5]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[6]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[7]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[8]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[9]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[10]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[11]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[12]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[13]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[14]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[15]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[16]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[17]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[18]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[19]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[20]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[21]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[22]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[23]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[24]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[25]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[26]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[27]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[28]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[29]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[30]	12788157	1			T21	263		T1	100587		T11	822
bins_for_gpio_bits[31]	12788157	1			T21	263		T1	100587		T11	822

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

243440356

1

T21

6497

T1

118355

T11

20597

auto[1]

165780668

1

T21

1919

T1

203523

T11

5707

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

243432907

1

T21

6487

T1

118369

T11

20597

auto[1]

165788117

1

T21

1929

T1

203509

T11

5707

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7376397	1			T21	204		T1	35155		T11	586
bins_for_gpio_bits[0]	auto[0]	auto[1]	228368	1			T21	5		T1	1785		T11	26
bins_for_gpio_bits[0]	auto[1]	auto[0]	228585	1			T21	5		T1	1783		T11	26
bins_for_gpio_bits[0]	auto[1]	auto[1]	4954807	1			T21	49		T1	61864		T11	184
bins_for_gpio_bits[1]	auto[0]	auto[0]	7376541	1			T21	226		T1	34722		T11	599
bins_for_gpio_bits[1]	auto[0]	auto[1]	228218	1			T21	2		T1	1697		T11	17
bins_for_gpio_bits[1]	auto[1]	auto[0]	228451	1			T21	2		T1	1693		T11	17
bins_for_gpio_bits[1]	auto[1]	auto[1]	4954947	1			T21	33		T1	62475		T11	189
bins_for_gpio_bits[2]	auto[0]	auto[0]	7381262	1			T21	207		T1	35256		T11	604
bins_for_gpio_bits[2]	auto[0]	auto[1]	227574	1			T21	3		T1	1686		T11	22
bins_for_gpio_bits[2]	auto[1]	auto[0]	227776	1			T21	3		T1	1683		T11	22
bins_for_gpio_bits[2]	auto[1]	auto[1]	4951545	1			T21	50		T1	61962		T11	174
bins_for_gpio_bits[3]	auto[0]	auto[0]	7374665	1			T21	184		T1	35369		T11	629
bins_for_gpio_bits[3]	auto[0]	auto[1]	227834	1			T21	5		T1	1686		T11	20
bins_for_gpio_bits[3]	auto[1]	auto[0]	228088	1			T21	5		T1	1680		T11	20
bins_for_gpio_bits[3]	auto[1]	auto[1]	4957570	1			T21	69		T1	61852		T11	153
bins_for_gpio_bits[4]	auto[0]	auto[0]	7379618	1			T21	226		T1	35503		T11	622
bins_for_gpio_bits[4]	auto[0]	auto[1]	227325	1			T21	1		T1	1713		T11	19
bins_for_gpio_bits[4]	auto[1]	auto[0]	227526	1			T21	1		T1	1711		T11	19
bins_for_gpio_bits[4]	auto[1]	auto[1]	4953688	1			T21	35		T1	61660		T11	162
bins_for_gpio_bits[5]	auto[0]	auto[0]	7376041	1			T21	196		T1	35276		T11	647
bins_for_gpio_bits[5]	auto[0]	auto[1]	227941	1			T21	6		T1	1712		T11	19
bins_for_gpio_bits[5]	auto[1]	auto[0]	228182	1			T21	7		T1	1705		T11	19
bins_for_gpio_bits[5]	auto[1]	auto[1]	4955993	1			T21	54		T1	61894		T11	137
bins_for_gpio_bits[6]	auto[0]	auto[0]	7371570	1			T21	197		T1	35075		T11	622
bins_for_gpio_bits[6]	auto[0]	auto[1]	228598	1			T21	4		T1	1706		T11	22
bins_for_gpio_bits[6]	auto[1]	auto[0]	228846	1			T21	4		T1	1700		T11	22
bins_for_gpio_bits[6]	auto[1]	auto[1]	4959143	1			T21	58		T1	62106		T11	156
bins_for_gpio_bits[7]	auto[0]	auto[0]	7369456	1			T21	212		T1	35693		T11	657
bins_for_gpio_bits[7]	auto[0]	auto[1]	227957	1			T21	3		T1	1735		T11	17
bins_for_gpio_bits[7]	auto[1]	auto[0]	228187	1			T21	4		T1	1731		T11	17
bins_for_gpio_bits[7]	auto[1]	auto[1]	4962557	1			T21	44		T1	61428		T11	131
bins_for_gpio_bits[8]	auto[0]	auto[0]	7383552	1			T21	197		T1	35269		T11	594
bins_for_gpio_bits[8]	auto[0]	auto[1]	228354	1			T21	7		T1	1706		T11	22
bins_for_gpio_bits[8]	auto[1]	auto[0]	228601	1			T21	7		T1	1700		T11	22
bins_for_gpio_bits[8]	auto[1]	auto[1]	4947650	1			T21	52		T1	61912		T11	184
bins_for_gpio_bits[9]	auto[0]	auto[0]	7377509	1			T21	186		T1	35310		T11	626
bins_for_gpio_bits[9]	auto[0]	auto[1]	228331	1			T21	9		T1	1694		T11	19
bins_for_gpio_bits[9]	auto[1]	auto[0]	228548	1			T21	9		T1	1689		T11	19
bins_for_gpio_bits[9]	auto[1]	auto[1]	4953769	1			T21	59		T1	61894		T11	158
bins_for_gpio_bits[10]	auto[0]	auto[0]	7385137	1			T21	186		T1	35108		T11	614
bins_for_gpio_bits[10]	auto[0]	auto[1]	227645	1			T21	5		T1	1722		T11	16
bins_for_gpio_bits[10]	auto[1]	auto[0]	227867	1			T21	5		T1	1717		T11	16
bins_for_gpio_bits[10]	auto[1]	auto[1]	4947508	1			T21	67		T1	62040		T11	176
bins_for_gpio_bits[11]	auto[0]	auto[0]	7364702	1			T21	206		T1	35093		T11	637
bins_for_gpio_bits[11]	auto[0]	auto[1]	228598	1			T21	5		T1	1692		T11	20
bins_for_gpio_bits[11]	auto[1]	auto[0]	228860	1			T21	6		T1	1691		T11	20
bins_for_gpio_bits[11]	auto[1]	auto[1]	4965997	1			T21	46		T1	62111		T11	145
bins_for_gpio_bits[12]	auto[0]	auto[0]	7374223	1			T21	188		T1	35457		T11	610
bins_for_gpio_bits[12]	auto[0]	auto[1]	228110	1			T21	7		T1	1711		T11	20
bins_for_gpio_bits[12]	auto[1]	auto[0]	228340	1			T21	7		T1	1707		T11	20
bins_for_gpio_bits[12]	auto[1]	auto[1]	4957484	1			T21	61		T1	61712		T11	172
bins_for_gpio_bits[13]	auto[0]	auto[0]	7371639	1			T21	225		T1	35430		T11	593
bins_for_gpio_bits[13]	auto[0]	auto[1]	228135	1			T21	3		T1	1712		T11	28
bins_for_gpio_bits[13]	auto[1]	auto[0]	228353	1			T21	3		T1	1708		T11	28
bins_for_gpio_bits[13]	auto[1]	auto[1]	4960030	1			T21	32		T1	61737		T11	173
bins_for_gpio_bits[14]	auto[0]	auto[0]	7381736	1			T21	166		T1	35248		T11	647
bins_for_gpio_bits[14]	auto[0]	auto[1]	228227	1			T21	11		T1	1720		T11	16
bins_for_gpio_bits[14]	auto[1]	auto[0]	228471	1			T21	11		T1	1716		T11	16
bins_for_gpio_bits[14]	auto[1]	auto[1]	4949723	1			T21	75		T1	61903		T11	143
bins_for_gpio_bits[15]	auto[0]	auto[0]	7381103	1			T21	205		T1	34980		T11	654
bins_for_gpio_bits[15]	auto[0]	auto[1]	228645	1			T21	3		T1	1733		T11	18
bins_for_gpio_bits[15]	auto[1]	auto[0]	228888	1			T21	3		T1	1732		T11	18
bins_for_gpio_bits[15]	auto[1]	auto[1]	4949521	1			T21	52		T1	62142		T11	132
bins_for_gpio_bits[16]	auto[0]	auto[0]	7382627	1			T21	176		T1	35203		T11	642
bins_for_gpio_bits[16]	auto[0]	auto[1]	228087	1			T21	5		T1	1712		T11	15
bins_for_gpio_bits[16]	auto[1]	auto[0]	228317	1			T21	6		T1	1709		T11	15
bins_for_gpio_bits[16]	auto[1]	auto[1]	4949126	1			T21	76		T1	61963		T11	150
bins_for_gpio_bits[17]	auto[0]	auto[0]	7379311	1			T21	210		T1	35656		T11	605
bins_for_gpio_bits[17]	auto[0]	auto[1]	228092	1			T21	3		T1	1703		T11	20
bins_for_gpio_bits[17]	auto[1]	auto[0]	228340	1			T21	4		T1	1696		T11	20
bins_for_gpio_bits[17]	auto[1]	auto[1]	4952414	1			T21	46		T1	61532		T11	177
bins_for_gpio_bits[18]	auto[0]	auto[0]	7377232	1			T21	177		T1	35158		T11	626
bins_for_gpio_bits[18]	auto[0]	auto[1]	227707	1			T21	7		T1	1704		T11	15
bins_for_gpio_bits[18]	auto[1]	auto[0]	227944	1			T21	8		T1	1695		T11	15
bins_for_gpio_bits[18]	auto[1]	auto[1]	4955274	1			T21	71		T1	62030		T11	166
bins_for_gpio_bits[19]	auto[0]	auto[0]	7379828	1			T21	155		T1	35715		T11	620
bins_for_gpio_bits[19]	auto[0]	auto[1]	227976	1			T21	9		T1	1693		T11	24
bins_for_gpio_bits[19]	auto[1]	auto[0]	228204	1			T21	10		T1	1687		T11	24
bins_for_gpio_bits[19]	auto[1]	auto[1]	4952149	1			T21	89		T1	61492		T11	154
bins_for_gpio_bits[20]	auto[0]	auto[0]	7387272	1			T21	169		T1	35431		T11	587
bins_for_gpio_bits[20]	auto[0]	auto[1]	227769	1			T21	5		T1	1712		T11	24
bins_for_gpio_bits[20]	auto[1]	auto[0]	227986	1			T21	6		T1	1708		T11	24
bins_for_gpio_bits[20]	auto[1]	auto[1]	4945130	1			T21	83		T1	61736		T11	187
bins_for_gpio_bits[21]	auto[0]	auto[0]	7375483	1			T21	204		T1	34970		T11	633
bins_for_gpio_bits[21]	auto[0]	auto[1]	228492	1			T21	4		T1	1695		T11	21
bins_for_gpio_bits[21]	auto[1]	auto[0]	228780	1			T21	4		T1	1691		T11	21
bins_for_gpio_bits[21]	auto[1]	auto[1]	4955402	1			T21	51		T1	62231		T11	147
bins_for_gpio_bits[22]	auto[0]	auto[0]	7395968	1			T21	220		T1	35206		T11	627
bins_for_gpio_bits[22]	auto[0]	auto[1]	227351	1			T21	4		T1	1683		T11	19
bins_for_gpio_bits[22]	auto[1]	auto[0]	227571	1			T21	4		T1	1678		T11	19
bins_for_gpio_bits[22]	auto[1]	auto[1]	4937267	1			T21	35		T1	62020		T11	157
bins_for_gpio_bits[23]	auto[0]	auto[0]	7379061	1			T21	192		T1	35858		T11	638
bins_for_gpio_bits[23]	auto[0]	auto[1]	228204	1			T21	6		T1	1743		T11	16
bins_for_gpio_bits[23]	auto[1]	auto[0]	228434	1			T21	6		T1	1740		T11	16
bins_for_gpio_bits[23]	auto[1]	auto[1]	4952458	1			T21	59		T1	61246		T11	152
bins_for_gpio_bits[24]	auto[0]	auto[0]	7387773	1			T21	196		T1	35464		T11	647
bins_for_gpio_bits[24]	auto[0]	auto[1]	228101	1			T21	3		T1	1711		T11	18
bins_for_gpio_bits[24]	auto[1]	auto[0]	228303	1			T21	3		T1	1707		T11	18
bins_for_gpio_bits[24]	auto[1]	auto[1]	4943980	1			T21	61		T1	61705		T11	139
bins_for_gpio_bits[25]	auto[0]	auto[0]	7389236	1			T21	212		T1	35228		T11	589
bins_for_gpio_bits[25]	auto[0]	auto[1]	228572	1			T21	4		T1	1695		T11	26
bins_for_gpio_bits[25]	auto[1]	auto[0]	228789	1			T21	4		T1	1692		T11	26
bins_for_gpio_bits[25]	auto[1]	auto[1]	4941560	1			T21	43		T1	61972		T11	181
bins_for_gpio_bits[26]	auto[0]	auto[0]	7374299	1			T21	191		T1	35283		T11	622
bins_for_gpio_bits[26]	auto[0]	auto[1]	228276	1			T21	5		T1	1731		T11	23
bins_for_gpio_bits[26]	auto[1]	auto[0]	228516	1			T21	5		T1	1726		T11	23
bins_for_gpio_bits[26]	auto[1]	auto[1]	4957066	1			T21	62		T1	61847		T11	154
bins_for_gpio_bits[27]	auto[0]	auto[0]	7370112	1			T21	197		T1	35371		T11	653
bins_for_gpio_bits[27]	auto[0]	auto[1]	228216	1			T21	7		T1	1736		T11	17
bins_for_gpio_bits[27]	auto[1]	auto[0]	228441	1			T21	7		T1	1729		T11	17
bins_for_gpio_bits[27]	auto[1]	auto[1]	4961388	1			T21	52		T1	61751		T11	135
bins_for_gpio_bits[28]	auto[0]	auto[0]	7376548	1			T21	206		T1	34937		T11	635
bins_for_gpio_bits[28]	auto[0]	auto[1]	227969	1			T21	4		T1	1672		T11	19
bins_for_gpio_bits[28]	auto[1]	auto[0]	228198	1			T21	5		T1	1667		T11	19
bins_for_gpio_bits[28]	auto[1]	auto[1]	4955442	1			T21	48		T1	62311		T11	149
bins_for_gpio_bits[29]	auto[0]	auto[0]	7383152	1			T21	200		T1	35345		T11	621
bins_for_gpio_bits[29]	auto[0]	auto[1]	227824	1			T21	5		T1	1772		T11	17
bins_for_gpio_bits[29]	auto[1]	auto[0]	228098	1			T21	5		T1	1769		T11	17
bins_for_gpio_bits[29]	auto[1]	auto[1]	4949083	1			T21	53		T1	61701		T11	167
bins_for_gpio_bits[30]	auto[0]	auto[0]	7385640	1			T21	206		T1	35172		T11	634
bins_for_gpio_bits[30]	auto[0]	auto[1]	227786	1			T21	5		T1	1657		T11	18
bins_for_gpio_bits[30]	auto[1]	auto[0]	228020	1			T21	5		T1	1654		T11	18
bins_for_gpio_bits[30]	auto[1]	auto[1]	4946711	1			T21	47		T1	62104		T11	152
bins_for_gpio_bits[31]	auto[0]	auto[0]	7385682	1			T21	205		T1	34988		T11	649
bins_for_gpio_bits[31]	auto[0]	auto[1]	228250	1			T21	5		T1	1735		T11	15
bins_for_gpio_bits[31]	auto[1]	auto[0]	228471	1			T21	6		T1	1729		T11	15
bins_for_gpio_bits[31]	auto[1]	auto[1]	4945754	1			T21	47		T1	62135		T11	143