Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459835 |
1 |
|
|
T21 |
137 |
|
T1 |
57962 |
|
T11 |
421 |
| auto[1] |
5490776 |
1 |
|
|
T1 |
45654 |
|
T16 |
1442 |
|
T17 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12248472 |
1 |
|
|
T21 |
137 |
|
T1 |
97119 |
|
T11 |
421 |
| auto[1] |
702139 |
1 |
|
|
T1 |
6497 |
|
T16 |
298 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7493191 |
1 |
|
|
T21 |
137 |
|
T1 |
58277 |
|
T11 |
421 |
| auto[1] |
5457420 |
1 |
|
|
T1 |
45339 |
|
T16 |
1579 |
|
T17 |
43 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2377897 |
1 |
|
|
T1 |
20117 |
|
T16 |
661 |
|
T17 |
26 |
| auto[1] |
auto[0] |
auto[1] |
350820 |
1 |
|
|
T1 |
3452 |
|
T16 |
152 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2377384 |
1 |
|
|
T1 |
18725 |
|
T16 |
620 |
|
T17 |
16 |
| auto[1] |
auto[1] |
auto[1] |
351319 |
1 |
|
|
T1 |
3045 |
|
T16 |
146 |
|
T2 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445873 |
1 |
|
|
T21 |
137 |
|
T1 |
54223 |
|
T11 |
421 |
| auto[1] |
5504738 |
1 |
|
|
T1 |
49393 |
|
T13 |
12 |
|
T16 |
1644 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12247046 |
1 |
|
|
T21 |
137 |
|
T1 |
97138 |
|
T11 |
421 |
| auto[1] |
703565 |
1 |
|
|
T1 |
6478 |
|
T16 |
313 |
|
T17 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7481098 |
1 |
|
|
T21 |
137 |
|
T1 |
58543 |
|
T11 |
421 |
| auto[1] |
5469513 |
1 |
|
|
T1 |
45073 |
|
T16 |
1578 |
|
T17 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2385663 |
1 |
|
|
T1 |
18114 |
|
T16 |
675 |
|
T17 |
24 |
| auto[1] |
auto[0] |
auto[1] |
351537 |
1 |
|
|
T1 |
3048 |
|
T16 |
165 |
|
T17 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2380285 |
1 |
|
|
T1 |
20481 |
|
T16 |
590 |
|
T17 |
6 |
| auto[1] |
auto[1] |
auto[1] |
352028 |
1 |
|
|
T1 |
3430 |
|
T16 |
148 |
|
T2 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7432790 |
1 |
|
|
T21 |
137 |
|
T1 |
55732 |
|
T11 |
421 |
| auto[1] |
5517821 |
1 |
|
|
T1 |
47884 |
|
T13 |
9 |
|
T16 |
1726 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12246193 |
1 |
|
|
T21 |
137 |
|
T1 |
96885 |
|
T11 |
421 |
| auto[1] |
704418 |
1 |
|
|
T1 |
6731 |
|
T16 |
278 |
|
T17 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7475773 |
1 |
|
|
T21 |
137 |
|
T1 |
56997 |
|
T11 |
421 |
| auto[1] |
5474838 |
1 |
|
|
T1 |
46619 |
|
T13 |
7 |
|
T16 |
1529 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2386697 |
1 |
|
|
T1 |
19812 |
|
T13 |
7 |
|
T16 |
534 |
| auto[1] |
auto[0] |
auto[1] |
351695 |
1 |
|
|
T1 |
3335 |
|
T16 |
110 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2383723 |
1 |
|
|
T1 |
20076 |
|
T16 |
717 |
|
T17 |
21 |
| auto[1] |
auto[1] |
auto[1] |
352723 |
1 |
|
|
T1 |
3396 |
|
T16 |
168 |
|
T17 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7455894 |
1 |
|
|
T21 |
137 |
|
T1 |
56744 |
|
T11 |
421 |
| auto[1] |
5494717 |
1 |
|
|
T1 |
46872 |
|
T13 |
12 |
|
T16 |
1464 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12236587 |
1 |
|
|
T21 |
137 |
|
T1 |
96932 |
|
T11 |
421 |
| auto[1] |
714024 |
1 |
|
|
T1 |
6684 |
|
T16 |
344 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7422860 |
1 |
|
|
T21 |
137 |
|
T1 |
56931 |
|
T11 |
421 |
| auto[1] |
5527751 |
1 |
|
|
T1 |
46685 |
|
T13 |
7 |
|
T16 |
1837 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2424236 |
1 |
|
|
T1 |
20501 |
|
T13 |
7 |
|
T16 |
836 |
| auto[1] |
auto[0] |
auto[1] |
359964 |
1 |
|
|
T1 |
3516 |
|
T16 |
200 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2389491 |
1 |
|
|
T1 |
19500 |
|
T16 |
657 |
|
T17 |
7 |
| auto[1] |
auto[1] |
auto[1] |
354060 |
1 |
|
|
T1 |
3168 |
|
T16 |
144 |
|
T2 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7470534 |
1 |
|
|
T21 |
137 |
|
T1 |
56990 |
|
T11 |
421 |
| auto[1] |
5480077 |
1 |
|
|
T1 |
46626 |
|
T13 |
9 |
|
T16 |
1550 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12239604 |
1 |
|
|
T21 |
137 |
|
T1 |
96797 |
|
T11 |
421 |
| auto[1] |
711007 |
1 |
|
|
T1 |
6819 |
|
T13 |
1 |
|
T16 |
363 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7448459 |
1 |
|
|
T21 |
137 |
|
T1 |
56473 |
|
T11 |
421 |
| auto[1] |
5502152 |
1 |
|
|
T1 |
47143 |
|
T13 |
13 |
|
T16 |
1918 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2399110 |
1 |
|
|
T1 |
20018 |
|
T13 |
12 |
|
T16 |
824 |
| auto[1] |
auto[0] |
auto[1] |
357143 |
1 |
|
|
T1 |
3318 |
|
T13 |
1 |
|
T16 |
189 |
| auto[1] |
auto[1] |
auto[0] |
2392035 |
1 |
|
|
T1 |
20306 |
|
T16 |
731 |
|
T17 |
13 |
| auto[1] |
auto[1] |
auto[1] |
353864 |
1 |
|
|
T1 |
3501 |
|
T16 |
174 |
|
T2 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445444 |
1 |
|
|
T21 |
137 |
|
T1 |
59220 |
|
T11 |
421 |
| auto[1] |
5505167 |
1 |
|
|
T1 |
44396 |
|
T13 |
12 |
|
T16 |
1313 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12242829 |
1 |
|
|
T21 |
137 |
|
T1 |
96905 |
|
T11 |
421 |
| auto[1] |
707782 |
1 |
|
|
T1 |
6711 |
|
T13 |
1 |
|
T16 |
278 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7462880 |
1 |
|
|
T21 |
137 |
|
T1 |
56888 |
|
T11 |
421 |
| auto[1] |
5487731 |
1 |
|
|
T1 |
46728 |
|
T13 |
6 |
|
T16 |
1514 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2398144 |
1 |
|
|
T1 |
21610 |
|
T13 |
5 |
|
T16 |
813 |
| auto[1] |
auto[0] |
auto[1] |
354588 |
1 |
|
|
T1 |
3626 |
|
T13 |
1 |
|
T16 |
182 |
| auto[1] |
auto[1] |
auto[0] |
2381805 |
1 |
|
|
T1 |
18407 |
|
T16 |
423 |
|
T17 |
12 |
| auto[1] |
auto[1] |
auto[1] |
353194 |
1 |
|
|
T1 |
3085 |
|
T16 |
96 |
|
T2 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7450211 |
1 |
|
|
T21 |
137 |
|
T1 |
56752 |
|
T11 |
421 |
| auto[1] |
5500400 |
1 |
|
|
T1 |
46864 |
|
T13 |
15 |
|
T16 |
1372 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12245985 |
1 |
|
|
T21 |
137 |
|
T1 |
96748 |
|
T11 |
421 |
| auto[1] |
704626 |
1 |
|
|
T1 |
6868 |
|
T16 |
291 |
|
T2 |
36 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7471230 |
1 |
|
|
T21 |
137 |
|
T1 |
56211 |
|
T11 |
421 |
| auto[1] |
5479381 |
1 |
|
|
T1 |
47405 |
|
T13 |
7 |
|
T16 |
1583 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2381575 |
1 |
|
|
T1 |
20310 |
|
T13 |
7 |
|
T16 |
724 |
| auto[1] |
auto[0] |
auto[1] |
351835 |
1 |
|
|
T1 |
3337 |
|
T16 |
161 |
|
T2 |
27 |
| auto[1] |
auto[1] |
auto[0] |
2393180 |
1 |
|
|
T1 |
20227 |
|
T16 |
568 |
|
T17 |
15 |
| auto[1] |
auto[1] |
auto[1] |
352791 |
1 |
|
|
T1 |
3531 |
|
T16 |
130 |
|
T2 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7417007 |
1 |
|
|
T21 |
137 |
|
T1 |
58299 |
|
T11 |
421 |
| auto[1] |
5533604 |
1 |
|
|
T1 |
45317 |
|
T13 |
3 |
|
T16 |
1684 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12240636 |
1 |
|
|
T21 |
137 |
|
T1 |
96985 |
|
T11 |
421 |
| auto[1] |
709975 |
1 |
|
|
T1 |
6631 |
|
T16 |
275 |
|
T2 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7438557 |
1 |
|
|
T21 |
137 |
|
T1 |
58543 |
|
T11 |
421 |
| auto[1] |
5512054 |
1 |
|
|
T1 |
45073 |
|
T13 |
13 |
|
T16 |
1450 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2386799 |
1 |
|
|
T1 |
19412 |
|
T13 |
13 |
|
T16 |
504 |
| auto[1] |
auto[0] |
auto[1] |
352407 |
1 |
|
|
T1 |
3380 |
|
T16 |
118 |
|
T2 |
21 |
| auto[1] |
auto[1] |
auto[0] |
2415280 |
1 |
|
|
T1 |
19030 |
|
T16 |
671 |
|
T17 |
10 |
| auto[1] |
auto[1] |
auto[1] |
357568 |
1 |
|
|
T1 |
3251 |
|
T16 |
157 |
|
T2 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7439294 |
1 |
|
|
T21 |
137 |
|
T1 |
57571 |
|
T11 |
421 |
| auto[1] |
5511317 |
1 |
|
|
T1 |
46045 |
|
T13 |
3 |
|
T16 |
1905 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12242293 |
1 |
|
|
T21 |
137 |
|
T1 |
96850 |
|
T11 |
421 |
| auto[1] |
708318 |
1 |
|
|
T1 |
6766 |
|
T16 |
372 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459584 |
1 |
|
|
T21 |
137 |
|
T1 |
56150 |
|
T11 |
421 |
| auto[1] |
5491027 |
1 |
|
|
T1 |
47466 |
|
T13 |
13 |
|
T16 |
1994 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2385987 |
1 |
|
|
T1 |
20620 |
|
T13 |
13 |
|
T16 |
773 |
| auto[1] |
auto[0] |
auto[1] |
352929 |
1 |
|
|
T1 |
3442 |
|
T16 |
187 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2396722 |
1 |
|
|
T1 |
20080 |
|
T16 |
849 |
|
T17 |
16 |
| auto[1] |
auto[1] |
auto[1] |
355389 |
1 |
|
|
T1 |
3324 |
|
T16 |
185 |
|
T2 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7472249 |
1 |
|
|
T21 |
137 |
|
T1 |
58247 |
|
T11 |
421 |
| auto[1] |
5478362 |
1 |
|
|
T1 |
45369 |
|
T13 |
6 |
|
T16 |
1888 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12244826 |
1 |
|
|
T21 |
137 |
|
T1 |
96999 |
|
T11 |
421 |
| auto[1] |
705785 |
1 |
|
|
T1 |
6617 |
|
T16 |
300 |
|
T17 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7465864 |
1 |
|
|
T21 |
137 |
|
T1 |
57712 |
|
T11 |
421 |
| auto[1] |
5484747 |
1 |
|
|
T1 |
45904 |
|
T16 |
1595 |
|
T17 |
52 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2417297 |
1 |
|
|
T1 |
20879 |
|
T16 |
558 |
|
T17 |
31 |
| auto[1] |
auto[0] |
auto[1] |
357306 |
1 |
|
|
T1 |
3594 |
|
T16 |
128 |
|
T17 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2361665 |
1 |
|
|
T1 |
18408 |
|
T16 |
737 |
|
T17 |
19 |
| auto[1] |
auto[1] |
auto[1] |
348479 |
1 |
|
|
T1 |
3023 |
|
T16 |
172 |
|
T2 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459579 |
1 |
|
|
T21 |
137 |
|
T1 |
56708 |
|
T11 |
421 |
| auto[1] |
5491032 |
1 |
|
|
T1 |
46908 |
|
T13 |
6 |
|
T16 |
1540 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12242135 |
1 |
|
|
T21 |
137 |
|
T1 |
96783 |
|
T11 |
421 |
| auto[1] |
708476 |
1 |
|
|
T1 |
6833 |
|
T13 |
1 |
|
T16 |
300 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7456609 |
1 |
|
|
T21 |
137 |
|
T1 |
56063 |
|
T11 |
421 |
| auto[1] |
5494002 |
1 |
|
|
T1 |
47553 |
|
T13 |
6 |
|
T16 |
1654 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2406369 |
1 |
|
|
T1 |
20201 |
|
T13 |
5 |
|
T16 |
758 |
| auto[1] |
auto[0] |
auto[1] |
356217 |
1 |
|
|
T1 |
3251 |
|
T13 |
1 |
|
T16 |
163 |
| auto[1] |
auto[1] |
auto[0] |
2379157 |
1 |
|
|
T1 |
20519 |
|
T16 |
596 |
|
T17 |
21 |
| auto[1] |
auto[1] |
auto[1] |
352259 |
1 |
|
|
T1 |
3582 |
|
T16 |
137 |
|
T2 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7479393 |
1 |
|
|
T21 |
137 |
|
T1 |
58198 |
|
T11 |
421 |
| auto[1] |
5471218 |
1 |
|
|
T1 |
45418 |
|
T13 |
3 |
|
T16 |
1859 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12237988 |
1 |
|
|
T21 |
137 |
|
T1 |
96732 |
|
T11 |
421 |
| auto[1] |
712623 |
1 |
|
|
T1 |
6884 |
|
T16 |
299 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7422613 |
1 |
|
|
T21 |
137 |
|
T1 |
55651 |
|
T11 |
421 |
| auto[1] |
5527998 |
1 |
|
|
T1 |
47965 |
|
T16 |
1703 |
|
T17 |
38 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2427432 |
1 |
|
|
T1 |
21696 |
|
T16 |
479 |
|
T17 |
35 |
| auto[1] |
auto[0] |
auto[1] |
359629 |
1 |
|
|
T1 |
3650 |
|
T16 |
110 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2387943 |
1 |
|
|
T1 |
19385 |
|
T16 |
925 |
|
T17 |
2 |
| auto[1] |
auto[1] |
auto[1] |
352994 |
1 |
|
|
T1 |
3234 |
|
T16 |
189 |
|
T2 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7439100 |
1 |
|
|
T21 |
137 |
|
T1 |
57394 |
|
T11 |
421 |
| auto[1] |
5511511 |
1 |
|
|
T1 |
46222 |
|
T16 |
1740 |
|
T17 |
56 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12235356 |
1 |
|
|
T21 |
137 |
|
T1 |
96629 |
|
T11 |
421 |
| auto[1] |
715255 |
1 |
|
|
T1 |
6987 |
|
T16 |
277 |
|
T2 |
41 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7413132 |
1 |
|
|
T21 |
137 |
|
T1 |
55803 |
|
T11 |
421 |
| auto[1] |
5537479 |
1 |
|
|
T1 |
47813 |
|
T13 |
7 |
|
T16 |
1501 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2415365 |
1 |
|
|
T1 |
20694 |
|
T13 |
7 |
|
T16 |
438 |
| auto[1] |
auto[0] |
auto[1] |
357905 |
1 |
|
|
T1 |
3609 |
|
T16 |
104 |
|
T2 |
22 |
| auto[1] |
auto[1] |
auto[0] |
2406859 |
1 |
|
|
T1 |
20132 |
|
T16 |
786 |
|
T17 |
14 |
| auto[1] |
auto[1] |
auto[1] |
357350 |
1 |
|
|
T1 |
3378 |
|
T16 |
173 |
|
T2 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7435091 |
1 |
|
|
T21 |
137 |
|
T1 |
55250 |
|
T11 |
421 |
| auto[1] |
5515520 |
1 |
|
|
T1 |
48366 |
|
T13 |
12 |
|
T16 |
1932 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12239198 |
1 |
|
|
T21 |
137 |
|
T1 |
97006 |
|
T11 |
421 |
| auto[1] |
711413 |
1 |
|
|
T1 |
6610 |
|
T13 |
1 |
|
T16 |
325 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7436988 |
1 |
|
|
T21 |
137 |
|
T1 |
57658 |
|
T11 |
421 |
| auto[1] |
5513623 |
1 |
|
|
T1 |
45958 |
|
T13 |
6 |
|
T16 |
1698 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2394820 |
1 |
|
|
T1 |
19080 |
|
T13 |
5 |
|
T16 |
522 |
| auto[1] |
auto[0] |
auto[1] |
353967 |
1 |
|
|
T1 |
3187 |
|
T13 |
1 |
|
T16 |
125 |
| auto[1] |
auto[1] |
auto[0] |
2407390 |
1 |
|
|
T1 |
20268 |
|
T16 |
851 |
|
T17 |
15 |
| auto[1] |
auto[1] |
auto[1] |
357446 |
1 |
|
|
T1 |
3423 |
|
T16 |
200 |
|
T2 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7441753 |
1 |
|
|
T21 |
137 |
|
T1 |
56305 |
|
T11 |
421 |
| auto[1] |
5508858 |
1 |
|
|
T1 |
47311 |
|
T13 |
9 |
|
T16 |
1381 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12242661 |
1 |
|
|
T21 |
137 |
|
T1 |
97121 |
|
T11 |
421 |
| auto[1] |
707950 |
1 |
|
|
T1 |
6495 |
|
T13 |
2 |
|
T16 |
344 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7461901 |
1 |
|
|
T21 |
137 |
|
T1 |
59001 |
|
T11 |
421 |
| auto[1] |
5488710 |
1 |
|
|
T1 |
44615 |
|
T13 |
6 |
|
T16 |
1863 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2405690 |
1 |
|
|
T1 |
19316 |
|
T13 |
4 |
|
T16 |
819 |
| auto[1] |
auto[0] |
auto[1] |
356435 |
1 |
|
|
T1 |
3418 |
|
T13 |
2 |
|
T16 |
179 |
| auto[1] |
auto[1] |
auto[0] |
2375070 |
1 |
|
|
T1 |
18804 |
|
T16 |
700 |
|
T17 |
14 |
| auto[1] |
auto[1] |
auto[1] |
351515 |
1 |
|
|
T1 |
3077 |
|
T16 |
165 |
|
T2 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447400 |
1 |
|
|
T21 |
137 |
|
T1 |
56356 |
|
T11 |
421 |
| auto[1] |
5503211 |
1 |
|
|
T1 |
47260 |
|
T16 |
1329 |
|
T17 |
34 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12241754 |
1 |
|
|
T21 |
137 |
|
T1 |
97151 |
|
T11 |
421 |
| auto[1] |
708857 |
1 |
|
|
T1 |
6465 |
|
T16 |
249 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7449800 |
1 |
|
|
T21 |
137 |
|
T1 |
58579 |
|
T11 |
421 |
| auto[1] |
5500811 |
1 |
|
|
T1 |
45037 |
|
T16 |
1277 |
|
T17 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2391589 |
1 |
|
|
T1 |
19187 |
|
T16 |
640 |
|
T17 |
9 |
| auto[1] |
auto[0] |
auto[1] |
353286 |
1 |
|
|
T1 |
3207 |
|
T16 |
161 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2400365 |
1 |
|
|
T1 |
19385 |
|
T16 |
388 |
|
T17 |
14 |
| auto[1] |
auto[1] |
auto[1] |
355571 |
1 |
|
|
T1 |
3258 |
|
T16 |
88 |
|
T2 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7466976 |
1 |
|
|
T21 |
137 |
|
T1 |
58171 |
|
T11 |
421 |
| auto[1] |
5483635 |
1 |
|
|
T1 |
45445 |
|
T13 |
6 |
|
T16 |
1745 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12248284 |
1 |
|
|
T21 |
137 |
|
T1 |
96748 |
|
T11 |
421 |
| auto[1] |
702327 |
1 |
|
|
T1 |
6868 |
|
T16 |
314 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7485673 |
1 |
|
|
T21 |
137 |
|
T1 |
56455 |
|
T11 |
421 |
| auto[1] |
5464938 |
1 |
|
|
T1 |
47161 |
|
T13 |
13 |
|
T16 |
1675 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2381496 |
1 |
|
|
T1 |
20448 |
|
T13 |
13 |
|
T16 |
710 |
| auto[1] |
auto[0] |
auto[1] |
350808 |
1 |
|
|
T1 |
3430 |
|
T16 |
170 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2381115 |
1 |
|
|
T1 |
19845 |
|
T16 |
651 |
|
T17 |
12 |
| auto[1] |
auto[1] |
auto[1] |
351519 |
1 |
|
|
T1 |
3438 |
|
T16 |
144 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7441323 |
1 |
|
|
T21 |
137 |
|
T1 |
55893 |
|
T11 |
421 |
| auto[1] |
5509288 |
1 |
|
|
T1 |
47723 |
|
T13 |
12 |
|
T16 |
1713 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12239172 |
1 |
|
|
T21 |
137 |
|
T1 |
97215 |
|
T11 |
421 |
| auto[1] |
711439 |
1 |
|
|
T1 |
6401 |
|
T16 |
363 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7434089 |
1 |
|
|
T21 |
137 |
|
T1 |
58690 |
|
T11 |
421 |
| auto[1] |
5516522 |
1 |
|
|
T1 |
44926 |
|
T16 |
1921 |
|
T17 |
65 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2397835 |
1 |
|
|
T1 |
18982 |
|
T16 |
768 |
|
T17 |
36 |
| auto[1] |
auto[0] |
auto[1] |
354154 |
1 |
|
|
T1 |
3095 |
|
T16 |
177 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2407248 |
1 |
|
|
T1 |
19543 |
|
T16 |
790 |
|
T17 |
28 |
| auto[1] |
auto[1] |
auto[1] |
357285 |
1 |
|
|
T1 |
3306 |
|
T16 |
186 |
|
T2 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7450229 |
1 |
|
|
T21 |
137 |
|
T1 |
55422 |
|
T11 |
421 |
| auto[1] |
5500382 |
1 |
|
|
T1 |
48194 |
|
T13 |
12 |
|
T16 |
1451 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12244471 |
1 |
|
|
T21 |
137 |
|
T1 |
96749 |
|
T11 |
421 |
| auto[1] |
706140 |
1 |
|
|
T1 |
6867 |
|
T13 |
1 |
|
T16 |
306 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7470358 |
1 |
|
|
T21 |
137 |
|
T1 |
55566 |
|
T11 |
421 |
| auto[1] |
5480253 |
1 |
|
|
T1 |
48050 |
|
T13 |
13 |
|
T16 |
1490 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2394091 |
1 |
|
|
T1 |
20042 |
|
T13 |
12 |
|
T16 |
601 |
| auto[1] |
auto[0] |
auto[1] |
354012 |
1 |
|
|
T1 |
3332 |
|
T13 |
1 |
|
T16 |
160 |
| auto[1] |
auto[1] |
auto[0] |
2380022 |
1 |
|
|
T1 |
21141 |
|
T16 |
583 |
|
T17 |
24 |
| auto[1] |
auto[1] |
auto[1] |
352128 |
1 |
|
|
T1 |
3535 |
|
T16 |
146 |
|
T2 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7436469 |
1 |
|
|
T21 |
137 |
|
T1 |
55878 |
|
T11 |
421 |
| auto[1] |
5514142 |
1 |
|
|
T1 |
47738 |
|
T13 |
6 |
|
T16 |
1295 |