Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7451834 |
1 |
|
|
T21 |
137 |
|
T1 |
58104 |
|
T11 |
421 |
| auto[1] |
5498777 |
1 |
|
|
T1 |
45512 |
|
T13 |
6 |
|
T16 |
1662 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12244240 |
1 |
|
|
T21 |
137 |
|
T1 |
97084 |
|
T11 |
421 |
| auto[1] |
706371 |
1 |
|
|
T1 |
6532 |
|
T16 |
263 |
|
T2 |
27 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7458013 |
1 |
|
|
T21 |
137 |
|
T1 |
58296 |
|
T11 |
421 |
| auto[1] |
5492598 |
1 |
|
|
T1 |
45320 |
|
T16 |
1374 |
|
T17 |
40 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2403722 |
1 |
|
|
T1 |
19768 |
|
T16 |
521 |
|
T17 |
33 |
| auto[1] |
auto[0] |
auto[1] |
354559 |
1 |
|
|
T1 |
3297 |
|
T16 |
115 |
|
T2 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2382505 |
1 |
|
|
T1 |
19020 |
|
T16 |
590 |
|
T17 |
7 |
| auto[1] |
auto[1] |
auto[1] |
351812 |
1 |
|
|
T1 |
3235 |
|
T16 |
148 |
|
T2 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |