Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7472936 |
1 |
|
|
T21 |
137 |
|
T1 |
56627 |
|
T11 |
421 |
| auto[1] |
5477675 |
1 |
|
|
T1 |
46989 |
|
T13 |
9 |
|
T16 |
1641 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12236973 |
1 |
|
|
T21 |
137 |
|
T1 |
96969 |
|
T11 |
421 |
| auto[1] |
713638 |
1 |
|
|
T1 |
6647 |
|
T16 |
294 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7417557 |
1 |
|
|
T21 |
137 |
|
T1 |
57263 |
|
T11 |
421 |
| auto[1] |
5533054 |
1 |
|
|
T1 |
46353 |
|
T16 |
1608 |
|
T17 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2416535 |
1 |
|
|
T1 |
20113 |
|
T16 |
683 |
|
T17 |
19 |
| auto[1] |
auto[0] |
auto[1] |
357467 |
1 |
|
|
T1 |
3255 |
|
T16 |
159 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2402881 |
1 |
|
|
T1 |
19593 |
|
T16 |
631 |
|
T17 |
16 |
| auto[1] |
auto[1] |
auto[1] |
356171 |
1 |
|
|
T1 |
3392 |
|
T16 |
135 |
|
T2 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |