Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7406992 |
1 |
|
|
T21 |
137 |
|
T1 |
55764 |
|
T11 |
421 |
| auto[1] |
5543619 |
1 |
|
|
T1 |
47852 |
|
T13 |
12 |
|
T16 |
1600 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12242817 |
1 |
|
|
T21 |
137 |
|
T1 |
97260 |
|
T11 |
421 |
| auto[1] |
707794 |
1 |
|
|
T1 |
6356 |
|
T13 |
1 |
|
T16 |
273 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7446740 |
1 |
|
|
T21 |
137 |
|
T1 |
58717 |
|
T11 |
421 |
| auto[1] |
5503871 |
1 |
|
|
T1 |
44899 |
|
T13 |
13 |
|
T16 |
1441 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2384126 |
1 |
|
|
T1 |
19422 |
|
T13 |
12 |
|
T16 |
634 |
| auto[1] |
auto[0] |
auto[1] |
351964 |
1 |
|
|
T1 |
3148 |
|
T13 |
1 |
|
T16 |
148 |
| auto[1] |
auto[1] |
auto[0] |
2411951 |
1 |
|
|
T1 |
19121 |
|
T16 |
534 |
|
T17 |
11 |
| auto[1] |
auto[1] |
auto[1] |
355830 |
1 |
|
|
T1 |
3208 |
|
T16 |
125 |
|
T2 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |