Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7484422 |
1 |
|
|
T21 |
137 |
|
T1 |
55635 |
|
T11 |
421 |
| auto[1] |
5466189 |
1 |
|
|
T1 |
47981 |
|
T13 |
9 |
|
T16 |
1452 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12242685 |
1 |
|
|
T21 |
137 |
|
T1 |
96900 |
|
T11 |
421 |
| auto[1] |
707926 |
1 |
|
|
T1 |
6716 |
|
T16 |
342 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7454096 |
1 |
|
|
T21 |
137 |
|
T1 |
56499 |
|
T11 |
421 |
| auto[1] |
5496515 |
1 |
|
|
T1 |
47117 |
|
T16 |
1740 |
|
T17 |
44 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2425747 |
1 |
|
|
T1 |
20219 |
|
T16 |
843 |
|
T17 |
21 |
| auto[1] |
auto[0] |
auto[1] |
359262 |
1 |
|
|
T1 |
3266 |
|
T16 |
201 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2362842 |
1 |
|
|
T1 |
20182 |
|
T16 |
555 |
|
T17 |
22 |
| auto[1] |
auto[1] |
auto[1] |
348664 |
1 |
|
|
T1 |
3450 |
|
T16 |
141 |
|
T2 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |