Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7463581 |
1 |
|
|
T21 |
137 |
|
T1 |
58303 |
|
T11 |
421 |
| auto[1] |
5487030 |
1 |
|
|
T1 |
45313 |
|
T16 |
1653 |
|
T17 |
52 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12240892 |
1 |
|
|
T21 |
137 |
|
T1 |
96959 |
|
T11 |
421 |
| auto[1] |
709719 |
1 |
|
|
T1 |
6657 |
|
T16 |
349 |
|
T2 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447078 |
1 |
|
|
T21 |
137 |
|
T1 |
57641 |
|
T11 |
421 |
| auto[1] |
5503533 |
1 |
|
|
T1 |
45975 |
|
T16 |
1881 |
|
T17 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2410199 |
1 |
|
|
T1 |
20386 |
|
T16 |
819 |
|
T17 |
4 |
| auto[1] |
auto[0] |
auto[1] |
357534 |
1 |
|
|
T1 |
3516 |
|
T16 |
176 |
|
T2 |
19 |
| auto[1] |
auto[1] |
auto[0] |
2383615 |
1 |
|
|
T1 |
18932 |
|
T16 |
713 |
|
T17 |
19 |
| auto[1] |
auto[1] |
auto[1] |
352185 |
1 |
|
|
T1 |
3141 |
|
T16 |
173 |
|
T2 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |