Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459835 |
1 |
|
|
T21 |
137 |
|
T1 |
57962 |
|
T11 |
421 |
| auto[1] |
5490776 |
1 |
|
|
T1 |
45654 |
|
T16 |
1442 |
|
T17 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10666820 |
1 |
|
|
T21 |
137 |
|
T1 |
75739 |
|
T11 |
421 |
| auto[1] |
2283791 |
1 |
|
|
T1 |
27877 |
|
T13 |
8 |
|
T16 |
627 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445359 |
1 |
|
|
T21 |
137 |
|
T1 |
56614 |
|
T11 |
421 |
| auto[1] |
5505252 |
1 |
|
|
T1 |
47002 |
|
T13 |
8 |
|
T16 |
1258 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1618726 |
1 |
|
|
T1 |
9823 |
|
T16 |
370 |
|
T17 |
19 |
| auto[1] |
auto[0] |
auto[1] |
1145545 |
1 |
|
|
T1 |
13909 |
|
T13 |
8 |
|
T16 |
378 |
| auto[1] |
auto[1] |
auto[0] |
1602735 |
1 |
|
|
T1 |
9302 |
|
T16 |
261 |
|
T17 |
5 |
| auto[1] |
auto[1] |
auto[1] |
1138246 |
1 |
|
|
T1 |
13968 |
|
T16 |
249 |
|
T17 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |