Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445873 |
1 |
|
|
T21 |
137 |
|
T1 |
54223 |
|
T11 |
421 |
| auto[1] |
5504738 |
1 |
|
|
T1 |
49393 |
|
T13 |
12 |
|
T16 |
1644 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10673259 |
1 |
|
|
T21 |
137 |
|
T1 |
75059 |
|
T11 |
421 |
| auto[1] |
2277352 |
1 |
|
|
T1 |
28557 |
|
T16 |
768 |
|
T17 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445344 |
1 |
|
|
T21 |
137 |
|
T1 |
55235 |
|
T11 |
421 |
| auto[1] |
5505267 |
1 |
|
|
T1 |
48381 |
|
T16 |
1603 |
|
T17 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1612256 |
1 |
|
|
T1 |
9365 |
|
T16 |
493 |
|
T17 |
7 |
| auto[1] |
auto[0] |
auto[1] |
1138961 |
1 |
|
|
T1 |
12980 |
|
T16 |
420 |
|
T17 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1615659 |
1 |
|
|
T1 |
10459 |
|
T16 |
342 |
|
T17 |
13 |
| auto[1] |
auto[1] |
auto[1] |
1138391 |
1 |
|
|
T1 |
15577 |
|
T16 |
348 |
|
T2 |
71 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |