Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7432790 |
1 |
|
|
T21 |
137 |
|
T1 |
55732 |
|
T11 |
421 |
| auto[1] |
5517821 |
1 |
|
|
T1 |
47884 |
|
T13 |
9 |
|
T16 |
1726 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10662511 |
1 |
|
|
T21 |
137 |
|
T1 |
76166 |
|
T11 |
421 |
| auto[1] |
2288100 |
1 |
|
|
T1 |
27450 |
|
T13 |
9 |
|
T16 |
794 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7435992 |
1 |
|
|
T21 |
137 |
|
T1 |
57304 |
|
T11 |
421 |
| auto[1] |
5514619 |
1 |
|
|
T1 |
46312 |
|
T13 |
14 |
|
T16 |
1656 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1611405 |
1 |
|
|
T1 |
9825 |
|
T13 |
1 |
|
T16 |
349 |
| auto[1] |
auto[0] |
auto[1] |
1143092 |
1 |
|
|
T1 |
13840 |
|
T13 |
4 |
|
T16 |
315 |
| auto[1] |
auto[1] |
auto[0] |
1615114 |
1 |
|
|
T1 |
9037 |
|
T13 |
4 |
|
T16 |
513 |
| auto[1] |
auto[1] |
auto[1] |
1145008 |
1 |
|
|
T1 |
13610 |
|
T13 |
5 |
|
T16 |
479 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |