Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7455894 |
1 |
|
|
T21 |
137 |
|
T1 |
56744 |
|
T11 |
421 |
| auto[1] |
5494717 |
1 |
|
|
T1 |
46872 |
|
T13 |
12 |
|
T16 |
1464 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10669593 |
1 |
|
|
T21 |
137 |
|
T1 |
75303 |
|
T11 |
421 |
| auto[1] |
2281018 |
1 |
|
|
T1 |
28313 |
|
T13 |
10 |
|
T16 |
960 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7455578 |
1 |
|
|
T21 |
137 |
|
T1 |
55872 |
|
T11 |
421 |
| auto[1] |
5495033 |
1 |
|
|
T1 |
47744 |
|
T13 |
19 |
|
T16 |
1892 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1610799 |
1 |
|
|
T1 |
9829 |
|
T13 |
5 |
|
T16 |
562 |
| auto[1] |
auto[0] |
auto[1] |
1146414 |
1 |
|
|
T1 |
13622 |
|
T13 |
2 |
|
T16 |
592 |
| auto[1] |
auto[1] |
auto[0] |
1603216 |
1 |
|
|
T1 |
9602 |
|
T13 |
4 |
|
T16 |
370 |
| auto[1] |
auto[1] |
auto[1] |
1134604 |
1 |
|
|
T1 |
14691 |
|
T13 |
8 |
|
T16 |
368 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |