Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7470534 |
1 |
|
|
T21 |
137 |
|
T1 |
56990 |
|
T11 |
421 |
| auto[1] |
5480077 |
1 |
|
|
T1 |
46626 |
|
T13 |
9 |
|
T16 |
1550 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10679218 |
1 |
|
|
T21 |
137 |
|
T1 |
75257 |
|
T11 |
421 |
| auto[1] |
2271393 |
1 |
|
|
T1 |
28359 |
|
T16 |
723 |
|
T17 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7473899 |
1 |
|
|
T21 |
137 |
|
T1 |
54777 |
|
T11 |
421 |
| auto[1] |
5476712 |
1 |
|
|
T1 |
48839 |
|
T13 |
12 |
|
T16 |
1493 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1608197 |
1 |
|
|
T1 |
10566 |
|
T13 |
10 |
|
T16 |
462 |
| auto[1] |
auto[0] |
auto[1] |
1144357 |
1 |
|
|
T1 |
15087 |
|
T16 |
460 |
|
T17 |
12 |
| auto[1] |
auto[1] |
auto[0] |
1597122 |
1 |
|
|
T1 |
9914 |
|
T13 |
2 |
|
T16 |
308 |
| auto[1] |
auto[1] |
auto[1] |
1127036 |
1 |
|
|
T1 |
13272 |
|
T16 |
263 |
|
T17 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |