Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12241624 |
1 |
|
|
T21 |
137 |
|
T1 |
96964 |
|
T11 |
421 |
| auto[1] |
708987 |
1 |
|
|
T1 |
6652 |
|
T16 |
289 |
|
T17 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7450138 |
1 |
|
|
T21 |
137 |
|
T1 |
58462 |
|
T11 |
421 |
| auto[1] |
5500473 |
1 |
|
|
T1 |
45154 |
|
T13 |
7 |
|
T16 |
1518 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2388938 |
1 |
|
|
T1 |
19295 |
|
T13 |
7 |
|
T16 |
700 |
| auto[1] |
auto[0] |
auto[1] |
353147 |
1 |
|
|
T1 |
3316 |
|
T16 |
169 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2402548 |
1 |
|
|
T1 |
19207 |
|
T16 |
529 |
|
T17 |
33 |
| auto[1] |
auto[1] |
auto[1] |
355840 |
1 |
|
|
T1 |
3336 |
|
T16 |
120 |
|
T17 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |