Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445444 |
1 |
|
|
T21 |
137 |
|
T1 |
59220 |
|
T11 |
421 |
| auto[1] |
5505167 |
1 |
|
|
T1 |
44396 |
|
T13 |
12 |
|
T16 |
1313 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10676463 |
1 |
|
|
T21 |
137 |
|
T1 |
77569 |
|
T11 |
421 |
| auto[1] |
2274148 |
1 |
|
|
T1 |
26047 |
|
T16 |
836 |
|
T17 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7453389 |
1 |
|
|
T21 |
137 |
|
T1 |
58868 |
|
T11 |
421 |
| auto[1] |
5497222 |
1 |
|
|
T1 |
44748 |
|
T13 |
7 |
|
T16 |
1664 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1615588 |
1 |
|
|
T1 |
9836 |
|
T13 |
5 |
|
T16 |
523 |
| auto[1] |
auto[0] |
auto[1] |
1139808 |
1 |
|
|
T1 |
13949 |
|
T16 |
539 |
|
T17 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1607486 |
1 |
|
|
T1 |
8865 |
|
T13 |
2 |
|
T16 |
305 |
| auto[1] |
auto[1] |
auto[1] |
1134340 |
1 |
|
|
T1 |
12098 |
|
T16 |
297 |
|
T17 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |