Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7450211 |
1 |
|
|
T21 |
137 |
|
T1 |
56752 |
|
T11 |
421 |
| auto[1] |
5500400 |
1 |
|
|
T1 |
46864 |
|
T13 |
15 |
|
T16 |
1372 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10658342 |
1 |
|
|
T21 |
137 |
|
T1 |
76627 |
|
T11 |
421 |
| auto[1] |
2292269 |
1 |
|
|
T1 |
26989 |
|
T13 |
7 |
|
T16 |
813 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7428637 |
1 |
|
|
T21 |
137 |
|
T1 |
57790 |
|
T11 |
421 |
| auto[1] |
5521974 |
1 |
|
|
T1 |
45826 |
|
T13 |
11 |
|
T16 |
1635 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1614518 |
1 |
|
|
T1 |
9263 |
|
T13 |
1 |
|
T16 |
503 |
| auto[1] |
auto[0] |
auto[1] |
1151941 |
1 |
|
|
T1 |
13384 |
|
T13 |
1 |
|
T16 |
520 |
| auto[1] |
auto[1] |
auto[0] |
1615187 |
1 |
|
|
T1 |
9574 |
|
T13 |
3 |
|
T16 |
319 |
| auto[1] |
auto[1] |
auto[1] |
1140328 |
1 |
|
|
T1 |
13605 |
|
T13 |
6 |
|
T16 |
293 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |