Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7417007 |
1 |
|
|
T21 |
137 |
|
T1 |
58299 |
|
T11 |
421 |
| auto[1] |
5533604 |
1 |
|
|
T1 |
45317 |
|
T13 |
3 |
|
T16 |
1684 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10683697 |
1 |
|
|
T21 |
137 |
|
T1 |
75209 |
|
T11 |
421 |
| auto[1] |
2266914 |
1 |
|
|
T1 |
28407 |
|
T13 |
1 |
|
T16 |
735 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7497310 |
1 |
|
|
T21 |
137 |
|
T1 |
55029 |
|
T11 |
421 |
| auto[1] |
5453301 |
1 |
|
|
T1 |
48587 |
|
T13 |
4 |
|
T16 |
1595 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1581045 |
1 |
|
|
T1 |
10442 |
|
T13 |
3 |
|
T16 |
436 |
| auto[1] |
auto[0] |
auto[1] |
1131566 |
1 |
|
|
T1 |
14975 |
|
T13 |
1 |
|
T16 |
366 |
| auto[1] |
auto[1] |
auto[0] |
1605342 |
1 |
|
|
T1 |
9738 |
|
T16 |
424 |
|
T17 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1135348 |
1 |
|
|
T1 |
13432 |
|
T16 |
369 |
|
T17 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |