Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7439294 |
1 |
|
|
T21 |
137 |
|
T1 |
57571 |
|
T11 |
421 |
| auto[1] |
5511317 |
1 |
|
|
T1 |
46045 |
|
T13 |
3 |
|
T16 |
1905 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10668742 |
1 |
|
|
T21 |
137 |
|
T1 |
76804 |
|
T11 |
421 |
| auto[1] |
2281869 |
1 |
|
|
T1 |
26812 |
|
T13 |
1 |
|
T16 |
1086 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7446428 |
1 |
|
|
T21 |
137 |
|
T1 |
58011 |
|
T11 |
421 |
| auto[1] |
5504183 |
1 |
|
|
T1 |
45605 |
|
T13 |
11 |
|
T16 |
2073 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1604661 |
1 |
|
|
T1 |
9479 |
|
T13 |
10 |
|
T16 |
399 |
| auto[1] |
auto[0] |
auto[1] |
1133975 |
1 |
|
|
T1 |
13520 |
|
T13 |
1 |
|
T16 |
419 |
| auto[1] |
auto[1] |
auto[0] |
1617653 |
1 |
|
|
T1 |
9314 |
|
T16 |
588 |
|
T17 |
29 |
| auto[1] |
auto[1] |
auto[1] |
1147894 |
1 |
|
|
T1 |
13292 |
|
T16 |
667 |
|
T17 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |