Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7472249 |
1 |
|
|
T21 |
137 |
|
T1 |
58247 |
|
T11 |
421 |
| auto[1] |
5478362 |
1 |
|
|
T1 |
45369 |
|
T13 |
6 |
|
T16 |
1888 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10667014 |
1 |
|
|
T21 |
137 |
|
T1 |
75397 |
|
T11 |
421 |
| auto[1] |
2283597 |
1 |
|
|
T1 |
28219 |
|
T16 |
864 |
|
T17 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7439658 |
1 |
|
|
T21 |
137 |
|
T1 |
55505 |
|
T11 |
421 |
| auto[1] |
5510953 |
1 |
|
|
T1 |
48111 |
|
T16 |
1804 |
|
T17 |
46 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1621817 |
1 |
|
|
T1 |
10035 |
|
T16 |
321 |
|
T17 |
22 |
| auto[1] |
auto[0] |
auto[1] |
1150571 |
1 |
|
|
T1 |
13981 |
|
T16 |
310 |
|
T17 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1605539 |
1 |
|
|
T1 |
9857 |
|
T16 |
619 |
|
T17 |
11 |
| auto[1] |
auto[1] |
auto[1] |
1133026 |
1 |
|
|
T1 |
14238 |
|
T16 |
554 |
|
T17 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |