Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459579 |
1 |
|
|
T21 |
137 |
|
T1 |
56708 |
|
T11 |
421 |
| auto[1] |
5491032 |
1 |
|
|
T1 |
46908 |
|
T13 |
6 |
|
T16 |
1540 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10684062 |
1 |
|
|
T21 |
137 |
|
T1 |
76402 |
|
T11 |
421 |
| auto[1] |
2266549 |
1 |
|
|
T1 |
27214 |
|
T13 |
13 |
|
T16 |
802 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7488404 |
1 |
|
|
T21 |
137 |
|
T1 |
57228 |
|
T11 |
421 |
| auto[1] |
5462207 |
1 |
|
|
T1 |
46388 |
|
T13 |
16 |
|
T16 |
1677 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1600865 |
1 |
|
|
T1 |
9604 |
|
T13 |
3 |
|
T16 |
389 |
| auto[1] |
auto[0] |
auto[1] |
1134099 |
1 |
|
|
T1 |
13040 |
|
T13 |
10 |
|
T16 |
365 |
| auto[1] |
auto[1] |
auto[0] |
1594793 |
1 |
|
|
T1 |
9570 |
|
T16 |
486 |
|
T17 |
17 |
| auto[1] |
auto[1] |
auto[1] |
1132450 |
1 |
|
|
T1 |
14174 |
|
T13 |
3 |
|
T16 |
437 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |