Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7479393 |
1 |
|
|
T21 |
137 |
|
T1 |
58198 |
|
T11 |
421 |
| auto[1] |
5471218 |
1 |
|
|
T1 |
45418 |
|
T13 |
3 |
|
T16 |
1859 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10666060 |
1 |
|
|
T21 |
137 |
|
T1 |
76340 |
|
T11 |
421 |
| auto[1] |
2284551 |
1 |
|
|
T1 |
27276 |
|
T13 |
10 |
|
T16 |
682 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7442783 |
1 |
|
|
T21 |
137 |
|
T1 |
56859 |
|
T11 |
421 |
| auto[1] |
5507828 |
1 |
|
|
T1 |
46757 |
|
T13 |
14 |
|
T16 |
1364 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1619006 |
1 |
|
|
T1 |
9748 |
|
T13 |
4 |
|
T16 |
244 |
| auto[1] |
auto[0] |
auto[1] |
1145147 |
1 |
|
|
T1 |
13649 |
|
T13 |
10 |
|
T16 |
247 |
| auto[1] |
auto[1] |
auto[0] |
1604271 |
1 |
|
|
T1 |
9733 |
|
T16 |
438 |
|
T17 |
11 |
| auto[1] |
auto[1] |
auto[1] |
1139404 |
1 |
|
|
T1 |
13627 |
|
T16 |
435 |
|
T17 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |