Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7435091 |
1 |
|
|
T21 |
137 |
|
T1 |
55250 |
|
T11 |
421 |
| auto[1] |
5515520 |
1 |
|
|
T1 |
48366 |
|
T13 |
12 |
|
T16 |
1932 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10672519 |
1 |
|
|
T21 |
137 |
|
T1 |
76802 |
|
T11 |
421 |
| auto[1] |
2278092 |
1 |
|
|
T1 |
26814 |
|
T13 |
1 |
|
T16 |
704 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7449828 |
1 |
|
|
T21 |
137 |
|
T1 |
58029 |
|
T11 |
421 |
| auto[1] |
5500783 |
1 |
|
|
T1 |
45587 |
|
T13 |
8 |
|
T16 |
1429 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1612345 |
1 |
|
|
T1 |
9080 |
|
T13 |
5 |
|
T16 |
335 |
| auto[1] |
auto[0] |
auto[1] |
1139060 |
1 |
|
|
T1 |
12998 |
|
T16 |
335 |
|
T17 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1610346 |
1 |
|
|
T1 |
9693 |
|
T13 |
2 |
|
T16 |
390 |
| auto[1] |
auto[1] |
auto[1] |
1139032 |
1 |
|
|
T1 |
13816 |
|
T13 |
1 |
|
T16 |
369 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |