Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7441753 |
1 |
|
|
T21 |
137 |
|
T1 |
56305 |
|
T11 |
421 |
| auto[1] |
5508858 |
1 |
|
|
T1 |
47311 |
|
T13 |
9 |
|
T16 |
1381 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10671498 |
1 |
|
|
T21 |
137 |
|
T1 |
75565 |
|
T11 |
421 |
| auto[1] |
2279113 |
1 |
|
|
T1 |
28051 |
|
T13 |
3 |
|
T16 |
534 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459921 |
1 |
|
|
T21 |
137 |
|
T1 |
56292 |
|
T11 |
421 |
| auto[1] |
5490690 |
1 |
|
|
T1 |
47324 |
|
T13 |
4 |
|
T16 |
1107 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1599865 |
1 |
|
|
T1 |
9789 |
|
T16 |
320 |
|
T17 |
13 |
| auto[1] |
auto[0] |
auto[1] |
1137910 |
1 |
|
|
T1 |
13533 |
|
T16 |
294 |
|
T17 |
29 |
| auto[1] |
auto[1] |
auto[0] |
1611712 |
1 |
|
|
T1 |
9484 |
|
T13 |
1 |
|
T16 |
253 |
| auto[1] |
auto[1] |
auto[1] |
1141203 |
1 |
|
|
T1 |
14518 |
|
T13 |
3 |
|
T16 |
240 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |