Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7448376 |
1 |
|
|
T21 |
137 |
|
T1 |
53917 |
|
T11 |
421 |
| auto[1] |
5502235 |
1 |
|
|
T1 |
49699 |
|
T13 |
6 |
|
T16 |
1731 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12249847 |
1 |
|
|
T21 |
137 |
|
T1 |
97025 |
|
T11 |
421 |
| auto[1] |
700764 |
1 |
|
|
T1 |
6591 |
|
T16 |
277 |
|
T17 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7492165 |
1 |
|
|
T21 |
137 |
|
T1 |
57511 |
|
T11 |
421 |
| auto[1] |
5458446 |
1 |
|
|
T1 |
46105 |
|
T13 |
7 |
|
T16 |
1503 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2385935 |
1 |
|
|
T1 |
18686 |
|
T13 |
7 |
|
T16 |
614 |
| auto[1] |
auto[0] |
auto[1] |
351702 |
1 |
|
|
T1 |
3041 |
|
T16 |
141 |
|
T17 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2371747 |
1 |
|
|
T1 |
20828 |
|
T16 |
612 |
|
T17 |
6 |
| auto[1] |
auto[1] |
auto[1] |
349062 |
1 |
|
|
T1 |
3550 |
|
T16 |
136 |
|
T2 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |