Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7466976 |
1 |
|
|
T21 |
137 |
|
T1 |
58171 |
|
T11 |
421 |
| auto[1] |
5483635 |
1 |
|
|
T1 |
45445 |
|
T13 |
6 |
|
T16 |
1745 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10661123 |
1 |
|
|
T21 |
137 |
|
T1 |
77427 |
|
T11 |
421 |
| auto[1] |
2289488 |
1 |
|
|
T1 |
26189 |
|
T13 |
11 |
|
T16 |
679 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7423967 |
1 |
|
|
T21 |
137 |
|
T1 |
58490 |
|
T11 |
421 |
| auto[1] |
5526644 |
1 |
|
|
T1 |
45126 |
|
T13 |
16 |
|
T16 |
1333 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1622312 |
1 |
|
|
T1 |
9715 |
|
T13 |
5 |
|
T16 |
304 |
| auto[1] |
auto[0] |
auto[1] |
1143948 |
1 |
|
|
T1 |
13679 |
|
T13 |
8 |
|
T16 |
343 |
| auto[1] |
auto[1] |
auto[0] |
1614844 |
1 |
|
|
T1 |
9222 |
|
T16 |
350 |
|
T17 |
17 |
| auto[1] |
auto[1] |
auto[1] |
1145540 |
1 |
|
|
T1 |
12510 |
|
T13 |
3 |
|
T16 |
336 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |