Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7441323 |
1 |
|
|
T21 |
137 |
|
T1 |
55893 |
|
T11 |
421 |
| auto[1] |
5509288 |
1 |
|
|
T1 |
47723 |
|
T13 |
12 |
|
T16 |
1713 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10661310 |
1 |
|
|
T21 |
137 |
|
T1 |
76884 |
|
T11 |
421 |
| auto[1] |
2289301 |
1 |
|
|
T1 |
26732 |
|
T13 |
3 |
|
T16 |
836 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7425460 |
1 |
|
|
T21 |
137 |
|
T1 |
57521 |
|
T11 |
421 |
| auto[1] |
5525151 |
1 |
|
|
T1 |
46095 |
|
T13 |
11 |
|
T16 |
1705 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1612773 |
1 |
|
|
T1 |
9786 |
|
T13 |
2 |
|
T16 |
352 |
| auto[1] |
auto[0] |
auto[1] |
1139133 |
1 |
|
|
T1 |
13652 |
|
T16 |
364 |
|
T17 |
25 |
| auto[1] |
auto[1] |
auto[0] |
1623077 |
1 |
|
|
T1 |
9577 |
|
T13 |
6 |
|
T16 |
517 |
| auto[1] |
auto[1] |
auto[1] |
1150168 |
1 |
|
|
T1 |
13080 |
|
T13 |
3 |
|
T16 |
472 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |