Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7425276 |
1 |
|
|
T21 |
137 |
|
T1 |
58947 |
|
T11 |
421 |
| auto[1] |
5525335 |
1 |
|
|
T1 |
44669 |
|
T16 |
1814 |
|
T17 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12239760 |
1 |
|
|
T21 |
137 |
|
T1 |
96947 |
|
T11 |
421 |
| auto[1] |
710851 |
1 |
|
|
T1 |
6669 |
|
T13 |
1 |
|
T16 |
298 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7432425 |
1 |
|
|
T21 |
137 |
|
T1 |
57368 |
|
T11 |
421 |
| auto[1] |
5518186 |
1 |
|
|
T1 |
46248 |
|
T13 |
13 |
|
T16 |
1518 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2390956 |
1 |
|
|
T1 |
21214 |
|
T13 |
12 |
|
T16 |
405 |
| auto[1] |
auto[0] |
auto[1] |
353001 |
1 |
|
|
T1 |
3584 |
|
T13 |
1 |
|
T16 |
99 |
| auto[1] |
auto[1] |
auto[0] |
2416379 |
1 |
|
|
T1 |
18365 |
|
T16 |
815 |
|
T17 |
19 |
| auto[1] |
auto[1] |
auto[1] |
357850 |
1 |
|
|
T1 |
3085 |
|
T16 |
199 |
|
T2 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |