Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7452787 |
1 |
|
|
T21 |
137 |
|
T1 |
56160 |
|
T11 |
421 |
| auto[1] |
5497824 |
1 |
|
|
T1 |
47456 |
|
T13 |
6 |
|
T16 |
1738 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12240363 |
1 |
|
|
T21 |
137 |
|
T1 |
97060 |
|
T11 |
421 |
| auto[1] |
710248 |
1 |
|
|
T1 |
6556 |
|
T16 |
312 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7443184 |
1 |
|
|
T21 |
137 |
|
T1 |
58050 |
|
T11 |
421 |
| auto[1] |
5507427 |
1 |
|
|
T1 |
45566 |
|
T13 |
7 |
|
T16 |
1564 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2403045 |
1 |
|
|
T1 |
18711 |
|
T13 |
7 |
|
T16 |
579 |
| auto[1] |
auto[0] |
auto[1] |
355250 |
1 |
|
|
T1 |
3127 |
|
T16 |
157 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2394134 |
1 |
|
|
T1 |
20299 |
|
T16 |
673 |
|
T17 |
9 |
| auto[1] |
auto[1] |
auto[1] |
354998 |
1 |
|
|
T1 |
3429 |
|
T16 |
155 |
|
T2 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |