Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7451240 |
1 |
|
|
T21 |
137 |
|
T1 |
57602 |
|
T11 |
421 |
| auto[1] |
5499371 |
1 |
|
|
T1 |
46014 |
|
T16 |
1248 |
|
T17 |
35 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12239488 |
1 |
|
|
T21 |
137 |
|
T1 |
97019 |
|
T11 |
421 |
| auto[1] |
711123 |
1 |
|
|
T1 |
6597 |
|
T16 |
270 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7430952 |
1 |
|
|
T21 |
137 |
|
T1 |
57408 |
|
T11 |
421 |
| auto[1] |
5519659 |
1 |
|
|
T1 |
46208 |
|
T16 |
1345 |
|
T17 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2398278 |
1 |
|
|
T1 |
20436 |
|
T16 |
671 |
|
T17 |
20 |
| auto[1] |
auto[0] |
auto[1] |
353860 |
1 |
|
|
T1 |
3399 |
|
T16 |
179 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2410258 |
1 |
|
|
T1 |
19175 |
|
T16 |
404 |
|
T17 |
11 |
| auto[1] |
auto[1] |
auto[1] |
357263 |
1 |
|
|
T1 |
3198 |
|
T16 |
91 |
|
T2 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |