Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7479327 |
1 |
|
|
T21 |
137 |
|
T1 |
56451 |
|
T11 |
421 |
| auto[1] |
5471284 |
1 |
|
|
T1 |
47165 |
|
T16 |
1901 |
|
T17 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12243369 |
1 |
|
|
T21 |
137 |
|
T1 |
97168 |
|
T11 |
421 |
| auto[1] |
707242 |
1 |
|
|
T1 |
6448 |
|
T16 |
286 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468525 |
1 |
|
|
T21 |
137 |
|
T1 |
59253 |
|
T11 |
421 |
| auto[1] |
5482086 |
1 |
|
|
T1 |
44363 |
|
T16 |
1508 |
|
T17 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2405847 |
1 |
|
|
T1 |
18910 |
|
T16 |
518 |
|
T17 |
25 |
| auto[1] |
auto[0] |
auto[1] |
356831 |
1 |
|
|
T1 |
3291 |
|
T16 |
117 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2368997 |
1 |
|
|
T1 |
19005 |
|
T16 |
704 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[1] |
350411 |
1 |
|
|
T1 |
3157 |
|
T16 |
169 |
|
T2 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |