Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7431227 |
1 |
|
|
T21 |
137 |
|
T1 |
57903 |
|
T11 |
421 |
| auto[1] |
5519384 |
1 |
|
|
T1 |
45713 |
|
T13 |
3 |
|
T16 |
1537 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12239415 |
1 |
|
|
T21 |
137 |
|
T1 |
96943 |
|
T11 |
421 |
| auto[1] |
711196 |
1 |
|
|
T1 |
6673 |
|
T16 |
282 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7435167 |
1 |
|
|
T21 |
137 |
|
T1 |
57221 |
|
T11 |
421 |
| auto[1] |
5515444 |
1 |
|
|
T1 |
46395 |
|
T13 |
6 |
|
T16 |
1519 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2409717 |
1 |
|
|
T1 |
20532 |
|
T13 |
6 |
|
T16 |
766 |
| auto[1] |
auto[0] |
auto[1] |
356554 |
1 |
|
|
T1 |
3431 |
|
T16 |
178 |
|
T2 |
21 |
| auto[1] |
auto[1] |
auto[0] |
2394531 |
1 |
|
|
T1 |
19190 |
|
T16 |
471 |
|
T17 |
9 |
| auto[1] |
auto[1] |
auto[1] |
354642 |
1 |
|
|
T1 |
3242 |
|
T16 |
104 |
|
T17 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |