Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7452194 |
1 |
|
|
T21 |
137 |
|
T1 |
57290 |
|
T11 |
421 |
| auto[1] |
5498417 |
1 |
|
|
T1 |
46326 |
|
T13 |
6 |
|
T16 |
1629 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12245777 |
1 |
|
|
T21 |
137 |
|
T1 |
96648 |
|
T11 |
421 |
| auto[1] |
704834 |
1 |
|
|
T1 |
6968 |
|
T16 |
329 |
|
T17 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7478987 |
1 |
|
|
T21 |
137 |
|
T1 |
55742 |
|
T11 |
421 |
| auto[1] |
5471624 |
1 |
|
|
T1 |
47874 |
|
T13 |
7 |
|
T16 |
1689 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2388901 |
1 |
|
|
T1 |
21147 |
|
T13 |
7 |
|
T16 |
576 |
| auto[1] |
auto[0] |
auto[1] |
351745 |
1 |
|
|
T1 |
3709 |
|
T16 |
136 |
|
T17 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2377889 |
1 |
|
|
T1 |
19759 |
|
T16 |
784 |
|
T17 |
6 |
| auto[1] |
auto[1] |
auto[1] |
353089 |
1 |
|
|
T1 |
3259 |
|
T16 |
193 |
|
T2 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |