| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.63 | 99.06 | 99.24 | 100.00 | 99.80 | 99.68 | 99.99 |
| T763 | /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1938267914 | Jul 18 05:40:17 PM PDT 24 | Jul 18 05:40:27 PM PDT 24 | 77623359 ps | ||
| T78 | /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3187365696 | Jul 18 05:39:58 PM PDT 24 | Jul 18 05:40:01 PM PDT 24 | 15032987 ps | ||
| T764 | /workspace/coverage/cover_reg_top/35.gpio_intr_test.3946150412 | Jul 18 05:40:14 PM PDT 24 | Jul 18 05:40:24 PM PDT 24 | 33214263 ps | ||
| T765 | /workspace/coverage/cover_reg_top/48.gpio_intr_test.1406699884 | Jul 18 05:40:15 PM PDT 24 | Jul 18 05:40:26 PM PDT 24 | 20885795 ps | ||
| T766 | /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.4015596263 | Jul 18 05:39:47 PM PDT 24 | Jul 18 05:39:54 PM PDT 24 | 126741306 ps | ||
| T767 | /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3999746300 | Jul 18 05:40:00 PM PDT 24 | Jul 18 05:40:06 PM PDT 24 | 122243886 ps | ||
| T768 | /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3873656249 | Jul 18 05:39:59 PM PDT 24 | Jul 18 05:40:03 PM PDT 24 | 65175386 ps | ||
| T769 | /workspace/coverage/cover_reg_top/4.gpio_csr_rw.836698856 | Jul 18 05:39:49 PM PDT 24 | Jul 18 05:39:56 PM PDT 24 | 15849219 ps | ||
| T770 | /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2782360981 | Jul 18 05:39:59 PM PDT 24 | Jul 18 05:40:03 PM PDT 24 | 32771320 ps | ||
| T771 | /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.701575731 | Jul 18 05:40:00 PM PDT 24 | Jul 18 05:40:05 PM PDT 24 | 36579640 ps | ||
| T772 | /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1004184396 | Jul 18 05:40:00 PM PDT 24 | Jul 18 05:40:07 PM PDT 24 | 60295949 ps | ||
| T773 | /workspace/coverage/cover_reg_top/19.gpio_intr_test.1732886560 | Jul 18 05:40:16 PM PDT 24 | Jul 18 05:40:26 PM PDT 24 | 16306361 ps | ||
| T774 | /workspace/coverage/cover_reg_top/31.gpio_intr_test.3970885573 | Jul 18 05:40:13 PM PDT 24 | Jul 18 05:40:23 PM PDT 24 | 32753455 ps | ||
| T775 | /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2213702750 | Jul 18 05:40:00 PM PDT 24 | Jul 18 05:40:07 PM PDT 24 | 21900114 ps | ||
| T776 | /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3770883985 | Jul 18 05:40:00 PM PDT 24 | Jul 18 05:40:06 PM PDT 24 | 27169343 ps | ||
| T79 | /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3798868658 | Jul 18 05:39:48 PM PDT 24 | Jul 18 05:39:54 PM PDT 24 | 14155010 ps | ||
| T80 | /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.760250331 | Jul 18 05:39:53 PM PDT 24 | Jul 18 05:39:57 PM PDT 24 | 33958310 ps | ||
| T95 | /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1427737238 | Jul 18 05:39:45 PM PDT 24 | Jul 18 05:39:52 PM PDT 24 | 356003668 ps | ||
| T777 | /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3666325110 | Jul 18 05:39:46 PM PDT 24 | Jul 18 05:39:53 PM PDT 24 | 488755051 ps | ||
| T778 | /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.34867971 | Jul 18 05:39:44 PM PDT 24 | Jul 18 05:39:49 PM PDT 24 | 79381683 ps | ||
| T779 | /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3487638880 | Jul 18 05:39:52 PM PDT 24 | Jul 18 05:39:57 PM PDT 24 | 24338629 ps | ||
| T780 | /workspace/coverage/cover_reg_top/32.gpio_intr_test.2368710174 | Jul 18 05:40:12 PM PDT 24 | Jul 18 05:40:21 PM PDT 24 | 13575904 ps | ||
| T781 | /workspace/coverage/cover_reg_top/3.gpio_intr_test.194068923 | Jul 18 05:39:48 PM PDT 24 | Jul 18 05:39:54 PM PDT 24 | 26940489 ps | ||
| T782 | /workspace/coverage/cover_reg_top/29.gpio_intr_test.90996723 | Jul 18 05:40:14 PM PDT 24 | Jul 18 05:40:23 PM PDT 24 | 11591536 ps | ||
| T783 | /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.373830725 | Jul 18 05:40:01 PM PDT 24 | Jul 18 05:40:07 PM PDT 24 | 57760720 ps | ||
| T784 | /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.4280257915 | Jul 18 05:39:52 PM PDT 24 | Jul 18 05:39:57 PM PDT 24 | 51728009 ps | ||
| T785 | /workspace/coverage/cover_reg_top/41.gpio_intr_test.773135289 | Jul 18 05:40:27 PM PDT 24 | Jul 18 05:40:35 PM PDT 24 | 50748236 ps | ||
| T786 | /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.709356602 | Jul 18 05:40:14 PM PDT 24 | Jul 18 05:40:25 PM PDT 24 | 102871491 ps | ||
| T787 | /workspace/coverage/cover_reg_top/11.gpio_csr_rw.185469919 | Jul 18 05:39:57 PM PDT 24 | Jul 18 05:39:59 PM PDT 24 | 56864168 ps | ||
| T788 | /workspace/coverage/cover_reg_top/9.gpio_intr_test.2945551535 | Jul 18 05:40:00 PM PDT 24 | Jul 18 05:40:07 PM PDT 24 | 30246407 ps | ||
| T789 | /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.448732252 | Jul 18 05:40:08 PM PDT 24 | Jul 18 05:40:15 PM PDT 24 | 374766199 ps | ||
| T790 | /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.619954546 | Jul 18 05:39:46 PM PDT 24 | Jul 18 05:39:53 PM PDT 24 | 21930068 ps | ||
| T791 | /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.4074602125 | Jul 18 05:39:46 PM PDT 24 | Jul 18 05:39:52 PM PDT 24 | 70035385 ps | ||
| T792 | /workspace/coverage/cover_reg_top/5.gpio_intr_test.197760902 | Jul 18 05:39:57 PM PDT 24 | Jul 18 05:40:00 PM PDT 24 | 39266823 ps | ||
| T81 | /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3781371967 | Jul 18 05:40:17 PM PDT 24 | Jul 18 05:40:28 PM PDT 24 | 15394507 ps | ||
| T793 | /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1534983824 | Jul 18 05:40:14 PM PDT 24 | Jul 18 05:40:24 PM PDT 24 | 34106520 ps | ||
| T794 | /workspace/coverage/cover_reg_top/15.gpio_tl_errors.829827938 | Jul 18 05:40:14 PM PDT 24 | Jul 18 05:40:24 PM PDT 24 | 32371176 ps | ||
| T795 | /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4161723000 | Jul 18 05:39:50 PM PDT 24 | Jul 18 05:39:57 PM PDT 24 | 34939900 ps | ||
| T796 | /workspace/coverage/cover_reg_top/20.gpio_intr_test.3183420407 | Jul 18 05:40:16 PM PDT 24 | Jul 18 05:40:26 PM PDT 24 | 125565765 ps | ||
| T797 | /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.346916651 | Jul 18 05:40:00 PM PDT 24 | Jul 18 05:40:07 PM PDT 24 | 73082045 ps | ||
| T798 | /workspace/coverage/cover_reg_top/17.gpio_tl_errors.269456704 | Jul 18 05:40:09 PM PDT 24 | Jul 18 05:40:18 PM PDT 24 | 41507636 ps | ||
| T799 | /workspace/coverage/cover_reg_top/33.gpio_intr_test.1848945804 | Jul 18 05:40:17 PM PDT 24 | Jul 18 05:40:28 PM PDT 24 | 13704587 ps | ||
| T800 | /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1304466112 | Jul 18 05:39:55 PM PDT 24 | Jul 18 05:39:59 PM PDT 24 | 104825582 ps | ||
| T801 | /workspace/coverage/cover_reg_top/12.gpio_tl_errors.738799971 | Jul 18 05:40:04 PM PDT 24 | Jul 18 05:40:14 PM PDT 24 | 276454828 ps | ||
| T802 | /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3080821953 | Jul 18 05:40:03 PM PDT 24 | Jul 18 05:40:10 PM PDT 24 | 73158220 ps | ||
| T803 | /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.4266771153 | Jul 18 05:40:15 PM PDT 24 | Jul 18 05:40:25 PM PDT 24 | 71267245 ps | ||
| T82 | /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2040860311 | Jul 18 05:39:55 PM PDT 24 | Jul 18 05:39:58 PM PDT 24 | 139146579 ps | ||
| T804 | /workspace/coverage/cover_reg_top/44.gpio_intr_test.4220956119 | Jul 18 05:40:13 PM PDT 24 | Jul 18 05:40:23 PM PDT 24 | 13581868 ps | ||
| T805 | /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1830454338 | Jul 18 05:40:05 PM PDT 24 | Jul 18 05:40:13 PM PDT 24 | 22525085 ps | ||
| T806 | /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2689338247 | Jul 18 05:40:00 PM PDT 24 | Jul 18 05:40:07 PM PDT 24 | 42576957 ps | ||
| T96 | /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.677413142 | Jul 18 05:40:00 PM PDT 24 | Jul 18 05:40:05 PM PDT 24 | 47314915 ps | ||
| T807 | /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4128623085 | Jul 18 05:40:01 PM PDT 24 | Jul 18 05:40:10 PM PDT 24 | 46687079 ps | ||
| T808 | /workspace/coverage/cover_reg_top/26.gpio_intr_test.2664859842 | Jul 18 05:40:13 PM PDT 24 | Jul 18 05:40:23 PM PDT 24 | 41388604 ps | ||
| T809 | /workspace/coverage/cover_reg_top/13.gpio_csr_rw.881017022 | Jul 18 05:40:01 PM PDT 24 | Jul 18 05:40:08 PM PDT 24 | 44528491 ps | ||
| T810 | /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1955796987 | Jul 18 05:39:45 PM PDT 24 | Jul 18 05:39:51 PM PDT 24 | 188650942 ps | ||
| T83 | /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3561876828 | Jul 18 05:39:58 PM PDT 24 | Jul 18 05:40:01 PM PDT 24 | 86651939 ps | ||
| T84 | /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2892197765 | Jul 18 05:39:59 PM PDT 24 | Jul 18 05:40:04 PM PDT 24 | 99804645 ps | ||
| T811 | /workspace/coverage/cover_reg_top/14.gpio_tl_errors.957758967 | Jul 18 05:40:14 PM PDT 24 | Jul 18 05:40:26 PM PDT 24 | 356028721 ps | ||
| T812 | /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1004665499 | Jul 18 05:39:48 PM PDT 24 | Jul 18 05:39:55 PM PDT 24 | 123302914 ps | ||
| T813 | /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3341775010 | Jul 18 05:40:15 PM PDT 24 | Jul 18 05:40:26 PM PDT 24 | 38136128 ps | ||
| T814 | /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.4200628903 | Jul 18 05:40:02 PM PDT 24 | Jul 18 05:40:09 PM PDT 24 | 82296837 ps | ||
| T815 | /workspace/coverage/cover_reg_top/27.gpio_intr_test.4178065087 | Jul 18 05:40:14 PM PDT 24 | Jul 18 05:40:23 PM PDT 24 | 34753167 ps | ||
| T816 | /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2072845885 | Jul 18 05:40:08 PM PDT 24 | Jul 18 05:40:17 PM PDT 24 | 468208870 ps | ||
| T817 | /workspace/coverage/cover_reg_top/18.gpio_intr_test.472500297 | Jul 18 05:40:08 PM PDT 24 | Jul 18 05:40:15 PM PDT 24 | 21508631 ps | ||
| T818 | /workspace/coverage/cover_reg_top/39.gpio_intr_test.2825344695 | Jul 18 05:40:16 PM PDT 24 | Jul 18 05:40:27 PM PDT 24 | 56513943 ps | ||
| T85 | /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.87017982 | Jul 18 05:39:48 PM PDT 24 | Jul 18 05:39:54 PM PDT 24 | 27834292 ps | ||
| T819 | /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3888374716 | Jul 18 05:39:58 PM PDT 24 | Jul 18 05:40:02 PM PDT 24 | 115194493 ps | ||
| T820 | /workspace/coverage/cover_reg_top/24.gpio_intr_test.1851986152 | Jul 18 05:40:15 PM PDT 24 | Jul 18 05:40:26 PM PDT 24 | 117435596 ps | ||
| T821 | /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1643832800 | Jul 18 05:39:48 PM PDT 24 | Jul 18 05:39:55 PM PDT 24 | 242820160 ps | ||
| T86 | /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1581171282 | Jul 18 05:40:00 PM PDT 24 | Jul 18 05:40:05 PM PDT 24 | 56761461 ps | ||
| T822 | /workspace/coverage/cover_reg_top/9.gpio_tl_errors.532454700 | Jul 18 05:40:08 PM PDT 24 | Jul 18 05:40:16 PM PDT 24 | 749315317 ps | ||
| T823 | /workspace/coverage/cover_reg_top/12.gpio_intr_test.1272387602 | Jul 18 05:39:57 PM PDT 24 | Jul 18 05:40:00 PM PDT 24 | 28098444 ps | ||
| T824 | /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2107947389 | Jul 18 05:40:17 PM PDT 24 | Jul 18 05:40:28 PM PDT 24 | 108209171 ps | ||
| T825 | /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3539174723 | Jul 18 05:40:00 PM PDT 24 | Jul 18 05:40:08 PM PDT 24 | 138117882 ps | ||
| T826 | /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4146124529 | Jul 18 05:40:01 PM PDT 24 | Jul 18 05:40:07 PM PDT 24 | 12189209 ps | ||
| T827 | /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2266492031 | Jul 18 05:40:00 PM PDT 24 | Jul 18 05:40:06 PM PDT 24 | 19876991 ps | ||
| T828 | /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1878152061 | Jul 18 05:40:09 PM PDT 24 | Jul 18 05:40:16 PM PDT 24 | 78849557 ps | ||
| T829 | /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2869795932 | Jul 18 05:40:08 PM PDT 24 | Jul 18 05:40:15 PM PDT 24 | 13806801 ps | ||
| T830 | /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3315374268 | Jul 18 05:40:13 PM PDT 24 | Jul 18 05:40:23 PM PDT 24 | 57949944 ps | ||
| T831 | /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1545479809 | Jul 18 05:39:45 PM PDT 24 | Jul 18 05:39:52 PM PDT 24 | 23740512 ps | ||
| T832 | /workspace/coverage/cover_reg_top/0.gpio_intr_test.3164101028 | Jul 18 05:39:55 PM PDT 24 | Jul 18 05:39:58 PM PDT 24 | 16759099 ps | ||
| T833 | /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3582122493 | Jul 18 05:41:36 PM PDT 24 | Jul 18 05:41:52 PM PDT 24 | 43401324 ps | ||
| T94 | /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.212361617 | Jul 18 05:40:04 PM PDT 24 | Jul 18 05:40:12 PM PDT 24 | 79645397 ps | ||
| T834 | /workspace/coverage/cover_reg_top/42.gpio_intr_test.3499489284 | Jul 18 05:40:15 PM PDT 24 | Jul 18 05:40:26 PM PDT 24 | 27764950 ps | ||
| T835 | /workspace/coverage/cover_reg_top/8.gpio_intr_test.3474802474 | Jul 18 05:40:07 PM PDT 24 | Jul 18 05:40:13 PM PDT 24 | 38361520 ps | ||
| T836 | /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1178270625 | Jul 18 05:40:17 PM PDT 24 | Jul 18 05:40:28 PM PDT 24 | 28201708 ps | ||
| T837 | /workspace/coverage/cover_reg_top/25.gpio_intr_test.3643337449 | Jul 18 05:40:17 PM PDT 24 | Jul 18 05:40:28 PM PDT 24 | 11990289 ps | ||
| T838 | /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1418253730 | Jul 18 05:40:00 PM PDT 24 | Jul 18 05:40:06 PM PDT 24 | 90956966 ps | ||
| T839 | /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2746563282 | Jul 18 05:40:00 PM PDT 24 | Jul 18 05:40:08 PM PDT 24 | 248859104 ps | ||
| T840 | /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.4067154128 | Jul 18 05:40:01 PM PDT 24 | Jul 18 05:40:08 PM PDT 24 | 19982248 ps | ||
| T841 | /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.796419896 | Jul 18 05:40:31 PM PDT 24 | Jul 18 05:40:41 PM PDT 24 | 183156141 ps | ||
| T842 | /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.865017286 | Jul 18 05:40:17 PM PDT 24 | Jul 18 05:40:28 PM PDT 24 | 279993812 ps | ||
| T843 | /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2328116304 | Jul 18 05:40:33 PM PDT 24 | Jul 18 05:40:43 PM PDT 24 | 136647370 ps | ||
| T844 | /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2910046788 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:38 PM PDT 24 | 308013036 ps | ||
| T845 | /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2732451449 | Jul 18 05:40:34 PM PDT 24 | Jul 18 05:40:43 PM PDT 24 | 201012368 ps | ||
| T846 | /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.512979252 | Jul 18 05:40:19 PM PDT 24 | Jul 18 05:40:30 PM PDT 24 | 223017841 ps | ||
| T847 | /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2613438879 | Jul 18 05:40:28 PM PDT 24 | Jul 18 05:40:36 PM PDT 24 | 66049003 ps | ||
| T848 | /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.936284082 | Jul 18 05:40:31 PM PDT 24 | Jul 18 05:40:40 PM PDT 24 | 39672405 ps | ||
| T849 | /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1603818806 | Jul 18 05:40:35 PM PDT 24 | Jul 18 05:40:43 PM PDT 24 | 43266899 ps | ||
| T850 | /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1796356031 | Jul 18 05:40:27 PM PDT 24 | Jul 18 05:40:34 PM PDT 24 | 142649150 ps | ||
| T851 | /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.904006568 | Jul 18 05:40:20 PM PDT 24 | Jul 18 05:40:30 PM PDT 24 | 67837170 ps | ||
| T852 | /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1787487947 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:39 PM PDT 24 | 64504208 ps | ||
| T853 | /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.446651654 | Jul 18 05:40:29 PM PDT 24 | Jul 18 05:40:37 PM PDT 24 | 121116864 ps | ||
| T854 | /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1288921522 | Jul 18 05:40:19 PM PDT 24 | Jul 18 05:40:30 PM PDT 24 | 34334992 ps | ||
| T855 | /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4255990974 | Jul 18 05:40:31 PM PDT 24 | Jul 18 05:40:40 PM PDT 24 | 298105574 ps | ||
| T856 | /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2098888629 | Jul 18 05:40:19 PM PDT 24 | Jul 18 05:40:30 PM PDT 24 | 77496945 ps | ||
| T857 | /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2156578572 | Jul 18 05:40:20 PM PDT 24 | Jul 18 05:40:30 PM PDT 24 | 41406327 ps | ||
| T858 | /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3097476855 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:39 PM PDT 24 | 56548262 ps | ||
| T859 | /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3697701583 | Jul 18 05:40:32 PM PDT 24 | Jul 18 05:40:42 PM PDT 24 | 67999608 ps | ||
| T860 | /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.238354402 | Jul 18 05:40:28 PM PDT 24 | Jul 18 05:40:36 PM PDT 24 | 182874006 ps | ||
| T861 | /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3514240142 | Jul 18 05:40:20 PM PDT 24 | Jul 18 05:40:30 PM PDT 24 | 22220920 ps | ||
| T862 | /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4092290532 | Jul 18 05:40:27 PM PDT 24 | Jul 18 05:40:35 PM PDT 24 | 56799855 ps | ||
| T863 | /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.285027149 | Jul 18 05:40:29 PM PDT 24 | Jul 18 05:40:36 PM PDT 24 | 210077630 ps | ||
| T864 | /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4258491335 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:38 PM PDT 24 | 141945021 ps | ||
| T865 | /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1191826687 | Jul 18 05:40:13 PM PDT 24 | Jul 18 05:40:24 PM PDT 24 | 176379892 ps | ||
| T866 | /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.404806343 | Jul 18 05:40:17 PM PDT 24 | Jul 18 05:40:28 PM PDT 24 | 677046553 ps | ||
| T867 | /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2885901305 | Jul 18 05:40:15 PM PDT 24 | Jul 18 05:40:25 PM PDT 24 | 44483440 ps | ||
| T868 | /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1544291622 | Jul 18 05:40:35 PM PDT 24 | Jul 18 05:40:44 PM PDT 24 | 191278251 ps | ||
| T869 | /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3789499732 | Jul 18 05:40:34 PM PDT 24 | Jul 18 05:40:43 PM PDT 24 | 107337015 ps | ||
| T870 | /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2860242612 | Jul 18 05:40:14 PM PDT 24 | Jul 18 05:40:24 PM PDT 24 | 381264611 ps | ||
| T871 | /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.907325980 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:39 PM PDT 24 | 110999227 ps | ||
| T872 | /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3759826111 | Jul 18 05:40:32 PM PDT 24 | Jul 18 05:40:41 PM PDT 24 | 148424973 ps | ||
| T873 | /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3503654885 | Jul 18 05:40:29 PM PDT 24 | Jul 18 05:40:37 PM PDT 24 | 71317143 ps | ||
| T874 | /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2818258733 | Jul 18 05:40:34 PM PDT 24 | Jul 18 05:40:44 PM PDT 24 | 139927921 ps | ||
| T875 | /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4024789341 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:38 PM PDT 24 | 208641389 ps | ||
| T876 | /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2205715208 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:38 PM PDT 24 | 144329268 ps | ||
| T877 | /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2396837059 | Jul 18 05:40:16 PM PDT 24 | Jul 18 05:40:28 PM PDT 24 | 35801443 ps | ||
| T878 | /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1144911943 | Jul 18 05:40:34 PM PDT 24 | Jul 18 05:40:43 PM PDT 24 | 122393322 ps | ||
| T879 | /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.357944971 | Jul 18 05:40:14 PM PDT 24 | Jul 18 05:40:25 PM PDT 24 | 97158278 ps | ||
| T880 | /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4085613591 | Jul 18 05:40:14 PM PDT 24 | Jul 18 05:40:24 PM PDT 24 | 38872674 ps | ||
| T881 | /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2439746336 | Jul 18 05:40:17 PM PDT 24 | Jul 18 05:40:28 PM PDT 24 | 26737706 ps | ||
| T882 | /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4061083053 | Jul 18 05:40:13 PM PDT 24 | Jul 18 05:40:23 PM PDT 24 | 46385550 ps | ||
| T883 | /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2347846361 | Jul 18 05:40:31 PM PDT 24 | Jul 18 05:40:40 PM PDT 24 | 111333143 ps | ||
| T884 | /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2106761391 | Jul 18 05:40:28 PM PDT 24 | Jul 18 05:40:36 PM PDT 24 | 94486864 ps | ||
| T885 | /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.566875886 | Jul 18 05:40:29 PM PDT 24 | Jul 18 05:40:37 PM PDT 24 | 50671477 ps | ||
| T886 | /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.4007077148 | Jul 18 05:40:19 PM PDT 24 | Jul 18 05:40:30 PM PDT 24 | 32048934 ps | ||
| T887 | /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2905352567 | Jul 18 05:40:14 PM PDT 24 | Jul 18 05:40:25 PM PDT 24 | 96027522 ps | ||
| T888 | /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1990232730 | Jul 18 05:40:27 PM PDT 24 | Jul 18 05:40:35 PM PDT 24 | 133086643 ps | ||
| T889 | /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3539202031 | Jul 18 05:40:12 PM PDT 24 | Jul 18 05:40:23 PM PDT 24 | 88777229 ps | ||
| T890 | /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1711081234 | Jul 18 05:40:15 PM PDT 24 | Jul 18 05:40:25 PM PDT 24 | 219276535 ps | ||
| T891 | /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.833492614 | Jul 18 05:40:35 PM PDT 24 | Jul 18 05:40:43 PM PDT 24 | 32059927 ps | ||
| T892 | /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2550664373 | Jul 18 05:40:27 PM PDT 24 | Jul 18 05:40:34 PM PDT 24 | 40955223 ps | ||
| T893 | /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3931768469 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:39 PM PDT 24 | 142477342 ps | ||
| T894 | /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2527422164 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:38 PM PDT 24 | 60935554 ps | ||
| T895 | /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1181398874 | Jul 18 05:40:35 PM PDT 24 | Jul 18 05:40:44 PM PDT 24 | 58245176 ps | ||
| T896 | /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1447119233 | Jul 18 05:40:33 PM PDT 24 | Jul 18 05:40:43 PM PDT 24 | 76730072 ps | ||
| T897 | /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4007478026 | Jul 18 05:40:32 PM PDT 24 | Jul 18 05:40:42 PM PDT 24 | 222514831 ps | ||
| T898 | /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1736367054 | Jul 18 05:40:31 PM PDT 24 | Jul 18 05:40:40 PM PDT 24 | 97356200 ps | ||
| T899 | /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3632057979 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:39 PM PDT 24 | 137504848 ps | ||
| T900 | /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3767603466 | Jul 18 05:40:33 PM PDT 24 | Jul 18 05:40:43 PM PDT 24 | 48685737 ps | ||
| T901 | /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3953874762 | Jul 18 05:40:32 PM PDT 24 | Jul 18 05:40:42 PM PDT 24 | 790992443 ps | ||
| T902 | /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.884099063 | Jul 18 05:40:15 PM PDT 24 | Jul 18 05:40:25 PM PDT 24 | 61341770 ps | ||
| T903 | /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3058706175 | Jul 18 05:40:17 PM PDT 24 | Jul 18 05:40:28 PM PDT 24 | 266190248 ps | ||
| T904 | /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3287068051 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:39 PM PDT 24 | 231668433 ps | ||
| T905 | /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4154800299 | Jul 18 05:40:16 PM PDT 24 | Jul 18 05:40:28 PM PDT 24 | 86321243 ps | ||
| T906 | /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2813167943 | Jul 18 05:40:19 PM PDT 24 | Jul 18 05:40:29 PM PDT 24 | 132076783 ps | ||
| T907 | /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2443084253 | Jul 18 05:40:26 PM PDT 24 | Jul 18 05:40:34 PM PDT 24 | 47051964 ps | ||
| T908 | /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3043184196 | Jul 18 05:40:13 PM PDT 24 | Jul 18 05:40:24 PM PDT 24 | 52916054 ps | ||
| T909 | /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1008602360 | Jul 18 05:40:20 PM PDT 24 | Jul 18 05:40:30 PM PDT 24 | 48535610 ps | ||
| T910 | /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2130624407 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:39 PM PDT 24 | 272649053 ps | ||
| T911 | /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4176568304 | Jul 18 05:40:17 PM PDT 24 | Jul 18 05:40:28 PM PDT 24 | 347662636 ps | ||
| T912 | /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4269225798 | Jul 18 05:40:35 PM PDT 24 | Jul 18 05:40:44 PM PDT 24 | 115833990 ps | ||
| T913 | /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1659993593 | Jul 18 05:41:55 PM PDT 24 | Jul 18 05:42:08 PM PDT 24 | 185131927 ps | ||
| T914 | /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.576880273 | Jul 18 05:40:17 PM PDT 24 | Jul 18 05:40:28 PM PDT 24 | 139771634 ps | ||
| T915 | /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1351291663 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:38 PM PDT 24 | 92826955 ps | ||
| T916 | /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1074506532 | Jul 18 05:40:31 PM PDT 24 | Jul 18 05:40:40 PM PDT 24 | 261541114 ps | ||
| T917 | /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1836248085 | Jul 18 05:40:18 PM PDT 24 | Jul 18 05:40:29 PM PDT 24 | 70677205 ps | ||
| T918 | /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.525454268 | Jul 18 05:40:34 PM PDT 24 | Jul 18 05:40:43 PM PDT 24 | 254660080 ps | ||
| T919 | /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3005540871 | Jul 18 05:40:13 PM PDT 24 | Jul 18 05:40:24 PM PDT 24 | 369904042 ps | ||
| T920 | /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.423409581 | Jul 18 05:40:28 PM PDT 24 | Jul 18 05:40:36 PM PDT 24 | 64401737 ps | ||
| T921 | /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1758740339 | Jul 18 05:40:35 PM PDT 24 | Jul 18 05:40:43 PM PDT 24 | 96180213 ps | ||
| T922 | /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1018751141 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:39 PM PDT 24 | 79624058 ps | ||
| T923 | /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1305096599 | Jul 18 05:40:15 PM PDT 24 | Jul 18 05:40:26 PM PDT 24 | 30403509 ps | ||
| T924 | /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.568622638 | Jul 18 05:40:34 PM PDT 24 | Jul 18 05:40:43 PM PDT 24 | 110316725 ps | ||
| T925 | /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.441217706 | Jul 18 05:40:32 PM PDT 24 | Jul 18 05:40:41 PM PDT 24 | 58424131 ps | ||
| T926 | /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4165803931 | Jul 18 05:40:33 PM PDT 24 | Jul 18 05:40:43 PM PDT 24 | 282518077 ps | ||
| T927 | /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.519521651 | Jul 18 05:40:32 PM PDT 24 | Jul 18 05:40:42 PM PDT 24 | 55380419 ps | ||
| T928 | /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2149121292 | Jul 18 05:40:15 PM PDT 24 | Jul 18 05:40:25 PM PDT 24 | 210485923 ps | ||
| T929 | /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.803417019 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:39 PM PDT 24 | 179866194 ps | ||
| T930 | /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3381860349 | Jul 18 05:40:27 PM PDT 24 | Jul 18 05:40:35 PM PDT 24 | 88650190 ps | ||
| T931 | /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2973699251 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:39 PM PDT 24 | 287163313 ps | ||
| T932 | /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.996340710 | Jul 18 05:40:32 PM PDT 24 | Jul 18 05:40:41 PM PDT 24 | 76487785 ps | ||
| T933 | /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.4011406358 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:39 PM PDT 24 | 103005929 ps | ||
| T934 | /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1961383554 | Jul 18 05:40:28 PM PDT 24 | Jul 18 05:40:36 PM PDT 24 | 214153657 ps | ||
| T935 | /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.621280804 | Jul 18 05:40:32 PM PDT 24 | Jul 18 05:40:42 PM PDT 24 | 48883020 ps | ||
| T936 | /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.602608641 | Jul 18 05:40:33 PM PDT 24 | Jul 18 05:40:43 PM PDT 24 | 500567947 ps | ||
| T937 | /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.544870160 | Jul 18 05:40:32 PM PDT 24 | Jul 18 05:40:42 PM PDT 24 | 41887457 ps | ||
| T938 | /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3229086727 | Jul 18 05:40:20 PM PDT 24 | Jul 18 05:40:31 PM PDT 24 | 45993688 ps | ||
| T939 | /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3951090057 | Jul 18 05:40:30 PM PDT 24 | Jul 18 05:40:38 PM PDT 24 | 93856822 ps | ||
| T940 | /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2402347216 | Jul 18 05:40:34 PM PDT 24 | Jul 18 05:40:43 PM PDT 24 | 316776462 ps |
| Test location | /workspace/coverage/default/42.gpio_full_random.4140636565 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 71079516 ps |
| CPU time | 1.11 seconds |
| Started | Jul 18 05:42:27 PM PDT 24 |
| Finished | Jul 18 05:42:43 PM PDT 24 |
| Peak memory | 196848 kb |
| Host | smart-d7023a5f-6427-4756-bd5e-37e92e082a8e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140636565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.4140636565 |
| Directory | /workspace/42.gpio_full_random/latest |
| Test location | /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2015494599 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 95698411 ps |
| CPU time | 3.88 seconds |
| Started | Jul 18 05:40:48 PM PDT 24 |
| Finished | Jul 18 05:40:57 PM PDT 24 |
| Peak memory | 198296 kb |
| Host | smart-c935723f-2c4f-4cd9-9be9-288c8bf9e92a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015494599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2015494599 |
| Directory | /workspace/0.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.117006700 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 38894470821 ps |
| CPU time | 247.27 seconds |
| Started | Jul 18 05:42:22 PM PDT 24 |
| Finished | Jul 18 05:46:42 PM PDT 24 |
| Peak memory | 198540 kb |
| Host | smart-fd184eda-69da-4bee-95e2-186349bbbd27 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =117006700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.117006700 |
| Directory | /workspace/46.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.gpio_sec_cm.1595979932 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 112972960 ps |
| CPU time | 0.92 seconds |
| Started | Jul 18 05:40:49 PM PDT 24 |
| Finished | Jul 18 05:40:56 PM PDT 24 |
| Peak memory | 214248 kb |
| Host | smart-71118abb-5eaa-48bd-aaeb-199e1dd0b8dc |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595979932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1595979932 |
| Directory | /workspace/0.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1138003117 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1492218728 ps |
| CPU time | 4.94 seconds |
| Started | Jul 18 05:42:09 PM PDT 24 |
| Finished | Jul 18 05:42:27 PM PDT 24 |
| Peak memory | 198120 kb |
| Host | smart-73b9eab0-813d-4b99-b91e-15e3fd413dd0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138003117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra ndom_long_reg_writes_reg_reads.1138003117 |
| Directory | /workspace/35.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2040860311 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 139146579 ps |
| CPU time | 0.88 seconds |
| Started | Jul 18 05:39:55 PM PDT 24 |
| Finished | Jul 18 05:39:58 PM PDT 24 |
| Peak memory | 196344 kb |
| Host | smart-d8c7d15d-dbf9-44bf-9836-4965f82aac98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040860311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_aliasing.2040860311 |
| Directory | /workspace/0.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1757615610 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 186821886 ps |
| CPU time | 1.52 seconds |
| Started | Jul 18 05:40:02 PM PDT 24 |
| Finished | Jul 18 05:40:10 PM PDT 24 |
| Peak memory | 198296 kb |
| Host | smart-961f3aea-a72c-4b98-a0d8-e00ccc63670a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757615610 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 10.gpio_tl_intg_err.1757615610 |
| Directory | /workspace/10.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.778332473 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 41255677 ps |
| CPU time | 0.92 seconds |
| Started | Jul 18 05:39:59 PM PDT 24 |
| Finished | Jul 18 05:40:05 PM PDT 24 |
| Peak memory | 197604 kb |
| Host | smart-ab92b77c-54e4-4181-8528-2424cac6bdcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778332473 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 11.gpio_same_csr_outstanding.778332473 |
| Directory | /workspace/11.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/12.gpio_alert_test.1906440549 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 32608992 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:41:14 PM PDT 24 |
| Finished | Jul 18 05:41:24 PM PDT 24 |
| Peak memory | 194156 kb |
| Host | smart-1a8d3f5b-324f-40a0-a16f-e1873724cf37 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906440549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1906440549 |
| Directory | /workspace/12.gpio_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2316752379 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 72672811 ps |
| CPU time | 1.17 seconds |
| Started | Jul 18 05:39:59 PM PDT 24 |
| Finished | Jul 18 05:40:05 PM PDT 24 |
| Peak memory | 198324 kb |
| Host | smart-e64ea678-7752-4c1c-b3e4-52ce11f99600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316752379 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 18.gpio_tl_intg_err.2316752379 |
| Directory | /workspace/18.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3684897253 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 158799177 ps |
| CPU time | 3.06 seconds |
| Started | Jul 18 05:39:58 PM PDT 24 |
| Finished | Jul 18 05:40:03 PM PDT 24 |
| Peak memory | 197400 kb |
| Host | smart-4c9f0829-11e0-4aae-b49f-be5e91d6e072 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684897253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3684897253 |
| Directory | /workspace/0.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.619954546 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 21930068 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:39:46 PM PDT 24 |
| Finished | Jul 18 05:39:53 PM PDT 24 |
| Peak memory | 195712 kb |
| Host | smart-4e76b4a2-8ab5-4f14-b807-7694626eeb7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619954546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.619954546 |
| Directory | /workspace/0.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3139520092 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 91074313 ps |
| CPU time | 1.76 seconds |
| Started | Jul 18 05:39:52 PM PDT 24 |
| Finished | Jul 18 05:39:58 PM PDT 24 |
| Peak memory | 198324 kb |
| Host | smart-a3ebba10-eb22-4522-aca2-b0ed2554a697 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139520092 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3139520092 |
| Directory | /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3798868658 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 14155010 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:39:48 PM PDT 24 |
| Finished | Jul 18 05:39:54 PM PDT 24 |
| Peak memory | 193556 kb |
| Host | smart-ec4aa412-f3f1-41c1-a0a5-6a810ecf6c35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798868658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio _csr_rw.3798868658 |
| Directory | /workspace/0.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_intr_test.3164101028 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 16759099 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:39:55 PM PDT 24 |
| Finished | Jul 18 05:39:58 PM PDT 24 |
| Peak memory | 194732 kb |
| Host | smart-8b8032ef-4b6c-4409-9bf8-9fa3c48f53ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164101028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3164101028 |
| Directory | /workspace/0.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2443841733 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 32983559 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:39:52 PM PDT 24 |
| Finished | Jul 18 05:39:57 PM PDT 24 |
| Peak memory | 197252 kb |
| Host | smart-6399b40a-2741-4e80-89af-5d442c96889f |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443841733 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.gpio_same_csr_outstanding.2443841733 |
| Directory | /workspace/0.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_tl_errors.673829600 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 374696875 ps |
| CPU time | 2.23 seconds |
| Started | Jul 18 05:39:52 PM PDT 24 |
| Finished | Jul 18 05:39:58 PM PDT 24 |
| Peak memory | 198348 kb |
| Host | smart-6726d6c4-37e3-402c-8db0-c48d3b358ae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673829600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.673829600 |
| Directory | /workspace/0.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.4280257915 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 51728009 ps |
| CPU time | 0.94 seconds |
| Started | Jul 18 05:39:52 PM PDT 24 |
| Finished | Jul 18 05:39:57 PM PDT 24 |
| Peak memory | 198064 kb |
| Host | smart-09b22ee0-85d6-4d1e-a72e-46ee39ad853b |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280257915 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 0.gpio_tl_intg_err.4280257915 |
| Directory | /workspace/0.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3561876828 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 86651939 ps |
| CPU time | 0.88 seconds |
| Started | Jul 18 05:39:58 PM PDT 24 |
| Finished | Jul 18 05:40:01 PM PDT 24 |
| Peak memory | 195984 kb |
| Host | smart-22a3a2a9-18a0-4524-8f6b-0021f8cdc4bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561876828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_aliasing.3561876828 |
| Directory | /workspace/1.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1955796987 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 188650942 ps |
| CPU time | 1.47 seconds |
| Started | Jul 18 05:39:45 PM PDT 24 |
| Finished | Jul 18 05:39:51 PM PDT 24 |
| Peak memory | 197420 kb |
| Host | smart-60df17c6-3d31-463b-ac5e-609e450428b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955796987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1955796987 |
| Directory | /workspace/1.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.87017982 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 27834292 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:39:48 PM PDT 24 |
| Finished | Jul 18 05:39:54 PM PDT 24 |
| Peak memory | 195512 kb |
| Host | smart-06c35b48-268c-4950-8155-09393ad81d9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87017982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.87017982 |
| Directory | /workspace/1.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1545479809 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 23740512 ps |
| CPU time | 1.14 seconds |
| Started | Jul 18 05:39:45 PM PDT 24 |
| Finished | Jul 18 05:39:52 PM PDT 24 |
| Peak memory | 198168 kb |
| Host | smart-c4f5f493-1e6f-4a13-9f2f-22c51c99cb53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545479809 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1545479809 |
| Directory | /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3487638880 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 24338629 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:39:52 PM PDT 24 |
| Finished | Jul 18 05:39:57 PM PDT 24 |
| Peak memory | 195480 kb |
| Host | smart-4205d6c3-cb29-45b5-85be-0571c75bf4b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487638880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio _csr_rw.3487638880 |
| Directory | /workspace/1.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_intr_test.2018618880 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 20444522 ps |
| CPU time | 0.62 seconds |
| Started | Jul 18 05:39:48 PM PDT 24 |
| Finished | Jul 18 05:39:54 PM PDT 24 |
| Peak memory | 194120 kb |
| Host | smart-d8871915-9757-4c0a-8a8e-524bcbf59d00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018618880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2018618880 |
| Directory | /workspace/1.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1004665499 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 123302914 ps |
| CPU time | 0.85 seconds |
| Started | Jul 18 05:39:48 PM PDT 24 |
| Finished | Jul 18 05:39:55 PM PDT 24 |
| Peak memory | 196656 kb |
| Host | smart-d4181cfc-0c18-40f8-9e81-fde519e8b63f |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004665499 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.gpio_same_csr_outstanding.1004665499 |
| Directory | /workspace/1.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2965376221 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 370985436 ps |
| CPU time | 3.29 seconds |
| Started | Jul 18 05:39:47 PM PDT 24 |
| Finished | Jul 18 05:39:56 PM PDT 24 |
| Peak memory | 198452 kb |
| Host | smart-3546ed7b-28b5-4ab9-8c7d-d1b3d565ce73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965376221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2965376221 |
| Directory | /workspace/1.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1427737238 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 356003668 ps |
| CPU time | 1.47 seconds |
| Started | Jul 18 05:39:45 PM PDT 24 |
| Finished | Jul 18 05:39:52 PM PDT 24 |
| Peak memory | 198316 kb |
| Host | smart-3d8ee6fb-ee9a-46b6-a91c-0e472adc1122 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427737238 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 1.gpio_tl_intg_err.1427737238 |
| Directory | /workspace/1.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2648501578 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 81070592 ps |
| CPU time | 0.69 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:06 PM PDT 24 |
| Peak memory | 197900 kb |
| Host | smart-5eb18748-7b24-4b95-a017-67580fb4c2f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648501578 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2648501578 |
| Directory | /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3080821953 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 73158220 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:40:03 PM PDT 24 |
| Finished | Jul 18 05:40:10 PM PDT 24 |
| Peak memory | 194696 kb |
| Host | smart-414a9aa1-b1df-4d40-8230-fe26ef6fce12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080821953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi o_csr_rw.3080821953 |
| Directory | /workspace/10.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_intr_test.3911686763 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 15461100 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:24 PM PDT 24 |
| Peak memory | 193952 kb |
| Host | smart-ec9d1f50-6f23-4808-882e-cd28f25a5daa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911686763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3911686763 |
| Directory | /workspace/10.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3873656249 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 65175386 ps |
| CPU time | 0.73 seconds |
| Started | Jul 18 05:39:59 PM PDT 24 |
| Finished | Jul 18 05:40:03 PM PDT 24 |
| Peak memory | 195904 kb |
| Host | smart-cf6151d9-7878-48b7-bf39-7d832b6095ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873656249 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 10.gpio_same_csr_outstanding.3873656249 |
| Directory | /workspace/10.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4128623085 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 46687079 ps |
| CPU time | 2.33 seconds |
| Started | Jul 18 05:40:01 PM PDT 24 |
| Finished | Jul 18 05:40:10 PM PDT 24 |
| Peak memory | 198364 kb |
| Host | smart-c07c8d2b-7c20-4eb7-9173-d68b0856ffad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128623085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.4128623085 |
| Directory | /workspace/10.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1938267914 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 77623359 ps |
| CPU time | 0.77 seconds |
| Started | Jul 18 05:40:17 PM PDT 24 |
| Finished | Jul 18 05:40:27 PM PDT 24 |
| Peak memory | 197980 kb |
| Host | smart-7da7bd91-bb9a-49c6-bf9e-c66fc332deda |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938267914 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1938267914 |
| Directory | /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_csr_rw.185469919 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 56864168 ps |
| CPU time | 0.65 seconds |
| Started | Jul 18 05:39:57 PM PDT 24 |
| Finished | Jul 18 05:39:59 PM PDT 24 |
| Peak memory | 195032 kb |
| Host | smart-71feb58e-2b97-41eb-b7dd-30ed99530c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185469919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio _csr_rw.185469919 |
| Directory | /workspace/11.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_intr_test.483521319 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 19699642 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:40:01 PM PDT 24 |
| Finished | Jul 18 05:40:07 PM PDT 24 |
| Peak memory | 194096 kb |
| Host | smart-9ccb13de-b1c3-484e-854e-51a28def190e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483521319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.483521319 |
| Directory | /workspace/11.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1490170193 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 95896352 ps |
| CPU time | 1.91 seconds |
| Started | Jul 18 05:40:08 PM PDT 24 |
| Finished | Jul 18 05:40:17 PM PDT 24 |
| Peak memory | 198272 kb |
| Host | smart-cf7c6900-46c8-4c17-a291-2749ac0b5fd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490170193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1490170193 |
| Directory | /workspace/11.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.949018802 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 49349150 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:40:01 PM PDT 24 |
| Finished | Jul 18 05:40:08 PM PDT 24 |
| Peak memory | 197404 kb |
| Host | smart-86b160fd-0a21-4709-a13f-8021bde7d80d |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949018802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.gpio_tl_intg_err.949018802 |
| Directory | /workspace/11.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3829408510 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 20465721 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:40:08 PM PDT 24 |
| Finished | Jul 18 05:40:15 PM PDT 24 |
| Peak memory | 198168 kb |
| Host | smart-ea2d53f4-2fc6-43ad-96a2-f57d1e0fac2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829408510 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3829408510 |
| Directory | /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2226337586 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 18898356 ps |
| CPU time | 0.66 seconds |
| Started | Jul 18 05:40:01 PM PDT 24 |
| Finished | Jul 18 05:40:08 PM PDT 24 |
| Peak memory | 195172 kb |
| Host | smart-48ff55d7-a6a8-482d-bd08-c0be495088ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226337586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi o_csr_rw.2226337586 |
| Directory | /workspace/12.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_intr_test.1272387602 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 28098444 ps |
| CPU time | 0.7 seconds |
| Started | Jul 18 05:39:57 PM PDT 24 |
| Finished | Jul 18 05:40:00 PM PDT 24 |
| Peak memory | 194024 kb |
| Host | smart-ce020ae6-fea4-4b40-8e7c-e7f041c3e2e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272387602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1272387602 |
| Directory | /workspace/12.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2689338247 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 42576957 ps |
| CPU time | 0.86 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:07 PM PDT 24 |
| Peak memory | 196636 kb |
| Host | smart-46223c61-eedd-4d1d-ab3c-04143a0b8ecd |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689338247 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 12.gpio_same_csr_outstanding.2689338247 |
| Directory | /workspace/12.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_tl_errors.738799971 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 276454828 ps |
| CPU time | 2.93 seconds |
| Started | Jul 18 05:40:04 PM PDT 24 |
| Finished | Jul 18 05:40:14 PM PDT 24 |
| Peak memory | 198292 kb |
| Host | smart-76b1e4e8-c408-4aab-bcfd-acefa5e36fee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738799971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.738799971 |
| Directory | /workspace/12.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.677413142 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 47314915 ps |
| CPU time | 0.89 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:05 PM PDT 24 |
| Peak memory | 197492 kb |
| Host | smart-1ff1ab5e-9baf-4d71-9ba7-535442635428 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677413142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.gpio_tl_intg_err.677413142 |
| Directory | /workspace/12.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3539174723 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 138117882 ps |
| CPU time | 1.56 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:08 PM PDT 24 |
| Peak memory | 198428 kb |
| Host | smart-c8e3bdfc-ae49-41a5-9d7d-9e2c5b31cae2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539174723 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3539174723 |
| Directory | /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_csr_rw.881017022 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 44528491 ps |
| CPU time | 0.62 seconds |
| Started | Jul 18 05:40:01 PM PDT 24 |
| Finished | Jul 18 05:40:08 PM PDT 24 |
| Peak memory | 195000 kb |
| Host | smart-23e518b4-f94d-4e0b-8507-9c0ce2ca3885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881017022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio _csr_rw.881017022 |
| Directory | /workspace/13.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_intr_test.969715214 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 14169358 ps |
| CPU time | 0.62 seconds |
| Started | Jul 18 05:39:59 PM PDT 24 |
| Finished | Jul 18 05:40:04 PM PDT 24 |
| Peak memory | 193992 kb |
| Host | smart-721186fa-7ea8-47ff-8dd8-6c400bec9832 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969715214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.969715214 |
| Directory | /workspace/13.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.4214533594 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 147463660 ps |
| CPU time | 0.8 seconds |
| Started | Jul 18 05:39:59 PM PDT 24 |
| Finished | Jul 18 05:40:04 PM PDT 24 |
| Peak memory | 196232 kb |
| Host | smart-9029290c-10ac-4904-9234-7fc92a9a15e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214533594 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 13.gpio_same_csr_outstanding.4214533594 |
| Directory | /workspace/13.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1913338324 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 88887991 ps |
| CPU time | 1.73 seconds |
| Started | Jul 18 05:40:05 PM PDT 24 |
| Finished | Jul 18 05:40:14 PM PDT 24 |
| Peak memory | 198284 kb |
| Host | smart-836512b7-fa0a-4d96-926b-220a938ccf25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913338324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1913338324 |
| Directory | /workspace/13.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3466527971 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 377634407 ps |
| CPU time | 1.18 seconds |
| Started | Jul 18 05:40:01 PM PDT 24 |
| Finished | Jul 18 05:40:09 PM PDT 24 |
| Peak memory | 198244 kb |
| Host | smart-93c7293e-a36c-420b-b2f4-5adba17fd7b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466527971 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 13.gpio_tl_intg_err.3466527971 |
| Directory | /workspace/13.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.4067154128 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 19982248 ps |
| CPU time | 0.9 seconds |
| Started | Jul 18 05:40:01 PM PDT 24 |
| Finished | Jul 18 05:40:08 PM PDT 24 |
| Peak memory | 198204 kb |
| Host | smart-c7bc96a1-412a-4835-ba11-16dc8e92da8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067154128 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.4067154128 |
| Directory | /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1117875719 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 106933548 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:25 PM PDT 24 |
| Peak memory | 193520 kb |
| Host | smart-6b2ee53a-50d4-427f-8bcb-9417de2d6a99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117875719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi o_csr_rw.1117875719 |
| Directory | /workspace/14.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_intr_test.262337356 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 37300243 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:39:59 PM PDT 24 |
| Finished | Jul 18 05:40:03 PM PDT 24 |
| Peak memory | 193904 kb |
| Host | smart-128c1283-e5c4-4665-833f-cf05ea14ac46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262337356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.262337356 |
| Directory | /workspace/14.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1990336412 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 109940451 ps |
| CPU time | 0.76 seconds |
| Started | Jul 18 05:40:06 PM PDT 24 |
| Finished | Jul 18 05:40:13 PM PDT 24 |
| Peak memory | 196200 kb |
| Host | smart-5a251c04-088c-414e-8fc5-045c66c5a416 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990336412 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 14.gpio_same_csr_outstanding.1990336412 |
| Directory | /workspace/14.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_tl_errors.957758967 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 356028721 ps |
| CPU time | 2.38 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:26 PM PDT 24 |
| Peak memory | 198300 kb |
| Host | smart-0dd6b793-4450-40ed-a356-7fa5d0c35613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957758967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.957758967 |
| Directory | /workspace/14.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.212361617 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 79645397 ps |
| CPU time | 1.17 seconds |
| Started | Jul 18 05:40:04 PM PDT 24 |
| Finished | Jul 18 05:40:12 PM PDT 24 |
| Peak memory | 198304 kb |
| Host | smart-803c0726-cf22-42f3-a6a8-284a2274c569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212361617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.gpio_tl_intg_err.212361617 |
| Directory | /workspace/14.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.709356602 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 102871491 ps |
| CPU time | 1.61 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:25 PM PDT 24 |
| Peak memory | 198416 kb |
| Host | smart-3fb54c0d-770b-4585-8e61-11b7f18f9509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709356602 -asser t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.709356602 |
| Directory | /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1620371814 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 48403061 ps |
| CPU time | 0.61 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:24 PM PDT 24 |
| Peak memory | 194916 kb |
| Host | smart-a80ae5e6-69b7-4218-bc01-449f69fa7d16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620371814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi o_csr_rw.1620371814 |
| Directory | /workspace/15.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_intr_test.1974764972 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 14689108 ps |
| CPU time | 0.6 seconds |
| Started | Jul 18 05:39:58 PM PDT 24 |
| Finished | Jul 18 05:40:01 PM PDT 24 |
| Peak memory | 193908 kb |
| Host | smart-a8688c6a-3d09-42c3-92f8-1f6545d6beeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974764972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1974764972 |
| Directory | /workspace/15.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.701575731 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 36579640 ps |
| CPU time | 0.89 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:05 PM PDT 24 |
| Peak memory | 198096 kb |
| Host | smart-85fd0a74-809e-4c70-b5de-05a1cb9f8a49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701575731 -assert nopostproc +UVM_TESTNAME=gpio_bas e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 15.gpio_same_csr_outstanding.701575731 |
| Directory | /workspace/15.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_tl_errors.829827938 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 32371176 ps |
| CPU time | 1.06 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:24 PM PDT 24 |
| Peak memory | 198132 kb |
| Host | smart-2f4af727-cd47-4fc8-84ee-ca0c40b000a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829827938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.829827938 |
| Directory | /workspace/15.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3815084818 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 221182848 ps |
| CPU time | 1.43 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:26 PM PDT 24 |
| Peak memory | 198312 kb |
| Host | smart-00e52154-878e-4126-ba65-a00c7c600df0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815084818 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 15.gpio_tl_intg_err.3815084818 |
| Directory | /workspace/15.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.4266771153 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 71267245 ps |
| CPU time | 0.74 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:25 PM PDT 24 |
| Peak memory | 198104 kb |
| Host | smart-756b6799-be9f-4f45-9f3d-43a2f929ffda |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266771153 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.4266771153 |
| Directory | /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_csr_rw.915508533 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 25343242 ps |
| CPU time | 0.6 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:25 PM PDT 24 |
| Peak memory | 194248 kb |
| Host | smart-99c6a7e5-f3fe-4a88-9e18-a58877a1008b |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915508533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio _csr_rw.915508533 |
| Directory | /workspace/16.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_intr_test.2307316825 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 18218094 ps |
| CPU time | 0.61 seconds |
| Started | Jul 18 05:40:08 PM PDT 24 |
| Finished | Jul 18 05:40:14 PM PDT 24 |
| Peak memory | 194052 kb |
| Host | smart-e65f0540-685a-4776-8151-f73745eef3b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307316825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2307316825 |
| Directory | /workspace/16.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3334652979 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 14685147 ps |
| CPU time | 0.64 seconds |
| Started | Jul 18 05:40:08 PM PDT 24 |
| Finished | Jul 18 05:40:15 PM PDT 24 |
| Peak memory | 194972 kb |
| Host | smart-f780c407-cf14-4a35-aba1-4025226346d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334652979 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 16.gpio_same_csr_outstanding.3334652979 |
| Directory | /workspace/16.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2072845885 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 468208870 ps |
| CPU time | 2.51 seconds |
| Started | Jul 18 05:40:08 PM PDT 24 |
| Finished | Jul 18 05:40:17 PM PDT 24 |
| Peak memory | 198264 kb |
| Host | smart-a8479561-425d-4813-a10c-489ca5ea48bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072845885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2072845885 |
| Directory | /workspace/16.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3277064578 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 88527664 ps |
| CPU time | 1.21 seconds |
| Started | Jul 18 05:40:17 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 198268 kb |
| Host | smart-08eccace-f831-4dd6-8452-3a7131ef714a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277064578 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 16.gpio_tl_intg_err.3277064578 |
| Directory | /workspace/16.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3925559078 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 20719461 ps |
| CPU time | 0.73 seconds |
| Started | Jul 18 05:40:08 PM PDT 24 |
| Finished | Jul 18 05:40:15 PM PDT 24 |
| Peak memory | 198164 kb |
| Host | smart-9df949a5-7a72-42df-9778-4e5a017fd3db |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925559078 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3925559078 |
| Directory | /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1163365623 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 16294899 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:40:09 PM PDT 24 |
| Finished | Jul 18 05:40:16 PM PDT 24 |
| Peak memory | 194524 kb |
| Host | smart-1f8aa73b-7892-4219-a1e2-76c813e2c6d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163365623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi o_csr_rw.1163365623 |
| Directory | /workspace/17.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_intr_test.4075888329 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 23454023 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:06 PM PDT 24 |
| Peak memory | 194636 kb |
| Host | smart-50cb13e6-d0c4-42fd-811b-7452e962c103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075888329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.4075888329 |
| Directory | /workspace/17.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1744066030 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 21430144 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:26 PM PDT 24 |
| Peak memory | 197912 kb |
| Host | smart-7fbcd31f-608d-483e-82b7-1cd51d7552a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744066030 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 17.gpio_same_csr_outstanding.1744066030 |
| Directory | /workspace/17.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_tl_errors.269456704 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 41507636 ps |
| CPU time | 2.08 seconds |
| Started | Jul 18 05:40:09 PM PDT 24 |
| Finished | Jul 18 05:40:18 PM PDT 24 |
| Peak memory | 198268 kb |
| Host | smart-452dfe43-26e0-4201-b7c8-15ab27ff6804 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269456704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.269456704 |
| Directory | /workspace/17.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.448732252 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 374766199 ps |
| CPU time | 1.38 seconds |
| Started | Jul 18 05:40:08 PM PDT 24 |
| Finished | Jul 18 05:40:15 PM PDT 24 |
| Peak memory | 198264 kb |
| Host | smart-d10e3aad-9993-41d7-9aec-5d52a43384eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448732252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.gpio_tl_intg_err.448732252 |
| Directory | /workspace/17.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1004184396 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 60295949 ps |
| CPU time | 0.78 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:07 PM PDT 24 |
| Peak memory | 198292 kb |
| Host | smart-6be2dec3-58d1-42f7-b908-b2c14556d231 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004184396 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1004184396 |
| Directory | /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4146124529 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 12189209 ps |
| CPU time | 0.61 seconds |
| Started | Jul 18 05:40:01 PM PDT 24 |
| Finished | Jul 18 05:40:07 PM PDT 24 |
| Peak memory | 195284 kb |
| Host | smart-aa168e73-bbcc-41ea-ad91-852949df1bff |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146124529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi o_csr_rw.4146124529 |
| Directory | /workspace/18.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_intr_test.472500297 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 21508631 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:40:08 PM PDT 24 |
| Finished | Jul 18 05:40:15 PM PDT 24 |
| Peak memory | 194700 kb |
| Host | smart-fb1dbecf-8aa7-4aab-8271-db5b2dd12172 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472500297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.472500297 |
| Directory | /workspace/18.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3770883985 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 27169343 ps |
| CPU time | 0.65 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:06 PM PDT 24 |
| Peak memory | 195888 kb |
| Host | smart-c201801d-cf1f-412e-82bf-d33a0e85d7f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770883985 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 18.gpio_same_csr_outstanding.3770883985 |
| Directory | /workspace/18.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1878152061 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 78849557 ps |
| CPU time | 1.51 seconds |
| Started | Jul 18 05:40:09 PM PDT 24 |
| Finished | Jul 18 05:40:16 PM PDT 24 |
| Peak memory | 198364 kb |
| Host | smart-b85a99da-35a7-4e02-86bc-96a234c3e995 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878152061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1878152061 |
| Directory | /workspace/18.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2107947389 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 108209171 ps |
| CPU time | 0.86 seconds |
| Started | Jul 18 05:40:17 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 198072 kb |
| Host | smart-50fa82b4-d2ee-450c-9730-87aac183c1a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107947389 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2107947389 |
| Directory | /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2869795932 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 13806801 ps |
| CPU time | 0.62 seconds |
| Started | Jul 18 05:40:08 PM PDT 24 |
| Finished | Jul 18 05:40:15 PM PDT 24 |
| Peak memory | 194892 kb |
| Host | smart-edd6b11d-d117-48a1-8bf8-af7ba66ed176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869795932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi o_csr_rw.2869795932 |
| Directory | /workspace/19.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_intr_test.1732886560 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 16306361 ps |
| CPU time | 0.64 seconds |
| Started | Jul 18 05:40:16 PM PDT 24 |
| Finished | Jul 18 05:40:26 PM PDT 24 |
| Peak memory | 194092 kb |
| Host | smart-9e213f58-5acd-4f7a-916e-a87834147e6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732886560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1732886560 |
| Directory | /workspace/19.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3315374268 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 57949944 ps |
| CPU time | 0.78 seconds |
| Started | Jul 18 05:40:13 PM PDT 24 |
| Finished | Jul 18 05:40:23 PM PDT 24 |
| Peak memory | 196896 kb |
| Host | smart-22c7ea30-e305-4d66-baa6-0015ad9a8f1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315374268 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 19.gpio_same_csr_outstanding.3315374268 |
| Directory | /workspace/19.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3341775010 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 38136128 ps |
| CPU time | 1.81 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:26 PM PDT 24 |
| Peak memory | 198348 kb |
| Host | smart-5b395318-9428-4937-81d2-38b8ba6fc80e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341775010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3341775010 |
| Directory | /workspace/19.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2844991598 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 309287218 ps |
| CPU time | 1.11 seconds |
| Started | Jul 18 05:40:13 PM PDT 24 |
| Finished | Jul 18 05:40:23 PM PDT 24 |
| Peak memory | 198508 kb |
| Host | smart-6906996e-3e00-4383-b50e-635c6d048687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844991598 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 19.gpio_tl_intg_err.2844991598 |
| Directory | /workspace/19.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.4074602125 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 70035385 ps |
| CPU time | 0.69 seconds |
| Started | Jul 18 05:39:46 PM PDT 24 |
| Finished | Jul 18 05:39:52 PM PDT 24 |
| Peak memory | 195500 kb |
| Host | smart-62a7105a-47bc-42cd-8b28-66c90863eb7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074602125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_aliasing.4074602125 |
| Directory | /workspace/2.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1304466112 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 104825582 ps |
| CPU time | 1.55 seconds |
| Started | Jul 18 05:39:55 PM PDT 24 |
| Finished | Jul 18 05:39:59 PM PDT 24 |
| Peak memory | 198044 kb |
| Host | smart-0e0d4459-c5c0-4409-af2c-e0d9478bfc16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304466112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1304466112 |
| Directory | /workspace/2.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1377650216 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 13616310 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:39:58 PM PDT 24 |
| Finished | Jul 18 05:40:01 PM PDT 24 |
| Peak memory | 194584 kb |
| Host | smart-f49a118b-b289-48d3-8bf4-52ba47b26a50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377650216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1377650216 |
| Directory | /workspace/2.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1643832800 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 242820160 ps |
| CPU time | 0.89 seconds |
| Started | Jul 18 05:39:48 PM PDT 24 |
| Finished | Jul 18 05:39:55 PM PDT 24 |
| Peak memory | 198368 kb |
| Host | smart-f032de2f-f50c-49fb-9376-702fb5273571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643832800 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1643832800 |
| Directory | /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3187365696 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 15032987 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:39:58 PM PDT 24 |
| Finished | Jul 18 05:40:01 PM PDT 24 |
| Peak memory | 195164 kb |
| Host | smart-2d551933-1be4-4248-9bec-25c616377f2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187365696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio _csr_rw.3187365696 |
| Directory | /workspace/2.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_intr_test.1556984593 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 10690261 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:39:58 PM PDT 24 |
| Finished | Jul 18 05:40:01 PM PDT 24 |
| Peak memory | 194292 kb |
| Host | smart-577bddee-3f67-4c6a-a1ef-5cda2e46d7b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556984593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1556984593 |
| Directory | /workspace/2.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4030674926 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 36524406 ps |
| CPU time | 0.8 seconds |
| Started | Jul 18 05:39:47 PM PDT 24 |
| Finished | Jul 18 05:39:54 PM PDT 24 |
| Peak memory | 196308 kb |
| Host | smart-197cf48e-836a-4fa5-a687-6e78a205c7ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030674926 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.gpio_same_csr_outstanding.4030674926 |
| Directory | /workspace/2.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2539474135 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 24435220 ps |
| CPU time | 1.3 seconds |
| Started | Jul 18 05:39:49 PM PDT 24 |
| Finished | Jul 18 05:39:56 PM PDT 24 |
| Peak memory | 198476 kb |
| Host | smart-714bedf1-1d0e-4afb-a16a-a7b2977c8ef4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539474135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2539474135 |
| Directory | /workspace/2.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2157055099 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 137243789 ps |
| CPU time | 1.42 seconds |
| Started | Jul 18 05:39:48 PM PDT 24 |
| Finished | Jul 18 05:39:55 PM PDT 24 |
| Peak memory | 198276 kb |
| Host | smart-72de8769-973d-4229-aec2-81c410a74af9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157055099 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.gpio_tl_intg_err.2157055099 |
| Directory | /workspace/2.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.gpio_intr_test.3183420407 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 125565765 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:40:16 PM PDT 24 |
| Finished | Jul 18 05:40:26 PM PDT 24 |
| Peak memory | 194012 kb |
| Host | smart-2e97372b-affc-4aed-add0-7eb4bc962f39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183420407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3183420407 |
| Directory | /workspace/20.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.gpio_intr_test.2013156869 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 30186149 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:40:27 PM PDT 24 |
| Finished | Jul 18 05:40:35 PM PDT 24 |
| Peak memory | 194684 kb |
| Host | smart-2e707763-5bbe-4ab0-9c14-a5b200022cb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013156869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2013156869 |
| Directory | /workspace/21.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.gpio_intr_test.71957043 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 41182437 ps |
| CPU time | 0.6 seconds |
| Started | Jul 18 05:40:13 PM PDT 24 |
| Finished | Jul 18 05:40:23 PM PDT 24 |
| Peak memory | 194592 kb |
| Host | smart-a8ee20e1-46bf-4a7a-a5b3-3596b7c329db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71957043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.71957043 |
| Directory | /workspace/22.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.gpio_intr_test.1602920629 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 50544765 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:40:16 PM PDT 24 |
| Finished | Jul 18 05:40:27 PM PDT 24 |
| Peak memory | 194020 kb |
| Host | smart-729d8f5a-b026-4e36-99b3-5516d2baf63d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602920629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1602920629 |
| Directory | /workspace/23.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.gpio_intr_test.1851986152 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 117435596 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:26 PM PDT 24 |
| Peak memory | 193936 kb |
| Host | smart-e933245c-267a-44bf-82dd-d5565fab9836 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851986152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1851986152 |
| Directory | /workspace/24.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.gpio_intr_test.3643337449 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 11990289 ps |
| CPU time | 0.64 seconds |
| Started | Jul 18 05:40:17 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 193924 kb |
| Host | smart-3b252b01-2d14-4e8a-9332-f9c23d6b0fab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643337449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3643337449 |
| Directory | /workspace/25.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.gpio_intr_test.2664859842 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 41388604 ps |
| CPU time | 0.64 seconds |
| Started | Jul 18 05:40:13 PM PDT 24 |
| Finished | Jul 18 05:40:23 PM PDT 24 |
| Peak memory | 193936 kb |
| Host | smart-2f8300fe-9c87-4f2c-a1ba-ef2dde923129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664859842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2664859842 |
| Directory | /workspace/26.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.gpio_intr_test.4178065087 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 34753167 ps |
| CPU time | 0.64 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:23 PM PDT 24 |
| Peak memory | 194052 kb |
| Host | smart-bf9fca66-16dc-4019-8659-f847080a5de7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178065087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.4178065087 |
| Directory | /workspace/27.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.gpio_intr_test.3560440877 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 26266594 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:26 PM PDT 24 |
| Peak memory | 193996 kb |
| Host | smart-b17c664b-c8d6-4d8d-b26e-0d80cf74073e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560440877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3560440877 |
| Directory | /workspace/28.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.gpio_intr_test.90996723 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 11591536 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:23 PM PDT 24 |
| Peak memory | 194652 kb |
| Host | smart-92d656d3-f2cf-4403-9b1f-e8f41881b77a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90996723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.90996723 |
| Directory | /workspace/29.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3417707859 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 79612621 ps |
| CPU time | 0.71 seconds |
| Started | Jul 18 05:39:50 PM PDT 24 |
| Finished | Jul 18 05:39:56 PM PDT 24 |
| Peak memory | 195136 kb |
| Host | smart-c3d8208a-8918-4c4f-9f4e-4acef05a151e |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417707859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_aliasing.3417707859 |
| Directory | /workspace/3.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4161723000 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 34939900 ps |
| CPU time | 1.37 seconds |
| Started | Jul 18 05:39:50 PM PDT 24 |
| Finished | Jul 18 05:39:57 PM PDT 24 |
| Peak memory | 196976 kb |
| Host | smart-c63f3ee6-b13f-4b84-8a9b-96d4aca5879e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161723000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.4161723000 |
| Directory | /workspace/3.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.760250331 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 33958310 ps |
| CPU time | 0.65 seconds |
| Started | Jul 18 05:39:53 PM PDT 24 |
| Finished | Jul 18 05:39:57 PM PDT 24 |
| Peak memory | 195216 kb |
| Host | smart-d6caa239-6767-4030-af2a-88fdb5708280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760250331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.760250331 |
| Directory | /workspace/3.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.4015596263 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 126741306 ps |
| CPU time | 0.77 seconds |
| Started | Jul 18 05:39:47 PM PDT 24 |
| Finished | Jul 18 05:39:54 PM PDT 24 |
| Peak memory | 198156 kb |
| Host | smart-21584252-ed09-424a-88bb-851d2f2a7ec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015596263 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.4015596263 |
| Directory | /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3582122493 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 43401324 ps |
| CPU time | 0.55 seconds |
| Started | Jul 18 05:41:36 PM PDT 24 |
| Finished | Jul 18 05:41:52 PM PDT 24 |
| Peak memory | 193492 kb |
| Host | smart-754ac9dc-c1d4-4c43-8d9c-a2fc37b310e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582122493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio _csr_rw.3582122493 |
| Directory | /workspace/3.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_intr_test.194068923 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 26940489 ps |
| CPU time | 0.61 seconds |
| Started | Jul 18 05:39:48 PM PDT 24 |
| Finished | Jul 18 05:39:54 PM PDT 24 |
| Peak memory | 193976 kb |
| Host | smart-4fc8563a-9c6b-4cdf-8e94-d7a4462c2a03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194068923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.194068923 |
| Directory | /workspace/3.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1539711332 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 208739296 ps |
| CPU time | 0.85 seconds |
| Started | Jul 18 05:39:58 PM PDT 24 |
| Finished | Jul 18 05:40:01 PM PDT 24 |
| Peak memory | 197228 kb |
| Host | smart-53a3084a-db9c-493d-8414-872ea3b420c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539711332 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.gpio_same_csr_outstanding.1539711332 |
| Directory | /workspace/3.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3666325110 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 488755051 ps |
| CPU time | 1.45 seconds |
| Started | Jul 18 05:39:46 PM PDT 24 |
| Finished | Jul 18 05:39:53 PM PDT 24 |
| Peak memory | 198284 kb |
| Host | smart-51806543-dd7b-461a-bfea-9c9c33dcabbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666325110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3666325110 |
| Directory | /workspace/3.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.34867971 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 79381683 ps |
| CPU time | 0.97 seconds |
| Started | Jul 18 05:39:44 PM PDT 24 |
| Finished | Jul 18 05:39:49 PM PDT 24 |
| Peak memory | 197516 kb |
| Host | smart-aa1c0cb4-f75c-4d37-ac66-95db1e27b9c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34867971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_intg_err.34867971 |
| Directory | /workspace/3.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.gpio_intr_test.2609929998 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 15464913 ps |
| CPU time | 0.62 seconds |
| Started | Jul 18 05:40:13 PM PDT 24 |
| Finished | Jul 18 05:40:23 PM PDT 24 |
| Peak memory | 193996 kb |
| Host | smart-3f8ab2d2-85d6-41c9-b15c-25b117fc5764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609929998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2609929998 |
| Directory | /workspace/30.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.gpio_intr_test.3970885573 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 32753455 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:40:13 PM PDT 24 |
| Finished | Jul 18 05:40:23 PM PDT 24 |
| Peak memory | 193936 kb |
| Host | smart-53f0cbc8-03ad-44a8-be75-68a6f6e35915 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970885573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3970885573 |
| Directory | /workspace/31.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.gpio_intr_test.2368710174 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 13575904 ps |
| CPU time | 0.64 seconds |
| Started | Jul 18 05:40:12 PM PDT 24 |
| Finished | Jul 18 05:40:21 PM PDT 24 |
| Peak memory | 194000 kb |
| Host | smart-6a377ea1-bcd6-415f-81ed-2573b9fd177e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368710174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2368710174 |
| Directory | /workspace/32.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.gpio_intr_test.1848945804 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 13704587 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:40:17 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 194588 kb |
| Host | smart-ab60c600-bb30-4320-b01c-1b53f757b80a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848945804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1848945804 |
| Directory | /workspace/33.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.gpio_intr_test.3662022971 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 16660556 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:40:13 PM PDT 24 |
| Finished | Jul 18 05:40:23 PM PDT 24 |
| Peak memory | 193984 kb |
| Host | smart-f3328579-20d4-43d3-8961-786e928d55ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662022971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3662022971 |
| Directory | /workspace/34.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.gpio_intr_test.3946150412 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 33214263 ps |
| CPU time | 0.74 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:24 PM PDT 24 |
| Peak memory | 193996 kb |
| Host | smart-5c5764ed-c414-4192-ab1c-c846bbf522a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946150412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3946150412 |
| Directory | /workspace/35.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.gpio_intr_test.3802078419 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 25962676 ps |
| CPU time | 0.62 seconds |
| Started | Jul 18 05:40:20 PM PDT 24 |
| Finished | Jul 18 05:40:30 PM PDT 24 |
| Peak memory | 194016 kb |
| Host | smart-ae154994-fb64-4102-a8bd-c41a0c7e34de |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802078419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3802078419 |
| Directory | /workspace/36.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.gpio_intr_test.2534851697 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 97512419 ps |
| CPU time | 0.65 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:23 PM PDT 24 |
| Peak memory | 194068 kb |
| Host | smart-b6d1824c-216c-49d8-9047-7119d7e48411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534851697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2534851697 |
| Directory | /workspace/37.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.gpio_intr_test.4120215736 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 14278997 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:40:11 PM PDT 24 |
| Finished | Jul 18 05:40:20 PM PDT 24 |
| Peak memory | 194048 kb |
| Host | smart-8dad1b84-84b9-4fbb-aec6-1aae37bf0dd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120215736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.4120215736 |
| Directory | /workspace/38.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.gpio_intr_test.2825344695 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 56513943 ps |
| CPU time | 0.6 seconds |
| Started | Jul 18 05:40:16 PM PDT 24 |
| Finished | Jul 18 05:40:27 PM PDT 24 |
| Peak memory | 193992 kb |
| Host | smart-05f50b9c-c86b-4ea2-a339-33aeee2e4ad1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825344695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2825344695 |
| Directory | /workspace/39.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2892197765 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 99804645 ps |
| CPU time | 0.8 seconds |
| Started | Jul 18 05:39:59 PM PDT 24 |
| Finished | Jul 18 05:40:04 PM PDT 24 |
| Peak memory | 196972 kb |
| Host | smart-a706153e-273a-4dd2-9d3b-e5f8f2dfd6c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892197765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM _TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_aliasing.2892197765 |
| Directory | /workspace/4.gpio_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4118251434 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 1121930528 ps |
| CPU time | 3.43 seconds |
| Started | Jul 18 05:39:57 PM PDT 24 |
| Finished | Jul 18 05:40:03 PM PDT 24 |
| Peak memory | 197176 kb |
| Host | smart-ad84bce7-b507-4d80-afb9-f7e7d4be3b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118251434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4118251434 |
| Directory | /workspace/4.gpio_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3781371967 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 15394507 ps |
| CPU time | 0.62 seconds |
| Started | Jul 18 05:40:17 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 195244 kb |
| Host | smart-dff8c8a6-af93-414d-81c3-eb6f93aa730f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781371967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3781371967 |
| Directory | /workspace/4.gpio_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.373830725 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 57760720 ps |
| CPU time | 0.67 seconds |
| Started | Jul 18 05:40:01 PM PDT 24 |
| Finished | Jul 18 05:40:07 PM PDT 24 |
| Peak memory | 196552 kb |
| Host | smart-9b9e8494-b589-4c23-9d18-40d917213f1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373830725 -asser t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.373830725 |
| Directory | /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_csr_rw.836698856 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 15849219 ps |
| CPU time | 0.62 seconds |
| Started | Jul 18 05:39:49 PM PDT 24 |
| Finished | Jul 18 05:39:56 PM PDT 24 |
| Peak memory | 193744 kb |
| Host | smart-df64ee67-ff1a-4ad1-a217-3eecbe36fe69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836698856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_ csr_rw.836698856 |
| Directory | /workspace/4.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_intr_test.842475373 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 16739140 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:39:59 PM PDT 24 |
| Finished | Jul 18 05:40:03 PM PDT 24 |
| Peak memory | 193916 kb |
| Host | smart-b27c925e-4582-43c7-bd12-ae77796c093f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842475373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.842475373 |
| Directory | /workspace/4.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3308440491 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 24315832 ps |
| CPU time | 0.71 seconds |
| Started | Jul 18 05:39:55 PM PDT 24 |
| Finished | Jul 18 05:39:58 PM PDT 24 |
| Peak memory | 195084 kb |
| Host | smart-1355e2b7-1269-4bdc-9027-abd60fee9757 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308440491 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.gpio_same_csr_outstanding.3308440491 |
| Directory | /workspace/4.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1418253730 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 90956966 ps |
| CPU time | 1.39 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:06 PM PDT 24 |
| Peak memory | 198324 kb |
| Host | smart-f307375f-4454-4d08-8f26-83f7f6ec10c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418253730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1418253730 |
| Directory | /workspace/4.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.784770545 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 476648107 ps |
| CPU time | 1.19 seconds |
| Started | Jul 18 05:40:01 PM PDT 24 |
| Finished | Jul 18 05:40:07 PM PDT 24 |
| Peak memory | 198248 kb |
| Host | smart-cbd78d88-fb33-4628-9e0b-eaa75e7464f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784770545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.gpio_tl_intg_err.784770545 |
| Directory | /workspace/4.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.gpio_intr_test.823135933 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 50029019 ps |
| CPU time | 0.7 seconds |
| Started | Jul 18 05:40:17 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 193956 kb |
| Host | smart-b920ee86-5f2e-402e-b7fb-296c9d7fd894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823135933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.823135933 |
| Directory | /workspace/40.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.gpio_intr_test.773135289 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 50748236 ps |
| CPU time | 0.57 seconds |
| Started | Jul 18 05:40:27 PM PDT 24 |
| Finished | Jul 18 05:40:35 PM PDT 24 |
| Peak memory | 193972 kb |
| Host | smart-eead6d63-0b45-42a0-8103-86975e8c63ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773135289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.773135289 |
| Directory | /workspace/41.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.gpio_intr_test.3499489284 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 27764950 ps |
| CPU time | 0.57 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:26 PM PDT 24 |
| Peak memory | 193976 kb |
| Host | smart-ecdd1b10-c393-470c-aaa7-dc3e572b447d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499489284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3499489284 |
| Directory | /workspace/42.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.gpio_intr_test.1909614791 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 14035000 ps |
| CPU time | 0.62 seconds |
| Started | Jul 18 05:40:13 PM PDT 24 |
| Finished | Jul 18 05:40:23 PM PDT 24 |
| Peak memory | 193980 kb |
| Host | smart-b93f238a-e27b-44b5-bfc9-aa59c95ce267 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909614791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1909614791 |
| Directory | /workspace/43.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.gpio_intr_test.4220956119 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 13581868 ps |
| CPU time | 0.64 seconds |
| Started | Jul 18 05:40:13 PM PDT 24 |
| Finished | Jul 18 05:40:23 PM PDT 24 |
| Peak memory | 194664 kb |
| Host | smart-c90641a0-a621-4149-bd5a-3648dcc879ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220956119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.4220956119 |
| Directory | /workspace/44.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.gpio_intr_test.3217838678 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 35813179 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:40:27 PM PDT 24 |
| Finished | Jul 18 05:40:34 PM PDT 24 |
| Peak memory | 194000 kb |
| Host | smart-71ee8797-40c8-4212-a1aa-d044020d705a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217838678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3217838678 |
| Directory | /workspace/45.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.gpio_intr_test.1435310498 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 23930375 ps |
| CPU time | 0.7 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:24 PM PDT 24 |
| Peak memory | 194044 kb |
| Host | smart-30483e16-1d34-4b63-b6b1-90cb28c36888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435310498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1435310498 |
| Directory | /workspace/46.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.gpio_intr_test.171923007 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 19606033 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:40:16 PM PDT 24 |
| Finished | Jul 18 05:40:27 PM PDT 24 |
| Peak memory | 194604 kb |
| Host | smart-a1a17ffe-7dff-4583-822e-68867ab8f7fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171923007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.171923007 |
| Directory | /workspace/47.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.gpio_intr_test.1406699884 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 20885795 ps |
| CPU time | 0.64 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:26 PM PDT 24 |
| Peak memory | 194688 kb |
| Host | smart-901b01fc-c992-45b4-8a68-70de4612b86e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406699884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1406699884 |
| Directory | /workspace/48.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.gpio_intr_test.3004457652 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 57150589 ps |
| CPU time | 0.56 seconds |
| Started | Jul 18 05:40:27 PM PDT 24 |
| Finished | Jul 18 05:40:35 PM PDT 24 |
| Peak memory | 193976 kb |
| Host | smart-a95d31e0-1fb5-405e-89b7-4a5ed9fc1306 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004457652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3004457652 |
| Directory | /workspace/49.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.419319767 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 24633236 ps |
| CPU time | 1.21 seconds |
| Started | Jul 18 05:40:08 PM PDT 24 |
| Finished | Jul 18 05:40:15 PM PDT 24 |
| Peak memory | 198296 kb |
| Host | smart-761b295c-3b08-42ca-9976-d3088155a110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419319767 -asser t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.419319767 |
| Directory | /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1581171282 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 56761461 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:05 PM PDT 24 |
| Peak memory | 194888 kb |
| Host | smart-a1da879e-2a36-4328-b9df-1ca28f695bf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581171282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio _csr_rw.1581171282 |
| Directory | /workspace/5.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_intr_test.197760902 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 39266823 ps |
| CPU time | 0.62 seconds |
| Started | Jul 18 05:39:57 PM PDT 24 |
| Finished | Jul 18 05:40:00 PM PDT 24 |
| Peak memory | 193992 kb |
| Host | smart-8613a0e9-2a90-4798-b6b3-e5ba7f5c88c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197760902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.197760902 |
| Directory | /workspace/5.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1189687635 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 22106690 ps |
| CPU time | 0.74 seconds |
| Started | Jul 18 05:39:57 PM PDT 24 |
| Finished | Jul 18 05:40:00 PM PDT 24 |
| Peak memory | 195432 kb |
| Host | smart-96b095c3-0098-461c-a583-f96c8f67959b |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189687635 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 5.gpio_same_csr_outstanding.1189687635 |
| Directory | /workspace/5.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2746563282 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 248859104 ps |
| CPU time | 2.38 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:08 PM PDT 24 |
| Peak memory | 198248 kb |
| Host | smart-a86d8704-e9d2-4f15-b59d-a2376bf4e5b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746563282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2746563282 |
| Directory | /workspace/5.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.346916651 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 73082045 ps |
| CPU time | 1.17 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:07 PM PDT 24 |
| Peak memory | 198276 kb |
| Host | smart-aa9123df-afda-4419-b6d3-133c78b56579 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346916651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.gpio_tl_intg_err.346916651 |
| Directory | /workspace/5.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2990058947 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 80197264 ps |
| CPU time | 0.71 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:25 PM PDT 24 |
| Peak memory | 197980 kb |
| Host | smart-349c5db1-7fda-4ea5-9399-a650df2cc393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990058947 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2990058947 |
| Directory | /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3354896034 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 42487906 ps |
| CPU time | 0.67 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:07 PM PDT 24 |
| Peak memory | 195812 kb |
| Host | smart-fad46169-de5c-4f40-8fd2-dd9be2523612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354896034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio _csr_rw.3354896034 |
| Directory | /workspace/6.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_intr_test.2650139553 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 36761822 ps |
| CPU time | 0.61 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:06 PM PDT 24 |
| Peak memory | 193968 kb |
| Host | smart-dafc8289-f3cb-40f6-a4f8-9a9c368c74d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650139553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2650139553 |
| Directory | /workspace/6.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1534983824 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 34106520 ps |
| CPU time | 0.64 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:24 PM PDT 24 |
| Peak memory | 194908 kb |
| Host | smart-a82bacfd-3109-45c9-8715-9f71d1c5423a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534983824 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 6.gpio_same_csr_outstanding.1534983824 |
| Directory | /workspace/6.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_tl_errors.841243542 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 241766932 ps |
| CPU time | 1.34 seconds |
| Started | Jul 18 05:47:50 PM PDT 24 |
| Finished | Jul 18 05:47:59 PM PDT 24 |
| Peak memory | 198356 kb |
| Host | smart-2df3890c-3192-4023-9df9-347112e88aec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841243542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.841243542 |
| Directory | /workspace/6.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2725967991 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 434684197 ps |
| CPU time | 1.19 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:07 PM PDT 24 |
| Peak memory | 198276 kb |
| Host | smart-5cf74b8e-1fff-4ca8-896a-8fb040ce5f5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725967991 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 6.gpio_tl_intg_err.2725967991 |
| Directory | /workspace/6.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2782360981 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 32771320 ps |
| CPU time | 0.9 seconds |
| Started | Jul 18 05:39:59 PM PDT 24 |
| Finished | Jul 18 05:40:03 PM PDT 24 |
| Peak memory | 198232 kb |
| Host | smart-16c804b5-0a93-4210-a04c-2d16cf41e6a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782360981 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2782360981 |
| Directory | /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1830454338 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 22525085 ps |
| CPU time | 0.61 seconds |
| Started | Jul 18 05:40:05 PM PDT 24 |
| Finished | Jul 18 05:40:13 PM PDT 24 |
| Peak memory | 195156 kb |
| Host | smart-d87ce5d9-ab73-4344-a9de-ccb928779841 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830454338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio _csr_rw.1830454338 |
| Directory | /workspace/7.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_intr_test.2493282063 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 75658051 ps |
| CPU time | 0.64 seconds |
| Started | Jul 18 05:39:58 PM PDT 24 |
| Finished | Jul 18 05:40:01 PM PDT 24 |
| Peak memory | 194052 kb |
| Host | smart-a8000261-4e3e-494a-a31d-bbcab4b01feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493282063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2493282063 |
| Directory | /workspace/7.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3287189188 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 43389621 ps |
| CPU time | 0.68 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:07 PM PDT 24 |
| Peak memory | 195948 kb |
| Host | smart-308b6d3f-5a71-48da-aaf1-785c1198eb9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287189188 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 7.gpio_same_csr_outstanding.3287189188 |
| Directory | /workspace/7.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3888374716 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 115194493 ps |
| CPU time | 1.54 seconds |
| Started | Jul 18 05:39:58 PM PDT 24 |
| Finished | Jul 18 05:40:02 PM PDT 24 |
| Peak memory | 198336 kb |
| Host | smart-dc2aee23-2bb0-40f4-a8f9-867ee42865f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888374716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3888374716 |
| Directory | /workspace/7.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3318829360 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 261557958 ps |
| CPU time | 1.18 seconds |
| Started | Jul 18 05:40:02 PM PDT 24 |
| Finished | Jul 18 05:40:09 PM PDT 24 |
| Peak memory | 198336 kb |
| Host | smart-59c5a510-347a-41eb-baf9-57ba0bd8bafd |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318829360 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 7.gpio_tl_intg_err.3318829360 |
| Directory | /workspace/7.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2266492031 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 19876991 ps |
| CPU time | 0.92 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:06 PM PDT 24 |
| Peak memory | 198104 kb |
| Host | smart-1eedd265-4fee-40da-92cf-e26ee1255ab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266492031 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2266492031 |
| Directory | /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3999746300 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 122243886 ps |
| CPU time | 0.6 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:06 PM PDT 24 |
| Peak memory | 194152 kb |
| Host | smart-4be8f772-a10f-4c3c-9271-78a8d3904168 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999746300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio _csr_rw.3999746300 |
| Directory | /workspace/8.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_intr_test.3474802474 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 38361520 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:40:07 PM PDT 24 |
| Finished | Jul 18 05:40:13 PM PDT 24 |
| Peak memory | 194040 kb |
| Host | smart-1219b91b-beb2-454c-899b-af28e1974bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474802474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3474802474 |
| Directory | /workspace/8.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1178270625 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 28201708 ps |
| CPU time | 0.72 seconds |
| Started | Jul 18 05:40:17 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 196484 kb |
| Host | smart-5f5ee67c-9935-47f7-91f8-ddb1b3eb0632 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178270625 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 8.gpio_same_csr_outstanding.1178270625 |
| Directory | /workspace/8.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2602094802 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 164544209 ps |
| CPU time | 3.09 seconds |
| Started | Jul 18 05:39:58 PM PDT 24 |
| Finished | Jul 18 05:40:04 PM PDT 24 |
| Peak memory | 198316 kb |
| Host | smart-12298669-e07a-49e9-a4ad-ba8ceb14c6cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602094802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2602094802 |
| Directory | /workspace/8.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.413780488 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 134458942 ps |
| CPU time | 0.88 seconds |
| Started | Jul 18 05:39:59 PM PDT 24 |
| Finished | Jul 18 05:40:03 PM PDT 24 |
| Peak memory | 198036 kb |
| Host | smart-589ce0ba-0c9b-44c9-b3ca-f2338557df15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413780488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.gpio_tl_intg_err.413780488 |
| Directory | /workspace/8.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2213702750 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 21900114 ps |
| CPU time | 0.8 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:07 PM PDT 24 |
| Peak memory | 197872 kb |
| Host | smart-0e61f3dc-9b56-4905-952d-265bb891192f |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213702750 -asse rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2213702750 |
| Directory | /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1297602732 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 15476812 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:40:01 PM PDT 24 |
| Finished | Jul 18 05:40:08 PM PDT 24 |
| Peak memory | 195184 kb |
| Host | smart-0eea32f6-528b-4462-a3d4-42edb6b9c9ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297602732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio _csr_rw.1297602732 |
| Directory | /workspace/9.gpio_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_intr_test.2945551535 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 30246407 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:07 PM PDT 24 |
| Peak memory | 194028 kb |
| Host | smart-1ea3d9ee-7daa-4b08-b5e3-1fe5e4d2fca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945551535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2945551535 |
| Directory | /workspace/9.gpio_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3638884163 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 12764526 ps |
| CPU time | 0.69 seconds |
| Started | Jul 18 05:40:00 PM PDT 24 |
| Finished | Jul 18 05:40:06 PM PDT 24 |
| Peak memory | 194984 kb |
| Host | smart-92409335-cc52-40ae-ae5d-99aab302033a |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638884163 -assert nopostproc +UVM_TESTNAME=gpio_ba se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 9.gpio_same_csr_outstanding.3638884163 |
| Directory | /workspace/9.gpio_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_tl_errors.532454700 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 749315317 ps |
| CPU time | 1.97 seconds |
| Started | Jul 18 05:40:08 PM PDT 24 |
| Finished | Jul 18 05:40:16 PM PDT 24 |
| Peak memory | 198288 kb |
| Host | smart-ca987df3-2acf-4dd3-9551-ec9cb0ba738c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532454700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.532454700 |
| Directory | /workspace/9.gpio_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.4200628903 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 82296837 ps |
| CPU time | 1.24 seconds |
| Started | Jul 18 05:40:02 PM PDT 24 |
| Finished | Jul 18 05:40:09 PM PDT 24 |
| Peak memory | 198324 kb |
| Host | smart-793b696a-5cbd-42ed-ae35-7771594c9ed0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200628903 -assert nopostproc +UVM_TESTNAME=gpio_base_test + UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 9.gpio_tl_intg_err.4200628903 |
| Directory | /workspace/9.gpio_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.gpio_alert_test.697355444 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 42850175 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:40:44 PM PDT 24 |
| Finished | Jul 18 05:40:48 PM PDT 24 |
| Peak memory | 194156 kb |
| Host | smart-eda1ea7b-7148-4040-b9e3-24631ccf6e07 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697355444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.697355444 |
| Directory | /workspace/0.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3880115381 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 19340563 ps |
| CPU time | 0.66 seconds |
| Started | Jul 18 05:40:50 PM PDT 24 |
| Finished | Jul 18 05:40:56 PM PDT 24 |
| Peak memory | 194316 kb |
| Host | smart-d67c479a-38ce-453a-9074-b5ef868e7b49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3880115381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3880115381 |
| Directory | /workspace/0.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/0.gpio_filter_stress.1847409432 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 595368113 ps |
| CPU time | 4.88 seconds |
| Started | Jul 18 05:40:51 PM PDT 24 |
| Finished | Jul 18 05:41:01 PM PDT 24 |
| Peak memory | 196144 kb |
| Host | smart-e2141ab0-f41d-49e8-8859-b73b7281b053 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847409432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres s.1847409432 |
| Directory | /workspace/0.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/0.gpio_full_random.1398225595 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 244708246 ps |
| CPU time | 1.1 seconds |
| Started | Jul 18 05:40:44 PM PDT 24 |
| Finished | Jul 18 05:40:48 PM PDT 24 |
| Peak memory | 197920 kb |
| Host | smart-a85d3b52-f3d7-42b0-bd55-f86ad202f81c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398225595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1398225595 |
| Directory | /workspace/0.gpio_full_random/latest |
| Test location | /workspace/coverage/default/0.gpio_intr_rand_pgm.2078888101 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 221888703 ps |
| CPU time | 0.91 seconds |
| Started | Jul 18 05:40:51 PM PDT 24 |
| Finished | Jul 18 05:40:57 PM PDT 24 |
| Peak memory | 195840 kb |
| Host | smart-123b17a4-4315-475f-9921-0233cdb84fde |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078888101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2078888101 |
| Directory | /workspace/0.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/0.gpio_rand_intr_trigger.216662850 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 79005130 ps |
| CPU time | 2.37 seconds |
| Started | Jul 18 05:40:50 PM PDT 24 |
| Finished | Jul 18 05:40:58 PM PDT 24 |
| Peak memory | 196048 kb |
| Host | smart-8194683f-f0b5-4f94-931e-18f57bea1b11 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216662850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.216662850 |
| Directory | /workspace/0.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/0.gpio_random_dout_din.1108099888 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 44736314 ps |
| CPU time | 0.68 seconds |
| Started | Jul 18 05:40:48 PM PDT 24 |
| Finished | Jul 18 05:40:54 PM PDT 24 |
| Peak memory | 194500 kb |
| Host | smart-1f56b544-248a-4fcb-8308-bf832ad29e28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108099888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1108099888 |
| Directory | /workspace/0.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2324577281 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 23892229 ps |
| CPU time | 0.96 seconds |
| Started | Jul 18 05:40:46 PM PDT 24 |
| Finished | Jul 18 05:40:52 PM PDT 24 |
| Peak memory | 196160 kb |
| Host | smart-fc945ebb-e171-4364-b01c-a875c44b5312 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324577281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup _pulldown.2324577281 |
| Directory | /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.826164367 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 1884116826 ps |
| CPU time | 6.39 seconds |
| Started | Jul 18 05:40:49 PM PDT 24 |
| Finished | Jul 18 05:41:00 PM PDT 24 |
| Peak memory | 198180 kb |
| Host | smart-77f5ff4e-1414-4b47-bed7-a648769538fa |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826164367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand om_long_reg_writes_reg_reads.826164367 |
| Directory | /workspace/0.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/0.gpio_smoke.4137010013 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 22657850 ps |
| CPU time | 0.67 seconds |
| Started | Jul 18 05:40:28 PM PDT 24 |
| Finished | Jul 18 05:40:35 PM PDT 24 |
| Peak memory | 194320 kb |
| Host | smart-15c5cdb3-56aa-4c16-8382-25071afb6c24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137010013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.4137010013 |
| Directory | /workspace/0.gpio_smoke/latest |
| Test location | /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3040172748 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 54353767 ps |
| CPU time | 1.26 seconds |
| Started | Jul 18 05:40:32 PM PDT 24 |
| Finished | Jul 18 05:40:42 PM PDT 24 |
| Peak memory | 197024 kb |
| Host | smart-d648b460-3d35-4c69-a7f2-142bef756a64 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040172748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3040172748 |
| Directory | /workspace/0.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/0.gpio_stress_all.980589500 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 4060108891 ps |
| CPU time | 102.75 seconds |
| Started | Jul 18 05:40:43 PM PDT 24 |
| Finished | Jul 18 05:42:29 PM PDT 24 |
| Peak memory | 198284 kb |
| Host | smart-7f2db6a2-2e1c-4810-94df-863e910cb89b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980589500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp io_stress_all.980589500 |
| Directory | /workspace/0.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3543607436 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 118541395586 ps |
| CPU time | 710.87 seconds |
| Started | Jul 18 05:40:47 PM PDT 24 |
| Finished | Jul 18 05:52:42 PM PDT 24 |
| Peak memory | 198500 kb |
| Host | smart-55875b95-06d8-4a08-ad51-86ccd87c608c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3543607436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3543607436 |
| Directory | /workspace/0.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.gpio_alert_test.1592945132 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 61574923 ps |
| CPU time | 0.61 seconds |
| Started | Jul 18 05:40:46 PM PDT 24 |
| Finished | Jul 18 05:40:51 PM PDT 24 |
| Peak memory | 195100 kb |
| Host | smart-c811ad7d-b7a8-4d55-bfee-aefcb9f26c26 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592945132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1592945132 |
| Directory | /workspace/1.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1740397446 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 29680353 ps |
| CPU time | 0.74 seconds |
| Started | Jul 18 05:40:51 PM PDT 24 |
| Finished | Jul 18 05:40:58 PM PDT 24 |
| Peak memory | 196120 kb |
| Host | smart-4278bb0b-1868-459c-8dd5-61fc4d584106 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740397446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1740397446 |
| Directory | /workspace/1.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/1.gpio_filter_stress.155479811 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 2595069047 ps |
| CPU time | 13.56 seconds |
| Started | Jul 18 05:40:43 PM PDT 24 |
| Finished | Jul 18 05:41:00 PM PDT 24 |
| Peak memory | 198320 kb |
| Host | smart-32c5e77e-7ed3-488f-aea9-dbacf271334f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155479811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress .155479811 |
| Directory | /workspace/1.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/1.gpio_full_random.56860152 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 427227888 ps |
| CPU time | 1.09 seconds |
| Started | Jul 18 05:40:51 PM PDT 24 |
| Finished | Jul 18 05:40:58 PM PDT 24 |
| Peak memory | 196936 kb |
| Host | smart-c77a6379-22b5-46da-9243-14b099e576c9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56860152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.56860152 |
| Directory | /workspace/1.gpio_full_random/latest |
| Test location | /workspace/coverage/default/1.gpio_intr_rand_pgm.1279919774 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 25436339 ps |
| CPU time | 0.72 seconds |
| Started | Jul 18 05:40:51 PM PDT 24 |
| Finished | Jul 18 05:40:57 PM PDT 24 |
| Peak memory | 194560 kb |
| Host | smart-3db79353-4112-44a2-8781-aa8f7a223068 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279919774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1279919774 |
| Directory | /workspace/1.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.791559352 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 311118025 ps |
| CPU time | 0.92 seconds |
| Started | Jul 18 05:40:52 PM PDT 24 |
| Finished | Jul 18 05:40:58 PM PDT 24 |
| Peak memory | 196164 kb |
| Host | smart-3dc09e9a-9da0-4a7c-bcab-ced1f3a3ee62 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791559352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.gpio_intr_with_filter_rand_intr_event.791559352 |
| Directory | /workspace/1.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/1.gpio_rand_intr_trigger.2630266419 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 243974200 ps |
| CPU time | 1.9 seconds |
| Started | Jul 18 05:40:47 PM PDT 24 |
| Finished | Jul 18 05:40:53 PM PDT 24 |
| Peak memory | 197504 kb |
| Host | smart-56851ee5-b263-4355-b00f-ba0fb791c15c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630266419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger. 2630266419 |
| Directory | /workspace/1.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/1.gpio_random_dout_din.1118380109 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 34197512 ps |
| CPU time | 1.29 seconds |
| Started | Jul 18 05:40:48 PM PDT 24 |
| Finished | Jul 18 05:40:55 PM PDT 24 |
| Peak memory | 198240 kb |
| Host | smart-b5f726c8-b5f2-4963-be16-fb54c76b8dd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1118380109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1118380109 |
| Directory | /workspace/1.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.562278355 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 103414151 ps |
| CPU time | 0.79 seconds |
| Started | Jul 18 05:40:50 PM PDT 24 |
| Finished | Jul 18 05:40:56 PM PDT 24 |
| Peak memory | 195524 kb |
| Host | smart-d899e03b-4323-455c-ac2a-9fd4dfba2d2d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562278355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_ pulldown.562278355 |
| Directory | /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3369495087 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 373979534 ps |
| CPU time | 5.69 seconds |
| Started | Jul 18 05:40:44 PM PDT 24 |
| Finished | Jul 18 05:40:53 PM PDT 24 |
| Peak memory | 198192 kb |
| Host | smart-7d048d0d-4dc4-4ec7-b3f3-512d41210c8c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369495087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran dom_long_reg_writes_reg_reads.3369495087 |
| Directory | /workspace/1.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/1.gpio_sec_cm.591865499 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 100946350 ps |
| CPU time | 0.93 seconds |
| Started | Jul 18 05:40:45 PM PDT 24 |
| Finished | Jul 18 05:40:49 PM PDT 24 |
| Peak memory | 215316 kb |
| Host | smart-64a0bb14-2294-42a6-851a-f64fd28fb7f8 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591865499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.591865499 |
| Directory | /workspace/1.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/1.gpio_smoke.3228488566 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 73184193 ps |
| CPU time | 1.43 seconds |
| Started | Jul 18 05:40:50 PM PDT 24 |
| Finished | Jul 18 05:40:57 PM PDT 24 |
| Peak memory | 196948 kb |
| Host | smart-2f73b636-8f94-46e2-a195-7657f8126687 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3228488566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3228488566 |
| Directory | /workspace/1.gpio_smoke/latest |
| Test location | /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3292561266 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 62082604 ps |
| CPU time | 0.88 seconds |
| Started | Jul 18 05:40:51 PM PDT 24 |
| Finished | Jul 18 05:40:57 PM PDT 24 |
| Peak memory | 196316 kb |
| Host | smart-83128202-8aac-430a-99b1-5c420c2da34c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292561266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3292561266 |
| Directory | /workspace/1.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/1.gpio_stress_all.2205633395 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2159778345 ps |
| CPU time | 64.1 seconds |
| Started | Jul 18 05:40:47 PM PDT 24 |
| Finished | Jul 18 05:41:55 PM PDT 24 |
| Peak memory | 198340 kb |
| Host | smart-677fc2e1-f8b4-4ec2-a23c-af481a4e0f54 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205633395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g pio_stress_all.2205633395 |
| Directory | /workspace/1.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/10.gpio_alert_test.3936013003 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 37518161 ps |
| CPU time | 0.56 seconds |
| Started | Jul 18 05:41:14 PM PDT 24 |
| Finished | Jul 18 05:41:22 PM PDT 24 |
| Peak memory | 194372 kb |
| Host | smart-253180b7-5966-4f74-b185-850959d11ce0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936013003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3936013003 |
| Directory | /workspace/10.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1349497044 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 196426963 ps |
| CPU time | 0.92 seconds |
| Started | Jul 18 05:41:13 PM PDT 24 |
| Finished | Jul 18 05:41:22 PM PDT 24 |
| Peak memory | 196092 kb |
| Host | smart-622aa158-55da-4dfa-b33f-8433bb77e263 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349497044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1349497044 |
| Directory | /workspace/10.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/10.gpio_filter_stress.3057189136 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 295201278 ps |
| CPU time | 14.78 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:28 PM PDT 24 |
| Peak memory | 197004 kb |
| Host | smart-f5385a1e-2da4-4245-ab64-f55334f6125d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057189136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre ss.3057189136 |
| Directory | /workspace/10.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/10.gpio_full_random.2814456401 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 47369509 ps |
| CPU time | 0.94 seconds |
| Started | Jul 18 05:41:09 PM PDT 24 |
| Finished | Jul 18 05:41:14 PM PDT 24 |
| Peak memory | 198140 kb |
| Host | smart-05b5fe76-536f-4ef2-ad10-a9b21921c118 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814456401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2814456401 |
| Directory | /workspace/10.gpio_full_random/latest |
| Test location | /workspace/coverage/default/10.gpio_intr_rand_pgm.4017500016 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 373508398 ps |
| CPU time | 1.39 seconds |
| Started | Jul 18 05:41:07 PM PDT 24 |
| Finished | Jul 18 05:41:10 PM PDT 24 |
| Peak memory | 197360 kb |
| Host | smart-54b11085-bb0d-4b29-9d53-d2cf9f640a17 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017500016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.4017500016 |
| Directory | /workspace/10.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3686462910 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 23478089 ps |
| CPU time | 1.07 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:19 PM PDT 24 |
| Peak memory | 197164 kb |
| Host | smart-cbec9c96-15fe-4f5d-8011-908d8041d574 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686462910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3686462910 |
| Directory | /workspace/10.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/10.gpio_rand_intr_trigger.2728660994 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 156745044 ps |
| CPU time | 1.8 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:12 PM PDT 24 |
| Peak memory | 196360 kb |
| Host | smart-92c46c38-954f-42e2-8091-2cad6653d423 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728660994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger .2728660994 |
| Directory | /workspace/10.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/10.gpio_random_dout_din.317176367 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 110006727 ps |
| CPU time | 1.29 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:20 PM PDT 24 |
| Peak memory | 197152 kb |
| Host | smart-5fd1e034-541a-4f1c-bbef-8de034b061ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=317176367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.317176367 |
| Directory | /workspace/10.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.4252498883 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 120473514 ps |
| CPU time | 0.82 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:20 PM PDT 24 |
| Peak memory | 195612 kb |
| Host | smart-6f361606-257a-4bc3-9c06-461fb560d6d2 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252498883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu p_pulldown.4252498883 |
| Directory | /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1842593848 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 552797874 ps |
| CPU time | 1.53 seconds |
| Started | Jul 18 05:41:14 PM PDT 24 |
| Finished | Jul 18 05:41:23 PM PDT 24 |
| Peak memory | 197708 kb |
| Host | smart-897f7077-145f-4a13-a8bb-1b890368916f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842593848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra ndom_long_reg_writes_reg_reads.1842593848 |
| Directory | /workspace/10.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/10.gpio_smoke.507695738 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 50479365 ps |
| CPU time | 0.83 seconds |
| Started | Jul 18 05:41:12 PM PDT 24 |
| Finished | Jul 18 05:41:21 PM PDT 24 |
| Peak memory | 195388 kb |
| Host | smart-ea85a00f-cca9-4917-8c35-fc1ebc21df1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507695738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.507695738 |
| Directory | /workspace/10.gpio_smoke/latest |
| Test location | /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2842721386 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 171186982 ps |
| CPU time | 1.28 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:18 PM PDT 24 |
| Peak memory | 196076 kb |
| Host | smart-a0b64659-18a1-4e85-8c19-ffd6b4530def |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842721386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2842721386 |
| Directory | /workspace/10.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/10.gpio_stress_all.2805275529 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 30888298247 ps |
| CPU time | 152.4 seconds |
| Started | Jul 18 05:41:13 PM PDT 24 |
| Finished | Jul 18 05:43:53 PM PDT 24 |
| Peak memory | 198256 kb |
| Host | smart-ab4c22ce-ca8a-4796-bbaf-75d63b0aeeae |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805275529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. gpio_stress_all.2805275529 |
| Directory | /workspace/10.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/11.gpio_alert_test.3350162099 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 16347030 ps |
| CPU time | 0.61 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:20 PM PDT 24 |
| Peak memory | 194372 kb |
| Host | smart-d1d23908-46e8-419f-87e6-c24807baa963 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350162099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3350162099 |
| Directory | /workspace/11.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2004021047 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 26279877 ps |
| CPU time | 0.76 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:11 PM PDT 24 |
| Peak memory | 195116 kb |
| Host | smart-02c989ae-641a-4f41-bdd2-e3968ba11c9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2004021047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2004021047 |
| Directory | /workspace/11.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/11.gpio_filter_stress.3443212319 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 783120279 ps |
| CPU time | 22.08 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:39 PM PDT 24 |
| Peak memory | 197096 kb |
| Host | smart-0721bfc7-b590-4741-a543-8d2c58e205d3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443212319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre ss.3443212319 |
| Directory | /workspace/11.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/11.gpio_full_random.3504798321 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 39912820 ps |
| CPU time | 0.74 seconds |
| Started | Jul 18 05:41:12 PM PDT 24 |
| Finished | Jul 18 05:41:20 PM PDT 24 |
| Peak memory | 195996 kb |
| Host | smart-6e68ac5c-8014-490a-b05e-139958bc0ad3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504798321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3504798321 |
| Directory | /workspace/11.gpio_full_random/latest |
| Test location | /workspace/coverage/default/11.gpio_intr_rand_pgm.2748157308 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 261796136 ps |
| CPU time | 0.81 seconds |
| Started | Jul 18 05:41:12 PM PDT 24 |
| Finished | Jul 18 05:41:21 PM PDT 24 |
| Peak memory | 196452 kb |
| Host | smart-b594d1ac-cf14-4828-8e9f-ae4392b64518 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748157308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2748157308 |
| Directory | /workspace/11.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.4074046105 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 428156440 ps |
| CPU time | 2.35 seconds |
| Started | Jul 18 05:41:14 PM PDT 24 |
| Finished | Jul 18 05:41:24 PM PDT 24 |
| Peak memory | 198244 kb |
| Host | smart-583521ab-5087-4be7-818f-6b17df93d2ab |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074046105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.gpio_intr_with_filter_rand_intr_event.4074046105 |
| Directory | /workspace/11.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/11.gpio_rand_intr_trigger.1882435025 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 38215384 ps |
| CPU time | 1.06 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:18 PM PDT 24 |
| Peak memory | 195840 kb |
| Host | smart-e25f5c72-fdc3-4e52-8949-9fa8a86cceaf |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882435025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger .1882435025 |
| Directory | /workspace/11.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/11.gpio_random_dout_din.1283701530 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1304069335 ps |
| CPU time | 1.24 seconds |
| Started | Jul 18 05:41:06 PM PDT 24 |
| Finished | Jul 18 05:41:09 PM PDT 24 |
| Peak memory | 197220 kb |
| Host | smart-dacd1341-899c-42c6-a1be-3010803ffb11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283701530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1283701530 |
| Directory | /workspace/11.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3368603552 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 83648069 ps |
| CPU time | 0.73 seconds |
| Started | Jul 18 05:41:15 PM PDT 24 |
| Finished | Jul 18 05:41:24 PM PDT 24 |
| Peak memory | 195580 kb |
| Host | smart-8da63e09-dc7a-4030-bb4d-c8f7aef81809 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368603552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu p_pulldown.3368603552 |
| Directory | /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.742951052 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1348529608 ps |
| CPU time | 5.52 seconds |
| Started | Jul 18 05:41:13 PM PDT 24 |
| Finished | Jul 18 05:41:26 PM PDT 24 |
| Peak memory | 198164 kb |
| Host | smart-d5c3fdb8-cafc-4c46-af68-b6d1db25bb5f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742951052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran dom_long_reg_writes_reg_reads.742951052 |
| Directory | /workspace/11.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/11.gpio_smoke.1718266122 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 75838520 ps |
| CPU time | 1.02 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:19 PM PDT 24 |
| Peak memory | 196732 kb |
| Host | smart-d6ac393b-73d7-41e3-93a3-fa949d8655fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1718266122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1718266122 |
| Directory | /workspace/11.gpio_smoke/latest |
| Test location | /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3166807804 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 46505532 ps |
| CPU time | 0.99 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:20 PM PDT 24 |
| Peak memory | 196560 kb |
| Host | smart-0c8680ac-25b4-4bef-a299-b888b0fb7396 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166807804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3166807804 |
| Directory | /workspace/11.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/11.gpio_stress_all.225205930 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8811299775 ps |
| CPU time | 90.64 seconds |
| Started | Jul 18 05:41:15 PM PDT 24 |
| Finished | Jul 18 05:42:55 PM PDT 24 |
| Peak memory | 198324 kb |
| Host | smart-954a8f4e-b3f8-4fef-bd69-0b23d8d632bf |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225205930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g pio_stress_all.225205930 |
| Directory | /workspace/11.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.57067470 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 27109301 ps |
| CPU time | 0.78 seconds |
| Started | Jul 18 05:41:15 PM PDT 24 |
| Finished | Jul 18 05:41:25 PM PDT 24 |
| Peak memory | 195588 kb |
| Host | smart-741703c4-9e4d-4e34-af04-b2fc15e9b2f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=57067470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.57067470 |
| Directory | /workspace/12.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/12.gpio_filter_stress.938073380 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 1389867787 ps |
| CPU time | 5.11 seconds |
| Started | Jul 18 05:41:15 PM PDT 24 |
| Finished | Jul 18 05:41:29 PM PDT 24 |
| Peak memory | 195680 kb |
| Host | smart-a9b0910a-6d51-48a5-ad28-cd26307a7d4a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938073380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres s.938073380 |
| Directory | /workspace/12.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/12.gpio_full_random.1609287409 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 290955744 ps |
| CPU time | 0.97 seconds |
| Started | Jul 18 05:41:14 PM PDT 24 |
| Finished | Jul 18 05:41:24 PM PDT 24 |
| Peak memory | 196916 kb |
| Host | smart-bd418bcc-3d7d-4c11-b5e9-889706a1c818 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609287409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1609287409 |
| Directory | /workspace/12.gpio_full_random/latest |
| Test location | /workspace/coverage/default/12.gpio_intr_rand_pgm.2145834242 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 53056202 ps |
| CPU time | 0.88 seconds |
| Started | Jul 18 05:41:14 PM PDT 24 |
| Finished | Jul 18 05:41:23 PM PDT 24 |
| Peak memory | 197700 kb |
| Host | smart-515c5d4b-3de1-44ec-bfb9-3c41d44d310b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145834242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2145834242 |
| Directory | /workspace/12.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.428398099 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 435617251 ps |
| CPU time | 3.29 seconds |
| Started | Jul 18 05:41:14 PM PDT 24 |
| Finished | Jul 18 05:41:26 PM PDT 24 |
| Peak memory | 198316 kb |
| Host | smart-5eb44f0f-40ba-4622-9855-dc85dee043e6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428398099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 12.gpio_intr_with_filter_rand_intr_event.428398099 |
| Directory | /workspace/12.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/12.gpio_rand_intr_trigger.1922658131 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 122905253 ps |
| CPU time | 1.09 seconds |
| Started | Jul 18 05:41:18 PM PDT 24 |
| Finished | Jul 18 05:41:27 PM PDT 24 |
| Peak memory | 196620 kb |
| Host | smart-00b59cba-4782-4ee5-84e7-4ecf7145c3af |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922658131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger .1922658131 |
| Directory | /workspace/12.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/12.gpio_random_dout_din.2815354499 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 22370609 ps |
| CPU time | 0.93 seconds |
| Started | Jul 18 05:41:12 PM PDT 24 |
| Finished | Jul 18 05:41:21 PM PDT 24 |
| Peak memory | 196216 kb |
| Host | smart-c9754259-6309-43b9-a0c6-fb92643e9be6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815354499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2815354499 |
| Directory | /workspace/12.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.4048111023 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 513500600 ps |
| CPU time | 1.36 seconds |
| Started | Jul 18 05:41:16 PM PDT 24 |
| Finished | Jul 18 05:41:26 PM PDT 24 |
| Peak memory | 198284 kb |
| Host | smart-8819fb51-3a60-4b99-ba97-5cd1d21adf1c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048111023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu p_pulldown.4048111023 |
| Directory | /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2993772875 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 138611565 ps |
| CPU time | 2.66 seconds |
| Started | Jul 18 05:41:13 PM PDT 24 |
| Finished | Jul 18 05:41:24 PM PDT 24 |
| Peak memory | 198136 kb |
| Host | smart-918c488f-9abd-4ee6-a57e-4bace1e6660d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993772875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra ndom_long_reg_writes_reg_reads.2993772875 |
| Directory | /workspace/12.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/12.gpio_smoke.3173262201 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 175520153 ps |
| CPU time | 1.01 seconds |
| Started | Jul 18 05:41:12 PM PDT 24 |
| Finished | Jul 18 05:41:21 PM PDT 24 |
| Peak memory | 196504 kb |
| Host | smart-cb36c5e0-6cfa-4eb4-8cef-4f6c417d4545 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173262201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3173262201 |
| Directory | /workspace/12.gpio_smoke/latest |
| Test location | /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1107438469 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 29242143 ps |
| CPU time | 0.9 seconds |
| Started | Jul 18 05:41:13 PM PDT 24 |
| Finished | Jul 18 05:41:22 PM PDT 24 |
| Peak memory | 195464 kb |
| Host | smart-0a8ad7e1-4cec-4c78-8538-a14723fd3dad |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107438469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1107438469 |
| Directory | /workspace/12.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/12.gpio_stress_all.2566775822 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 49455043881 ps |
| CPU time | 181.06 seconds |
| Started | Jul 18 05:41:16 PM PDT 24 |
| Finished | Jul 18 05:44:26 PM PDT 24 |
| Peak memory | 198240 kb |
| Host | smart-11e32bc2-a066-4265-95d8-3cf19393b5e6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566775822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. gpio_stress_all.2566775822 |
| Directory | /workspace/12.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.2511064274 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 414427186437 ps |
| CPU time | 2297.49 seconds |
| Started | Jul 18 05:41:14 PM PDT 24 |
| Finished | Jul 18 06:19:41 PM PDT 24 |
| Peak memory | 206684 kb |
| Host | smart-670b2b39-ced6-45c2-96bc-b9e0b301fef2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2511064274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.2511064274 |
| Directory | /workspace/12.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.gpio_alert_test.772946245 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 13398698 ps |
| CPU time | 0.61 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:12 PM PDT 24 |
| Peak memory | 194912 kb |
| Host | smart-1bdc7968-4b70-44a7-9bd6-a6be25ef440a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772946245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.772946245 |
| Directory | /workspace/13.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2099292221 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 124072337 ps |
| CPU time | 0.82 seconds |
| Started | Jul 18 05:41:14 PM PDT 24 |
| Finished | Jul 18 05:41:23 PM PDT 24 |
| Peak memory | 195688 kb |
| Host | smart-61bb52f2-7c57-4b1b-9230-b63e763f6a80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099292221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2099292221 |
| Directory | /workspace/13.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/13.gpio_filter_stress.2399723425 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1922511789 ps |
| CPU time | 14.11 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:33 PM PDT 24 |
| Peak memory | 195772 kb |
| Host | smart-6c927e34-6612-4efd-84d1-db9760be9ea8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399723425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre ss.2399723425 |
| Directory | /workspace/13.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/13.gpio_full_random.353565259 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 115463830 ps |
| CPU time | 0.81 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:13 PM PDT 24 |
| Peak memory | 196072 kb |
| Host | smart-5b2f11e0-c9f7-40ee-9ca2-dada90ee0ed4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353565259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.353565259 |
| Directory | /workspace/13.gpio_full_random/latest |
| Test location | /workspace/coverage/default/13.gpio_intr_rand_pgm.2364792026 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 28865070 ps |
| CPU time | 0.95 seconds |
| Started | Jul 18 05:41:15 PM PDT 24 |
| Finished | Jul 18 05:41:24 PM PDT 24 |
| Peak memory | 197048 kb |
| Host | smart-5052854b-e390-42a4-8303-b9040c1c3cf8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364792026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2364792026 |
| Directory | /workspace/13.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1830229518 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 239179995 ps |
| CPU time | 2.47 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:19 PM PDT 24 |
| Peak memory | 198168 kb |
| Host | smart-8dce4240-c941-469d-9e74-92f506dfa7ef |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830229518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1830229518 |
| Directory | /workspace/13.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/13.gpio_rand_intr_trigger.4020748137 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 279298831 ps |
| CPU time | 2.97 seconds |
| Started | Jul 18 05:41:14 PM PDT 24 |
| Finished | Jul 18 05:41:26 PM PDT 24 |
| Peak memory | 197188 kb |
| Host | smart-31533e88-d683-43c1-b841-ede6ba0fedf7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020748137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger .4020748137 |
| Directory | /workspace/13.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/13.gpio_random_dout_din.3303815634 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 21838132 ps |
| CPU time | 0.71 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:14 PM PDT 24 |
| Peak memory | 194536 kb |
| Host | smart-c73e1cdf-99cb-4d7a-b6b0-88ed1d07b3ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3303815634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3303815634 |
| Directory | /workspace/13.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.4165766647 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 53073051 ps |
| CPU time | 0.67 seconds |
| Started | Jul 18 05:41:15 PM PDT 24 |
| Finished | Jul 18 05:41:24 PM PDT 24 |
| Peak memory | 195360 kb |
| Host | smart-2c3d89df-e358-419b-a7e9-711960f84663 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165766647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu p_pulldown.4165766647 |
| Directory | /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2839235798 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1349480045 ps |
| CPU time | 4.46 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:17 PM PDT 24 |
| Peak memory | 198228 kb |
| Host | smart-a9c9409e-22cd-464a-9c9e-fd7d1f304a18 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839235798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra ndom_long_reg_writes_reg_reads.2839235798 |
| Directory | /workspace/13.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/13.gpio_smoke.1966980672 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 220848335 ps |
| CPU time | 1.16 seconds |
| Started | Jul 18 05:41:16 PM PDT 24 |
| Finished | Jul 18 05:41:25 PM PDT 24 |
| Peak memory | 195976 kb |
| Host | smart-52501255-4140-46a8-8387-4ca5ef0f8fca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1966980672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1966980672 |
| Directory | /workspace/13.gpio_smoke/latest |
| Test location | /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3846816015 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 27364071 ps |
| CPU time | 0.88 seconds |
| Started | Jul 18 05:41:14 PM PDT 24 |
| Finished | Jul 18 05:41:23 PM PDT 24 |
| Peak memory | 195580 kb |
| Host | smart-2bd803c2-25c7-4f67-b968-5eef63b9ea72 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846816015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3846816015 |
| Directory | /workspace/13.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/13.gpio_stress_all.1743958580 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 34660742886 ps |
| CPU time | 221.53 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:44:53 PM PDT 24 |
| Peak memory | 198332 kb |
| Host | smart-44ad00d9-9c5e-4e92-94e4-fbd86750fd93 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743958580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. gpio_stress_all.1743958580 |
| Directory | /workspace/13.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1033172587 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 205638637785 ps |
| CPU time | 2152.06 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 06:17:09 PM PDT 24 |
| Peak memory | 198336 kb |
| Host | smart-8c970846-e22b-47fb-8442-eff654a4a3f5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1033172587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1033172587 |
| Directory | /workspace/13.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.gpio_alert_test.3439903258 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 126914080 ps |
| CPU time | 0.54 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:41:44 PM PDT 24 |
| Peak memory | 193680 kb |
| Host | smart-713e254a-b856-405c-acdf-f2b03d076558 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439903258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3439903258 |
| Directory | /workspace/14.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.4287481969 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 27670311 ps |
| CPU time | 0.76 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:17 PM PDT 24 |
| Peak memory | 195352 kb |
| Host | smart-e08655b3-a81b-4af4-8acd-444414c5f8bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4287481969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.4287481969 |
| Directory | /workspace/14.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/14.gpio_filter_stress.1173165492 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 269840722 ps |
| CPU time | 14.67 seconds |
| Started | Jul 18 05:41:22 PM PDT 24 |
| Finished | Jul 18 05:41:45 PM PDT 24 |
| Peak memory | 198256 kb |
| Host | smart-99097118-6fac-4469-8ef9-b56de7fccfa6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173165492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre ss.1173165492 |
| Directory | /workspace/14.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/14.gpio_full_random.2244453239 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 75743020 ps |
| CPU time | 0.76 seconds |
| Started | Jul 18 05:41:24 PM PDT 24 |
| Finished | Jul 18 05:41:34 PM PDT 24 |
| Peak memory | 196036 kb |
| Host | smart-6ce579f8-3598-46cf-9e40-bcd474bc4a12 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244453239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2244453239 |
| Directory | /workspace/14.gpio_full_random/latest |
| Test location | /workspace/coverage/default/14.gpio_intr_rand_pgm.899691242 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 113325776 ps |
| CPU time | 0.99 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:17 PM PDT 24 |
| Peak memory | 196252 kb |
| Host | smart-16d831c9-755f-4eb6-a160-4d49659cb426 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899691242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.899691242 |
| Directory | /workspace/14.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1403513788 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 36015695 ps |
| CPU time | 1.53 seconds |
| Started | Jul 18 05:41:20 PM PDT 24 |
| Finished | Jul 18 05:41:30 PM PDT 24 |
| Peak memory | 196980 kb |
| Host | smart-d59f6e1d-7f29-42ee-becf-2ba316b592a0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403513788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1403513788 |
| Directory | /workspace/14.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/14.gpio_rand_intr_trigger.2265083781 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 67742209 ps |
| CPU time | 1.57 seconds |
| Started | Jul 18 05:41:13 PM PDT 24 |
| Finished | Jul 18 05:41:23 PM PDT 24 |
| Peak memory | 196184 kb |
| Host | smart-7a0f9300-08dc-4faa-8601-f9a947d47b0b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265083781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger .2265083781 |
| Directory | /workspace/14.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/14.gpio_random_dout_din.2773440318 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 153918143 ps |
| CPU time | 0.99 seconds |
| Started | Jul 18 05:41:09 PM PDT 24 |
| Finished | Jul 18 05:41:15 PM PDT 24 |
| Peak memory | 196920 kb |
| Host | smart-e43cf7ec-bcfb-4907-91fc-4da28ad5f0fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2773440318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2773440318 |
| Directory | /workspace/14.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1454924552 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 41792250 ps |
| CPU time | 1.19 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:15 PM PDT 24 |
| Peak memory | 196944 kb |
| Host | smart-1a2bef53-5a7c-4f43-ab49-745923b62829 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454924552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu p_pulldown.1454924552 |
| Directory | /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2302169469 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 291156065 ps |
| CPU time | 4.88 seconds |
| Started | Jul 18 05:41:31 PM PDT 24 |
| Finished | Jul 18 05:41:52 PM PDT 24 |
| Peak memory | 198136 kb |
| Host | smart-c1420d51-d32c-43e6-9d17-9076b57018d0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302169469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra ndom_long_reg_writes_reg_reads.2302169469 |
| Directory | /workspace/14.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/14.gpio_smoke.4018881095 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 184398160 ps |
| CPU time | 1.32 seconds |
| Started | Jul 18 05:41:09 PM PDT 24 |
| Finished | Jul 18 05:41:16 PM PDT 24 |
| Peak memory | 196896 kb |
| Host | smart-08aeb007-26bd-4a3e-8045-43ab1f2d23e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4018881095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.4018881095 |
| Directory | /workspace/14.gpio_smoke/latest |
| Test location | /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3838352725 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 36446184 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:19 PM PDT 24 |
| Peak memory | 196440 kb |
| Host | smart-4f24aaee-c2cd-464d-8bfe-22aacad50272 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838352725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3838352725 |
| Directory | /workspace/14.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/14.gpio_stress_all.1117382702 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 20905740479 ps |
| CPU time | 145.62 seconds |
| Started | Jul 18 05:41:30 PM PDT 24 |
| Finished | Jul 18 05:44:11 PM PDT 24 |
| Peak memory | 198276 kb |
| Host | smart-3988eaba-d09b-4265-93fb-8546538f235a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117382702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. gpio_stress_all.1117382702 |
| Directory | /workspace/14.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.700745681 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 65904266212 ps |
| CPU time | 1167.84 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 06:01:12 PM PDT 24 |
| Peak memory | 198428 kb |
| Host | smart-df96af72-ba5b-43bc-99dd-b54ed78fdc96 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =700745681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.700745681 |
| Directory | /workspace/14.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/15.gpio_alert_test.1977562235 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 17380160 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:41:21 PM PDT 24 |
| Finished | Jul 18 05:41:29 PM PDT 24 |
| Peak memory | 195060 kb |
| Host | smart-85022aea-4129-4189-933d-2773334c1b50 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977562235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1977562235 |
| Directory | /workspace/15.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1896361606 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 103834127 ps |
| CPU time | 0.79 seconds |
| Started | Jul 18 05:41:23 PM PDT 24 |
| Finished | Jul 18 05:41:34 PM PDT 24 |
| Peak memory | 195776 kb |
| Host | smart-1aaa7c3c-cbe5-46e7-86ef-2eb7a4851085 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1896361606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1896361606 |
| Directory | /workspace/15.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/15.gpio_filter_stress.3186208503 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 314069686 ps |
| CPU time | 16.48 seconds |
| Started | Jul 18 05:41:21 PM PDT 24 |
| Finished | Jul 18 05:41:46 PM PDT 24 |
| Peak memory | 197028 kb |
| Host | smart-32d4c619-ed30-42a0-8ab7-b2615b8ce917 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186208503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre ss.3186208503 |
| Directory | /workspace/15.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/15.gpio_full_random.1686471406 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 57208796 ps |
| CPU time | 0.95 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:41:44 PM PDT 24 |
| Peak memory | 196900 kb |
| Host | smart-3dff3d7a-b97f-44b0-97b3-c207d665b18b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686471406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1686471406 |
| Directory | /workspace/15.gpio_full_random/latest |
| Test location | /workspace/coverage/default/15.gpio_intr_rand_pgm.3385824248 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 173246094 ps |
| CPU time | 1.2 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:41:45 PM PDT 24 |
| Peak memory | 197420 kb |
| Host | smart-89740c66-045e-4a2c-9c78-75f7195cfcf6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385824248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3385824248 |
| Directory | /workspace/15.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3463095109 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 28919503 ps |
| CPU time | 1.33 seconds |
| Started | Jul 18 05:41:22 PM PDT 24 |
| Finished | Jul 18 05:41:33 PM PDT 24 |
| Peak memory | 198284 kb |
| Host | smart-bf5032ff-744a-4a2c-b35f-4922c6c05369 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463095109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3463095109 |
| Directory | /workspace/15.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/15.gpio_rand_intr_trigger.1420026543 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 131254188 ps |
| CPU time | 1.07 seconds |
| Started | Jul 18 05:41:22 PM PDT 24 |
| Finished | Jul 18 05:41:32 PM PDT 24 |
| Peak memory | 195788 kb |
| Host | smart-a1b10ef1-a566-4be8-a7d6-974153de8714 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420026543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger .1420026543 |
| Directory | /workspace/15.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/15.gpio_random_dout_din.2789889554 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 116843843 ps |
| CPU time | 0.82 seconds |
| Started | Jul 18 05:41:18 PM PDT 24 |
| Finished | Jul 18 05:41:27 PM PDT 24 |
| Peak memory | 196588 kb |
| Host | smart-67f8cfbd-0901-4238-986c-efb23f314c65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789889554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2789889554 |
| Directory | /workspace/15.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1620844939 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 91610931 ps |
| CPU time | 0.77 seconds |
| Started | Jul 18 05:41:18 PM PDT 24 |
| Finished | Jul 18 05:41:27 PM PDT 24 |
| Peak memory | 195476 kb |
| Host | smart-c4d517e1-16ac-4205-a441-2ee26f5b9e24 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620844939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu p_pulldown.1620844939 |
| Directory | /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2892403923 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 156379112 ps |
| CPU time | 2.76 seconds |
| Started | Jul 18 05:41:21 PM PDT 24 |
| Finished | Jul 18 05:41:32 PM PDT 24 |
| Peak memory | 198160 kb |
| Host | smart-9dd1db40-8325-4d7f-8de8-590591731e76 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892403923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra ndom_long_reg_writes_reg_reads.2892403923 |
| Directory | /workspace/15.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/15.gpio_smoke.2388208786 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 24896704 ps |
| CPU time | 0.72 seconds |
| Started | Jul 18 05:41:18 PM PDT 24 |
| Finished | Jul 18 05:41:27 PM PDT 24 |
| Peak memory | 194356 kb |
| Host | smart-7cfe58ed-c244-4b14-b8ca-1dd445fa7599 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388208786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2388208786 |
| Directory | /workspace/15.gpio_smoke/latest |
| Test location | /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1431036560 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 77814179 ps |
| CPU time | 1.16 seconds |
| Started | Jul 18 05:41:21 PM PDT 24 |
| Finished | Jul 18 05:41:30 PM PDT 24 |
| Peak memory | 196032 kb |
| Host | smart-22af21dd-e0ae-4c28-8f2e-e13d48a38eeb |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431036560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1431036560 |
| Directory | /workspace/15.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/15.gpio_stress_all.4058851125 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 81396286953 ps |
| CPU time | 59.68 seconds |
| Started | Jul 18 05:41:21 PM PDT 24 |
| Finished | Jul 18 05:42:29 PM PDT 24 |
| Peak memory | 198236 kb |
| Host | smart-1aee9c83-d7e4-44db-818f-26de0c1edbc9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058851125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. gpio_stress_all.4058851125 |
| Directory | /workspace/15.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.3501989874 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 181598458324 ps |
| CPU time | 389.9 seconds |
| Started | Jul 18 05:41:19 PM PDT 24 |
| Finished | Jul 18 05:47:56 PM PDT 24 |
| Peak memory | 198508 kb |
| Host | smart-64e5f5c2-197b-4039-80c8-c277c0076ae1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3501989874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.3501989874 |
| Directory | /workspace/15.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.gpio_alert_test.3580892095 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 37211986 ps |
| CPU time | 0.57 seconds |
| Started | Jul 18 05:41:23 PM PDT 24 |
| Finished | Jul 18 05:41:34 PM PDT 24 |
| Peak memory | 194060 kb |
| Host | smart-8289fe57-3841-46f2-bba4-5e933941616a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580892095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3580892095 |
| Directory | /workspace/16.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1547261340 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 83313021 ps |
| CPU time | 0.75 seconds |
| Started | Jul 18 05:41:21 PM PDT 24 |
| Finished | Jul 18 05:41:30 PM PDT 24 |
| Peak memory | 195604 kb |
| Host | smart-c046c182-e2b4-4040-8188-3bd197600311 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1547261340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1547261340 |
| Directory | /workspace/16.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/16.gpio_filter_stress.3704098457 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2026528568 ps |
| CPU time | 21.03 seconds |
| Started | Jul 18 05:41:28 PM PDT 24 |
| Finished | Jul 18 05:42:03 PM PDT 24 |
| Peak memory | 196492 kb |
| Host | smart-8d69d232-45d1-48b7-af2b-d7d4367d5f0f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704098457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre ss.3704098457 |
| Directory | /workspace/16.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/16.gpio_full_random.757008861 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 221540668 ps |
| CPU time | 1.04 seconds |
| Started | Jul 18 05:41:24 PM PDT 24 |
| Finished | Jul 18 05:41:36 PM PDT 24 |
| Peak memory | 196860 kb |
| Host | smart-3ea6f934-bfe5-41c4-a144-0c93166cb540 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757008861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.757008861 |
| Directory | /workspace/16.gpio_full_random/latest |
| Test location | /workspace/coverage/default/16.gpio_intr_rand_pgm.650082967 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 133453901 ps |
| CPU time | 1.24 seconds |
| Started | Jul 18 05:41:21 PM PDT 24 |
| Finished | Jul 18 05:41:30 PM PDT 24 |
| Peak memory | 196928 kb |
| Host | smart-7c3003bb-1fb2-47f7-97da-2325b0826279 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650082967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.650082967 |
| Directory | /workspace/16.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3508757850 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 61323440 ps |
| CPU time | 1.1 seconds |
| Started | Jul 18 05:41:26 PM PDT 24 |
| Finished | Jul 18 05:41:39 PM PDT 24 |
| Peak memory | 196160 kb |
| Host | smart-280a981b-e5cb-4185-838b-d98ffaf26169 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508757850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3508757850 |
| Directory | /workspace/16.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/16.gpio_rand_intr_trigger.610149901 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 319623253 ps |
| CPU time | 3.13 seconds |
| Started | Jul 18 05:41:20 PM PDT 24 |
| Finished | Jul 18 05:41:31 PM PDT 24 |
| Peak memory | 196020 kb |
| Host | smart-8ae52e65-381e-4726-81fc-d6c672476094 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610149901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger. 610149901 |
| Directory | /workspace/16.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/16.gpio_random_dout_din.2567074529 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 227315339 ps |
| CPU time | 0.86 seconds |
| Started | Jul 18 05:41:24 PM PDT 24 |
| Finished | Jul 18 05:41:35 PM PDT 24 |
| Peak memory | 196908 kb |
| Host | smart-7d70e073-6c0c-41e5-b65a-62cef31df401 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2567074529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2567074529 |
| Directory | /workspace/16.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1343107599 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 19542549 ps |
| CPU time | 0.67 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:37 PM PDT 24 |
| Peak memory | 194524 kb |
| Host | smart-51150f20-1832-430c-8573-75a5bbda5999 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343107599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu p_pulldown.1343107599 |
| Directory | /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2106280567 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 703477709 ps |
| CPU time | 5.7 seconds |
| Started | Jul 18 05:41:22 PM PDT 24 |
| Finished | Jul 18 05:41:38 PM PDT 24 |
| Peak memory | 198156 kb |
| Host | smart-902dd70a-552d-444a-b89b-134722fdb7a4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106280567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra ndom_long_reg_writes_reg_reads.2106280567 |
| Directory | /workspace/16.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/16.gpio_smoke.63030764 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 65114203 ps |
| CPU time | 1.11 seconds |
| Started | Jul 18 05:41:31 PM PDT 24 |
| Finished | Jul 18 05:41:48 PM PDT 24 |
| Peak memory | 195968 kb |
| Host | smart-7f951cea-70c1-4be2-93c8-3297e4e6040b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63030764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.63030764 |
| Directory | /workspace/16.gpio_smoke/latest |
| Test location | /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1072910381 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 130231545 ps |
| CPU time | 0.97 seconds |
| Started | Jul 18 05:41:18 PM PDT 24 |
| Finished | Jul 18 05:41:27 PM PDT 24 |
| Peak memory | 196620 kb |
| Host | smart-4bb2fdbd-78cc-49d7-b31a-4cd4a2691784 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072910381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1072910381 |
| Directory | /workspace/16.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/16.gpio_stress_all.3551278963 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 41500520511 ps |
| CPU time | 145.37 seconds |
| Started | Jul 18 05:41:21 PM PDT 24 |
| Finished | Jul 18 05:43:55 PM PDT 24 |
| Peak memory | 198352 kb |
| Host | smart-307339c5-4055-4f69-9dc6-8c0e4f836b5f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551278963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. gpio_stress_all.3551278963 |
| Directory | /workspace/16.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/17.gpio_alert_test.304302182 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 13417539 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:37 PM PDT 24 |
| Peak memory | 195088 kb |
| Host | smart-6af26787-026e-4560-8740-5f37c4e9cd41 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304302182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.304302182 |
| Directory | /workspace/17.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3027175182 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 57797696 ps |
| CPU time | 0.65 seconds |
| Started | Jul 18 05:41:20 PM PDT 24 |
| Finished | Jul 18 05:41:29 PM PDT 24 |
| Peak memory | 194208 kb |
| Host | smart-992eeaf0-66c6-4dc6-b9e6-1dec5b25b22f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3027175182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3027175182 |
| Directory | /workspace/17.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/17.gpio_filter_stress.1474994546 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 677929685 ps |
| CPU time | 17.73 seconds |
| Started | Jul 18 05:41:23 PM PDT 24 |
| Finished | Jul 18 05:41:50 PM PDT 24 |
| Peak memory | 197208 kb |
| Host | smart-ef853d0b-4b07-4106-92e2-401cf08e8ad9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474994546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre ss.1474994546 |
| Directory | /workspace/17.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/17.gpio_full_random.1053955627 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 31883939 ps |
| CPU time | 0.73 seconds |
| Started | Jul 18 05:41:23 PM PDT 24 |
| Finished | Jul 18 05:41:33 PM PDT 24 |
| Peak memory | 196080 kb |
| Host | smart-083f7800-213d-421b-bed5-13c49d8d4b6b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053955627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1053955627 |
| Directory | /workspace/17.gpio_full_random/latest |
| Test location | /workspace/coverage/default/17.gpio_intr_rand_pgm.407739807 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 668265887 ps |
| CPU time | 1.15 seconds |
| Started | Jul 18 05:41:26 PM PDT 24 |
| Finished | Jul 18 05:41:39 PM PDT 24 |
| Peak memory | 196292 kb |
| Host | smart-4a27bcc9-2cee-405e-9772-b5a2171afa14 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407739807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.407739807 |
| Directory | /workspace/17.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2920783062 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 205050625 ps |
| CPU time | 2.67 seconds |
| Started | Jul 18 05:41:31 PM PDT 24 |
| Finished | Jul 18 05:41:50 PM PDT 24 |
| Peak memory | 198264 kb |
| Host | smart-9e884b26-f1bd-4e99-bfa6-e6d349ff8554 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920783062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2920783062 |
| Directory | /workspace/17.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/17.gpio_rand_intr_trigger.3026207356 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 410155848 ps |
| CPU time | 2.44 seconds |
| Started | Jul 18 05:41:30 PM PDT 24 |
| Finished | Jul 18 05:41:49 PM PDT 24 |
| Peak memory | 196068 kb |
| Host | smart-11a2955b-dfd9-47eb-99cf-c561cc701291 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026207356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger .3026207356 |
| Directory | /workspace/17.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/17.gpio_random_dout_din.229144814 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 216121785 ps |
| CPU time | 1.28 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:41:45 PM PDT 24 |
| Peak memory | 197264 kb |
| Host | smart-aed65a9f-2e1a-4aff-852b-0053e1925b75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=229144814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.229144814 |
| Directory | /workspace/17.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.250174920 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 26760487 ps |
| CPU time | 0.8 seconds |
| Started | Jul 18 05:41:31 PM PDT 24 |
| Finished | Jul 18 05:41:48 PM PDT 24 |
| Peak memory | 196400 kb |
| Host | smart-11edaee5-2cc8-46ee-9df1-632418cfabaf |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250174920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup _pulldown.250174920 |
| Directory | /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1313852076 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 188231100 ps |
| CPU time | 4.42 seconds |
| Started | Jul 18 05:56:41 PM PDT 24 |
| Finished | Jul 18 05:56:53 PM PDT 24 |
| Peak memory | 198156 kb |
| Host | smart-d4beda0b-2a13-4c30-b249-f2d9433ddb71 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313852076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra ndom_long_reg_writes_reg_reads.1313852076 |
| Directory | /workspace/17.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/17.gpio_smoke.4273355549 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 72555515 ps |
| CPU time | 1.26 seconds |
| Started | Jul 18 05:41:32 PM PDT 24 |
| Finished | Jul 18 05:41:49 PM PDT 24 |
| Peak memory | 196820 kb |
| Host | smart-997b3fb5-da00-45da-9b7f-bdbf3a8ef92f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4273355549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.4273355549 |
| Directory | /workspace/17.gpio_smoke/latest |
| Test location | /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3447947465 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 136540225 ps |
| CPU time | 0.82 seconds |
| Started | Jul 18 05:41:23 PM PDT 24 |
| Finished | Jul 18 05:41:34 PM PDT 24 |
| Peak memory | 195512 kb |
| Host | smart-13ff0c16-baa2-41cf-93d7-a36333422056 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447947465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3447947465 |
| Directory | /workspace/17.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/17.gpio_stress_all.1190304510 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 17504217085 ps |
| CPU time | 135.95 seconds |
| Started | Jul 18 05:41:22 PM PDT 24 |
| Finished | Jul 18 05:43:48 PM PDT 24 |
| Peak memory | 198396 kb |
| Host | smart-249fda2f-2843-417e-b9cd-b7e2019ffc38 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190304510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. gpio_stress_all.1190304510 |
| Directory | /workspace/17.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/18.gpio_alert_test.1861000443 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 13541055 ps |
| CPU time | 0.66 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:37 PM PDT 24 |
| Peak memory | 195104 kb |
| Host | smart-5e673abb-0d31-4631-bc7a-f6a50223bd05 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861000443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1861000443 |
| Directory | /workspace/18.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3178177480 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 48203958 ps |
| CPU time | 1.02 seconds |
| Started | Jul 18 05:41:31 PM PDT 24 |
| Finished | Jul 18 05:41:48 PM PDT 24 |
| Peak memory | 196684 kb |
| Host | smart-a6f8b27b-74b0-4b78-9aac-23e3c378eb65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3178177480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3178177480 |
| Directory | /workspace/18.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/18.gpio_filter_stress.2984142324 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 212313135 ps |
| CPU time | 6.89 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:41:51 PM PDT 24 |
| Peak memory | 195716 kb |
| Host | smart-15916c8a-cffd-4559-93a9-91b02b614146 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984142324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre ss.2984142324 |
| Directory | /workspace/18.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/18.gpio_full_random.642911402 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 52114020 ps |
| CPU time | 0.76 seconds |
| Started | Jul 18 05:41:28 PM PDT 24 |
| Finished | Jul 18 05:41:42 PM PDT 24 |
| Peak memory | 194640 kb |
| Host | smart-707fa188-b483-42fd-9f02-6cd9433010db |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642911402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.642911402 |
| Directory | /workspace/18.gpio_full_random/latest |
| Test location | /workspace/coverage/default/18.gpio_intr_rand_pgm.1606824916 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 97333067 ps |
| CPU time | 0.88 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:41:44 PM PDT 24 |
| Peak memory | 196896 kb |
| Host | smart-68cafda4-f4d5-4bd7-ba41-279e2eeb281c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606824916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1606824916 |
| Directory | /workspace/18.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.59954569 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 44399979 ps |
| CPU time | 1.83 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:41:45 PM PDT 24 |
| Peak memory | 198380 kb |
| Host | smart-1d379dad-e9ae-44cb-9fe4-4979eb30ab05 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59954569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 18.gpio_intr_with_filter_rand_intr_event.59954569 |
| Directory | /workspace/18.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/18.gpio_rand_intr_trigger.2049859025 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 227543126 ps |
| CPU time | 2.53 seconds |
| Started | Jul 18 05:41:22 PM PDT 24 |
| Finished | Jul 18 05:41:34 PM PDT 24 |
| Peak memory | 196020 kb |
| Host | smart-bf498ecb-b5cb-4b1f-871b-4611b7cc9b13 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049859025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger .2049859025 |
| Directory | /workspace/18.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/18.gpio_random_dout_din.761944284 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 48028691 ps |
| CPU time | 0.67 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:41:45 PM PDT 24 |
| Peak memory | 194540 kb |
| Host | smart-3c5c40d5-7013-4ce2-b4ee-c99344df2472 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=761944284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.761944284 |
| Directory | /workspace/18.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.204705670 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 63384737 ps |
| CPU time | 0.81 seconds |
| Started | Jul 18 05:41:23 PM PDT 24 |
| Finished | Jul 18 05:41:34 PM PDT 24 |
| Peak memory | 195492 kb |
| Host | smart-63b19209-2b50-40ea-b976-3b2f263024cd |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204705670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup _pulldown.204705670 |
| Directory | /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.282617721 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 260414196 ps |
| CPU time | 3.18 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:39 PM PDT 24 |
| Peak memory | 198220 kb |
| Host | smart-74855407-e8db-4103-8212-71ba9b98fec1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282617721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran dom_long_reg_writes_reg_reads.282617721 |
| Directory | /workspace/18.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/18.gpio_smoke.2362286521 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 319877202 ps |
| CPU time | 1.38 seconds |
| Started | Jul 18 05:41:24 PM PDT 24 |
| Finished | Jul 18 05:41:36 PM PDT 24 |
| Peak memory | 197148 kb |
| Host | smart-cd40dac3-65b3-478c-8cf5-a4d43f4ac6c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362286521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2362286521 |
| Directory | /workspace/18.gpio_smoke/latest |
| Test location | /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3352113671 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 36809755 ps |
| CPU time | 0.85 seconds |
| Started | Jul 18 05:41:23 PM PDT 24 |
| Finished | Jul 18 05:41:35 PM PDT 24 |
| Peak memory | 196260 kb |
| Host | smart-cc9d08fd-80d8-475c-bc31-411efd71f9bd |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352113671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3352113671 |
| Directory | /workspace/18.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/18.gpio_stress_all.4023814133 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 35298384536 ps |
| CPU time | 129.32 seconds |
| Started | Jul 18 05:41:27 PM PDT 24 |
| Finished | Jul 18 05:43:50 PM PDT 24 |
| Peak memory | 198240 kb |
| Host | smart-e3f83840-d45c-4078-944f-52b9bdafd809 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023814133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. gpio_stress_all.4023814133 |
| Directory | /workspace/18.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/19.gpio_alert_test.3195641768 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 12232907 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:41:24 PM PDT 24 |
| Finished | Jul 18 05:41:36 PM PDT 24 |
| Peak memory | 194928 kb |
| Host | smart-fccededd-0ade-4008-8a66-393b46049b46 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195641768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3195641768 |
| Directory | /workspace/19.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.617993797 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 61294967 ps |
| CPU time | 0.71 seconds |
| Started | Jul 18 05:42:39 PM PDT 24 |
| Finished | Jul 18 05:42:55 PM PDT 24 |
| Peak memory | 194172 kb |
| Host | smart-6dc33eab-5e2a-4a13-99bd-823c49ef3437 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=617993797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.617993797 |
| Directory | /workspace/19.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/19.gpio_filter_stress.3387750232 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1005395505 ps |
| CPU time | 24.15 seconds |
| Started | Jul 18 05:41:24 PM PDT 24 |
| Finished | Jul 18 05:41:59 PM PDT 24 |
| Peak memory | 195716 kb |
| Host | smart-86c1dd32-ccfc-4fa8-96a0-81356e304235 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387750232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre ss.3387750232 |
| Directory | /workspace/19.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/19.gpio_full_random.2725394491 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 196887072 ps |
| CPU time | 0.96 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:39 PM PDT 24 |
| Peak memory | 196628 kb |
| Host | smart-53e207ed-c740-4112-ae58-2f039787bf07 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725394491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2725394491 |
| Directory | /workspace/19.gpio_full_random/latest |
| Test location | /workspace/coverage/default/19.gpio_intr_rand_pgm.2052673432 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 165204694 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:41:21 PM PDT 24 |
| Finished | Jul 18 05:41:31 PM PDT 24 |
| Peak memory | 195740 kb |
| Host | smart-b0879f25-3336-4665-b601-8e20e2defb9e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052673432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2052673432 |
| Directory | /workspace/19.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3782336242 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 71586937 ps |
| CPU time | 2.81 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:39 PM PDT 24 |
| Peak memory | 196552 kb |
| Host | smart-da951c2f-2a22-4f1a-82f7-5a0d4ae1ac73 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782336242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3782336242 |
| Directory | /workspace/19.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/19.gpio_rand_intr_trigger.496116873 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 240285756 ps |
| CPU time | 2.72 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:39 PM PDT 24 |
| Peak memory | 198268 kb |
| Host | smart-5380db7c-2c61-44ac-ab7a-436d31b47be7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496116873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger. 496116873 |
| Directory | /workspace/19.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/19.gpio_random_dout_din.2811665069 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 78350670 ps |
| CPU time | 0.97 seconds |
| Started | Jul 18 05:41:28 PM PDT 24 |
| Finished | Jul 18 05:41:43 PM PDT 24 |
| Peak memory | 195996 kb |
| Host | smart-4bfea808-d8f8-4174-86bb-d3d01477c6f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2811665069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2811665069 |
| Directory | /workspace/19.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3840114994 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 68795491 ps |
| CPU time | 0.88 seconds |
| Started | Jul 18 05:41:24 PM PDT 24 |
| Finished | Jul 18 05:41:35 PM PDT 24 |
| Peak memory | 196184 kb |
| Host | smart-fe86d07e-1db0-4a5d-a498-b3c904a40751 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840114994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu p_pulldown.3840114994 |
| Directory | /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2405712478 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 454076013 ps |
| CPU time | 1.87 seconds |
| Started | Jul 18 05:41:24 PM PDT 24 |
| Finished | Jul 18 05:41:37 PM PDT 24 |
| Peak memory | 198132 kb |
| Host | smart-0b5aadd0-9d50-4043-8721-d855b5a85fed |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405712478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra ndom_long_reg_writes_reg_reads.2405712478 |
| Directory | /workspace/19.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/19.gpio_smoke.1073045160 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 52470371 ps |
| CPU time | 1.03 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:37 PM PDT 24 |
| Peak memory | 196520 kb |
| Host | smart-08cc815e-48cd-4a0a-a44f-e1f1b5dab746 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1073045160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1073045160 |
| Directory | /workspace/19.gpio_smoke/latest |
| Test location | /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.580856419 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 39417345 ps |
| CPU time | 1.05 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:37 PM PDT 24 |
| Peak memory | 195776 kb |
| Host | smart-dea2a815-b6bb-44c2-8c18-913c8b57b927 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580856419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.580856419 |
| Directory | /workspace/19.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/19.gpio_stress_all.952262115 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 22088381767 ps |
| CPU time | 119.5 seconds |
| Started | Jul 18 05:41:23 PM PDT 24 |
| Finished | Jul 18 05:43:33 PM PDT 24 |
| Peak memory | 198272 kb |
| Host | smart-dcc5f421-e80c-464e-a2de-b5a47bcb49b8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952262115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g pio_stress_all.952262115 |
| Directory | /workspace/19.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/2.gpio_alert_test.4262972912 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 11501978 ps |
| CPU time | 0.55 seconds |
| Started | Jul 18 05:40:45 PM PDT 24 |
| Finished | Jul 18 05:40:48 PM PDT 24 |
| Peak memory | 194872 kb |
| Host | smart-1c8978c3-9530-4f98-bcb5-9b70b88b9d5b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262972912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.4262972912 |
| Directory | /workspace/2.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.490156643 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 98555754 ps |
| CPU time | 0.83 seconds |
| Started | Jul 18 05:40:47 PM PDT 24 |
| Finished | Jul 18 05:40:53 PM PDT 24 |
| Peak memory | 196272 kb |
| Host | smart-5177e904-dff3-4898-92be-443536743d94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490156643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.490156643 |
| Directory | /workspace/2.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/2.gpio_filter_stress.1976336691 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 230814049 ps |
| CPU time | 5.49 seconds |
| Started | Jul 18 05:40:44 PM PDT 24 |
| Finished | Jul 18 05:40:52 PM PDT 24 |
| Peak memory | 197204 kb |
| Host | smart-05824508-227c-4c3f-af68-7d3dcd939fc2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976336691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres s.1976336691 |
| Directory | /workspace/2.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/2.gpio_full_random.3307146030 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 45574609 ps |
| CPU time | 0.66 seconds |
| Started | Jul 18 05:40:51 PM PDT 24 |
| Finished | Jul 18 05:40:57 PM PDT 24 |
| Peak memory | 194252 kb |
| Host | smart-7dcae113-f866-4f69-a591-552ddf772e20 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307146030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3307146030 |
| Directory | /workspace/2.gpio_full_random/latest |
| Test location | /workspace/coverage/default/2.gpio_intr_rand_pgm.2496819171 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 58727204 ps |
| CPU time | 1.1 seconds |
| Started | Jul 18 05:40:46 PM PDT 24 |
| Finished | Jul 18 05:40:52 PM PDT 24 |
| Peak memory | 195968 kb |
| Host | smart-1d790c48-02eb-4d8a-b645-037a2214fc12 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496819171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2496819171 |
| Directory | /workspace/2.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3662909188 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 104108172 ps |
| CPU time | 2.08 seconds |
| Started | Jul 18 05:40:45 PM PDT 24 |
| Finished | Jul 18 05:40:50 PM PDT 24 |
| Peak memory | 198312 kb |
| Host | smart-7c81a6d7-0ad8-4d66-95ad-c1b7e5267180 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662909188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3662909188 |
| Directory | /workspace/2.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/2.gpio_rand_intr_trigger.3430021891 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 338422308 ps |
| CPU time | 3.3 seconds |
| Started | Jul 18 05:40:49 PM PDT 24 |
| Finished | Jul 18 05:40:57 PM PDT 24 |
| Peak memory | 195912 kb |
| Host | smart-c1662772-0775-4cc4-99d4-94142e28706e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430021891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger. 3430021891 |
| Directory | /workspace/2.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/2.gpio_random_dout_din.3240787969 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 113216147 ps |
| CPU time | 1.23 seconds |
| Started | Jul 18 05:40:44 PM PDT 24 |
| Finished | Jul 18 05:40:49 PM PDT 24 |
| Peak memory | 197232 kb |
| Host | smart-3b101129-662d-4c78-86f3-b9d0059537ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3240787969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3240787969 |
| Directory | /workspace/2.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3191011569 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 75277248 ps |
| CPU time | 1.36 seconds |
| Started | Jul 18 05:40:49 PM PDT 24 |
| Finished | Jul 18 05:40:56 PM PDT 24 |
| Peak memory | 197268 kb |
| Host | smart-231265fa-6b12-4dc6-b13b-1a020c8eb785 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191011569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup _pulldown.3191011569 |
| Directory | /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1272442967 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 95348946 ps |
| CPU time | 4.37 seconds |
| Started | Jul 18 05:40:45 PM PDT 24 |
| Finished | Jul 18 05:40:53 PM PDT 24 |
| Peak memory | 198188 kb |
| Host | smart-004faa88-daaf-4589-a9af-1fd29dd3c99d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272442967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran dom_long_reg_writes_reg_reads.1272442967 |
| Directory | /workspace/2.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/2.gpio_sec_cm.2258137472 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 173110962 ps |
| CPU time | 0.99 seconds |
| Started | Jul 18 05:40:49 PM PDT 24 |
| Finished | Jul 18 05:40:55 PM PDT 24 |
| Peak memory | 215420 kb |
| Host | smart-fbc47684-7369-4a1f-a722-0b5618617da5 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258137472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2258137472 |
| Directory | /workspace/2.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/2.gpio_smoke.4209003216 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 81345931 ps |
| CPU time | 1.47 seconds |
| Started | Jul 18 05:40:50 PM PDT 24 |
| Finished | Jul 18 05:40:57 PM PDT 24 |
| Peak memory | 197040 kb |
| Host | smart-64e4e26c-986b-48fe-9fed-8108eb8bc352 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209003216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.4209003216 |
| Directory | /workspace/2.gpio_smoke/latest |
| Test location | /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2806306802 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 338372291 ps |
| CPU time | 1.31 seconds |
| Started | Jul 18 05:40:47 PM PDT 24 |
| Finished | Jul 18 05:40:53 PM PDT 24 |
| Peak memory | 196732 kb |
| Host | smart-5732dd9b-c2eb-4fc6-bf64-58c913b03dd1 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806306802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2806306802 |
| Directory | /workspace/2.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/2.gpio_stress_all.2972317547 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 5064695041 ps |
| CPU time | 126.39 seconds |
| Started | Jul 18 05:40:50 PM PDT 24 |
| Finished | Jul 18 05:43:02 PM PDT 24 |
| Peak memory | 198340 kb |
| Host | smart-85f97584-d2d3-4c77-bfed-9750e81aeb58 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972317547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g pio_stress_all.2972317547 |
| Directory | /workspace/2.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.3083447414 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 15581929372 ps |
| CPU time | 458.74 seconds |
| Started | Jul 18 05:40:47 PM PDT 24 |
| Finished | Jul 18 05:48:30 PM PDT 24 |
| Peak memory | 198460 kb |
| Host | smart-55788f0d-377e-4823-bfc3-40140e1183a5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3083447414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.3083447414 |
| Directory | /workspace/2.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.gpio_alert_test.2744194915 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 24683191 ps |
| CPU time | 0.56 seconds |
| Started | Jul 18 05:41:33 PM PDT 24 |
| Finished | Jul 18 05:41:49 PM PDT 24 |
| Peak memory | 194200 kb |
| Host | smart-d0d454ba-6617-4fe5-8a17-ac15f3e7e1ff |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744194915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2744194915 |
| Directory | /workspace/20.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3817728371 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 23004502 ps |
| CPU time | 0.73 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:38 PM PDT 24 |
| Peak memory | 195544 kb |
| Host | smart-0fc3a4ed-9a28-467d-b65e-18863bb309f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817728371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3817728371 |
| Directory | /workspace/20.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/20.gpio_filter_stress.1328540057 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 181212139 ps |
| CPU time | 9.42 seconds |
| Started | Jul 18 05:41:30 PM PDT 24 |
| Finished | Jul 18 05:41:55 PM PDT 24 |
| Peak memory | 195772 kb |
| Host | smart-efaa0a8f-c292-40cf-b175-6bc98e410629 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328540057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre ss.1328540057 |
| Directory | /workspace/20.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/20.gpio_full_random.2622192359 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 72077318 ps |
| CPU time | 0.9 seconds |
| Started | Jul 18 05:41:28 PM PDT 24 |
| Finished | Jul 18 05:41:43 PM PDT 24 |
| Peak memory | 197160 kb |
| Host | smart-6219d4ea-1117-4ec8-b670-ecb7628c0b30 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622192359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2622192359 |
| Directory | /workspace/20.gpio_full_random/latest |
| Test location | /workspace/coverage/default/20.gpio_intr_rand_pgm.630671301 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 61362125 ps |
| CPU time | 1.04 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:39 PM PDT 24 |
| Peak memory | 197108 kb |
| Host | smart-4f0cab7d-56d2-4f40-ac54-b768aeec60b0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630671301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.630671301 |
| Directory | /workspace/20.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2229887394 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 360749359 ps |
| CPU time | 3.79 seconds |
| Started | Jul 18 05:41:30 PM PDT 24 |
| Finished | Jul 18 05:41:49 PM PDT 24 |
| Peak memory | 198284 kb |
| Host | smart-61f7aa2d-6aa8-418a-ac24-6f9c479d8bfe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229887394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2229887394 |
| Directory | /workspace/20.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/20.gpio_rand_intr_trigger.210795493 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 111532110 ps |
| CPU time | 2.67 seconds |
| Started | Jul 18 05:41:26 PM PDT 24 |
| Finished | Jul 18 05:41:41 PM PDT 24 |
| Peak memory | 196892 kb |
| Host | smart-4f80e0b9-3468-4381-bfed-e4a68f89aa2d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210795493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger. 210795493 |
| Directory | /workspace/20.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/20.gpio_random_dout_din.4222009775 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 59984321 ps |
| CPU time | 1.13 seconds |
| Started | Jul 18 05:41:30 PM PDT 24 |
| Finished | Jul 18 05:41:52 PM PDT 24 |
| Peak memory | 196204 kb |
| Host | smart-eac7e00b-17a4-4d3c-b85e-7ff0024b39a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4222009775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.4222009775 |
| Directory | /workspace/20.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.118359120 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 36675401 ps |
| CPU time | 0.68 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:38 PM PDT 24 |
| Peak memory | 194588 kb |
| Host | smart-68c211fa-5a8f-4f9e-b9c2-9e09883c4b90 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118359120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup _pulldown.118359120 |
| Directory | /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.946074614 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 181380720 ps |
| CPU time | 2.48 seconds |
| Started | Jul 18 05:41:30 PM PDT 24 |
| Finished | Jul 18 05:41:49 PM PDT 24 |
| Peak memory | 198204 kb |
| Host | smart-b9df8dfa-541f-43a5-bc02-357f70e11ca7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946074614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran dom_long_reg_writes_reg_reads.946074614 |
| Directory | /workspace/20.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/20.gpio_smoke.453054023 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 288782463 ps |
| CPU time | 1.03 seconds |
| Started | Jul 18 05:41:31 PM PDT 24 |
| Finished | Jul 18 05:41:48 PM PDT 24 |
| Peak memory | 196772 kb |
| Host | smart-9e38bcf8-3f52-47b2-b8bb-baf8f8c81a21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=453054023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.453054023 |
| Directory | /workspace/20.gpio_smoke/latest |
| Test location | /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1485498735 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 67258352 ps |
| CPU time | 0.72 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:41:44 PM PDT 24 |
| Peak memory | 194404 kb |
| Host | smart-134e79e8-5c6a-45ad-ae5c-aeac05d47cd0 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485498735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1485498735 |
| Directory | /workspace/20.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/20.gpio_stress_all.4102456072 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 27191118035 ps |
| CPU time | 196.38 seconds |
| Started | Jul 18 05:41:35 PM PDT 24 |
| Finished | Jul 18 05:45:07 PM PDT 24 |
| Peak memory | 198308 kb |
| Host | smart-af30c605-0bf2-4332-83ff-a0ddcd5a8c4b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102456072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. gpio_stress_all.4102456072 |
| Directory | /workspace/20.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.3287977618 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 410636744903 ps |
| CPU time | 2154.57 seconds |
| Started | Jul 18 05:43:36 PM PDT 24 |
| Finished | Jul 18 06:19:46 PM PDT 24 |
| Peak memory | 198440 kb |
| Host | smart-b85b6d74-a70b-4d9f-b8fa-823b5305ddbc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3287977618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.3287977618 |
| Directory | /workspace/20.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.gpio_alert_test.149177761 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 32935885 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:41:31 PM PDT 24 |
| Finished | Jul 18 05:41:48 PM PDT 24 |
| Peak memory | 194832 kb |
| Host | smart-e654d24a-bce0-4e82-9fbe-99909925fc07 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149177761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.149177761 |
| Directory | /workspace/21.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.144393296 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 43772421 ps |
| CPU time | 0.81 seconds |
| Started | Jul 18 05:41:24 PM PDT 24 |
| Finished | Jul 18 05:41:35 PM PDT 24 |
| Peak memory | 196284 kb |
| Host | smart-50e5fa82-1580-4293-8b0a-dbd465d42c77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=144393296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.144393296 |
| Directory | /workspace/21.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/21.gpio_filter_stress.592076818 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 881359570 ps |
| CPU time | 6.94 seconds |
| Started | Jul 18 05:41:31 PM PDT 24 |
| Finished | Jul 18 05:41:54 PM PDT 24 |
| Peak memory | 198172 kb |
| Host | smart-790848a0-b138-4126-b231-f36871718333 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592076818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres s.592076818 |
| Directory | /workspace/21.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/21.gpio_full_random.1320824636 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 155823963 ps |
| CPU time | 0.99 seconds |
| Started | Jul 18 05:41:30 PM PDT 24 |
| Finished | Jul 18 05:41:46 PM PDT 24 |
| Peak memory | 196768 kb |
| Host | smart-bce52c12-7d9d-4bea-8696-983abcf3db27 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320824636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1320824636 |
| Directory | /workspace/21.gpio_full_random/latest |
| Test location | /workspace/coverage/default/21.gpio_intr_rand_pgm.3064038584 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 23055259 ps |
| CPU time | 0.79 seconds |
| Started | Jul 18 05:41:22 PM PDT 24 |
| Finished | Jul 18 05:41:33 PM PDT 24 |
| Peak memory | 195808 kb |
| Host | smart-802cbc07-8c11-485e-94e6-22dff3539de9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064038584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3064038584 |
| Directory | /workspace/21.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1590330158 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 579965899 ps |
| CPU time | 2.38 seconds |
| Started | Jul 18 05:41:28 PM PDT 24 |
| Finished | Jul 18 05:41:44 PM PDT 24 |
| Peak memory | 198184 kb |
| Host | smart-4aee7079-e47c-46ac-bf3a-769d96060092 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590330158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1590330158 |
| Directory | /workspace/21.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/21.gpio_rand_intr_trigger.972454467 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 43706799 ps |
| CPU time | 0.89 seconds |
| Started | Jul 18 05:41:34 PM PDT 24 |
| Finished | Jul 18 05:41:50 PM PDT 24 |
| Peak memory | 195720 kb |
| Host | smart-874f5b34-c559-4de1-b04c-1306006c0c21 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972454467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger. 972454467 |
| Directory | /workspace/21.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/21.gpio_random_dout_din.325291185 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 192995432 ps |
| CPU time | 0.97 seconds |
| Started | Jul 18 05:41:34 PM PDT 24 |
| Finished | Jul 18 05:41:50 PM PDT 24 |
| Peak memory | 196180 kb |
| Host | smart-a130880f-e513-4a8d-a8f6-016c9765a486 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=325291185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.325291185 |
| Directory | /workspace/21.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1078244219 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 72958742 ps |
| CPU time | 0.95 seconds |
| Started | Jul 18 05:41:26 PM PDT 24 |
| Finished | Jul 18 05:41:39 PM PDT 24 |
| Peak memory | 196816 kb |
| Host | smart-a100e49d-7ab1-4d86-940e-005d627612e0 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078244219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu p_pulldown.1078244219 |
| Directory | /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1417338491 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 46682320 ps |
| CPU time | 2.04 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:39 PM PDT 24 |
| Peak memory | 198268 kb |
| Host | smart-4bc06fac-095d-4b89-8908-de6df250607b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417338491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra ndom_long_reg_writes_reg_reads.1417338491 |
| Directory | /workspace/21.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/21.gpio_smoke.809888694 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 36499385 ps |
| CPU time | 1.04 seconds |
| Started | Jul 18 05:41:33 PM PDT 24 |
| Finished | Jul 18 05:41:50 PM PDT 24 |
| Peak memory | 195944 kb |
| Host | smart-1047c203-c1f1-4dc6-9612-64bf0b93d988 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=809888694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.809888694 |
| Directory | /workspace/21.gpio_smoke/latest |
| Test location | /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3872151275 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 61588756 ps |
| CPU time | 0.98 seconds |
| Started | Jul 18 05:41:26 PM PDT 24 |
| Finished | Jul 18 05:41:39 PM PDT 24 |
| Peak memory | 196264 kb |
| Host | smart-b0bdcf87-e2b9-4094-8214-eed017dfe6aa |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872151275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3872151275 |
| Directory | /workspace/21.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/21.gpio_stress_all.180798703 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 4825738311 ps |
| CPU time | 58.93 seconds |
| Started | Jul 18 05:41:30 PM PDT 24 |
| Finished | Jul 18 05:42:44 PM PDT 24 |
| Peak memory | 198288 kb |
| Host | smart-337526ee-9cc1-4914-8c2b-70ca5e6bad58 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180798703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g pio_stress_all.180798703 |
| Directory | /workspace/21.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/22.gpio_alert_test.3614110746 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 81944760 ps |
| CPU time | 0.56 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:41:44 PM PDT 24 |
| Peak memory | 194224 kb |
| Host | smart-bf9c5c03-430f-4152-ae65-df5921e26184 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614110746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3614110746 |
| Directory | /workspace/22.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3399608217 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 18368825 ps |
| CPU time | 0.72 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:37 PM PDT 24 |
| Peak memory | 195172 kb |
| Host | smart-a924f77b-2ceb-4139-8e2a-0c7c8331b73d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399608217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3399608217 |
| Directory | /workspace/22.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/22.gpio_filter_stress.2445660367 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2445123564 ps |
| CPU time | 19.68 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:42:03 PM PDT 24 |
| Peak memory | 197244 kb |
| Host | smart-951b46f9-8cb7-4daa-b5bd-539049c736be |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445660367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre ss.2445660367 |
| Directory | /workspace/22.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/22.gpio_full_random.4276256149 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 70238930 ps |
| CPU time | 0.85 seconds |
| Started | Jul 18 05:41:28 PM PDT 24 |
| Finished | Jul 18 05:41:43 PM PDT 24 |
| Peak memory | 195972 kb |
| Host | smart-9afa22d3-a13b-4660-8cc2-bea7677300c6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276256149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.4276256149 |
| Directory | /workspace/22.gpio_full_random/latest |
| Test location | /workspace/coverage/default/22.gpio_intr_rand_pgm.1218227180 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 279368116 ps |
| CPU time | 1 seconds |
| Started | Jul 18 05:41:31 PM PDT 24 |
| Finished | Jul 18 05:41:47 PM PDT 24 |
| Peak memory | 196156 kb |
| Host | smart-e03d3759-7fe6-4d93-b300-5e38031d5cef |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218227180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1218227180 |
| Directory | /workspace/22.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3449654092 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 212260554 ps |
| CPU time | 2.31 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:39 PM PDT 24 |
| Peak memory | 196548 kb |
| Host | smart-c9870b0f-de83-4b94-a12e-7a0a8483ab29 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449654092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3449654092 |
| Directory | /workspace/22.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/22.gpio_rand_intr_trigger.3224020714 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 113079812 ps |
| CPU time | 3.4 seconds |
| Started | Jul 18 05:41:25 PM PDT 24 |
| Finished | Jul 18 05:41:40 PM PDT 24 |
| Peak memory | 197424 kb |
| Host | smart-9465654c-ee2a-4e00-a99e-c23d0c0e66e5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224020714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger .3224020714 |
| Directory | /workspace/22.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/22.gpio_random_dout_din.3232971314 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 45709572 ps |
| CPU time | 1.03 seconds |
| Started | Jul 18 05:41:30 PM PDT 24 |
| Finished | Jul 18 05:41:46 PM PDT 24 |
| Peak memory | 195976 kb |
| Host | smart-8a7f8357-a6bd-4f58-88d2-b14646a1140e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3232971314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3232971314 |
| Directory | /workspace/22.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2146154937 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 95105975 ps |
| CPU time | 0.93 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:41:45 PM PDT 24 |
| Peak memory | 196080 kb |
| Host | smart-7d65fb85-f932-4356-887c-c2b86d3e7f71 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146154937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu p_pulldown.2146154937 |
| Directory | /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2132993191 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 362590975 ps |
| CPU time | 2.41 seconds |
| Started | Jul 18 05:41:27 PM PDT 24 |
| Finished | Jul 18 05:41:43 PM PDT 24 |
| Peak memory | 198116 kb |
| Host | smart-3e21be55-929d-4a7a-8ac2-a635471d0263 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132993191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra ndom_long_reg_writes_reg_reads.2132993191 |
| Directory | /workspace/22.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/22.gpio_smoke.3004818325 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 95720465 ps |
| CPU time | 1.05 seconds |
| Started | Jul 18 05:41:28 PM PDT 24 |
| Finished | Jul 18 05:41:42 PM PDT 24 |
| Peak memory | 195760 kb |
| Host | smart-68155285-ef5f-41fc-9ff1-b3e502278e23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3004818325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3004818325 |
| Directory | /workspace/22.gpio_smoke/latest |
| Test location | /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.4219138050 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 214622482 ps |
| CPU time | 1.11 seconds |
| Started | Jul 18 05:41:28 PM PDT 24 |
| Finished | Jul 18 05:41:43 PM PDT 24 |
| Peak memory | 195668 kb |
| Host | smart-c9356225-adc6-4cd6-a1f0-838f3a9825db |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219138050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.4219138050 |
| Directory | /workspace/22.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/22.gpio_stress_all.3572508775 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 17333777306 ps |
| CPU time | 71.91 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:42:55 PM PDT 24 |
| Peak memory | 198360 kb |
| Host | smart-51e00a01-1bb6-4e87-916f-01ba61b5e8de |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572508775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. gpio_stress_all.3572508775 |
| Directory | /workspace/22.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.3906147745 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 129948332634 ps |
| CPU time | 1679.54 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 06:09:42 PM PDT 24 |
| Peak memory | 198504 kb |
| Host | smart-ae7a86e7-4073-4556-a70f-89acb49cd980 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3906147745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.3906147745 |
| Directory | /workspace/22.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.gpio_alert_test.2739306594 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 16000087 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:41:27 PM PDT 24 |
| Finished | Jul 18 05:41:41 PM PDT 24 |
| Peak memory | 194324 kb |
| Host | smart-608e3f8c-5365-4ac8-99fc-dc1ede002065 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739306594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2739306594 |
| Directory | /workspace/23.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1260440653 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 24920805 ps |
| CPU time | 0.74 seconds |
| Started | Jul 18 05:41:20 PM PDT 24 |
| Finished | Jul 18 05:41:29 PM PDT 24 |
| Peak memory | 195576 kb |
| Host | smart-ede46547-fa6d-4af9-9076-17e28063fb45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1260440653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1260440653 |
| Directory | /workspace/23.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/23.gpio_filter_stress.972439354 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 433195487 ps |
| CPU time | 11.1 seconds |
| Started | Jul 18 05:41:20 PM PDT 24 |
| Finished | Jul 18 05:41:40 PM PDT 24 |
| Peak memory | 196932 kb |
| Host | smart-2b36accc-8ebf-4717-a6d1-87861e2f78b5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972439354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres s.972439354 |
| Directory | /workspace/23.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/23.gpio_full_random.1716646095 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 94777392 ps |
| CPU time | 0.88 seconds |
| Started | Jul 18 05:41:26 PM PDT 24 |
| Finished | Jul 18 05:41:40 PM PDT 24 |
| Peak memory | 196328 kb |
| Host | smart-b16a5dfb-cbee-4769-b50b-1e2c08e973eb |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716646095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1716646095 |
| Directory | /workspace/23.gpio_full_random/latest |
| Test location | /workspace/coverage/default/23.gpio_intr_rand_pgm.619974221 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 44763500 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:41:19 PM PDT 24 |
| Finished | Jul 18 05:41:27 PM PDT 24 |
| Peak memory | 197868 kb |
| Host | smart-48b62473-5e26-4093-9742-2f123f721259 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619974221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.619974221 |
| Directory | /workspace/23.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.642334364 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 423083859 ps |
| CPU time | 1.51 seconds |
| Started | Jul 18 05:41:31 PM PDT 24 |
| Finished | Jul 18 05:41:49 PM PDT 24 |
| Peak memory | 198288 kb |
| Host | smart-d8bde3c2-3cc7-4091-af8b-577e9827a86a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642334364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 23.gpio_intr_with_filter_rand_intr_event.642334364 |
| Directory | /workspace/23.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/23.gpio_rand_intr_trigger.1873103382 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 76895446 ps |
| CPU time | 2.13 seconds |
| Started | Jul 18 05:41:20 PM PDT 24 |
| Finished | Jul 18 05:41:31 PM PDT 24 |
| Peak memory | 198248 kb |
| Host | smart-e660e985-f76e-4d5d-bbfa-d59cc4976af6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873103382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger .1873103382 |
| Directory | /workspace/23.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/23.gpio_random_dout_din.1804189699 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 282782113 ps |
| CPU time | 0.83 seconds |
| Started | Jul 18 05:41:20 PM PDT 24 |
| Finished | Jul 18 05:41:29 PM PDT 24 |
| Peak memory | 196896 kb |
| Host | smart-5dd1ad8a-e851-4567-a732-291453e11d3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1804189699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1804189699 |
| Directory | /workspace/23.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2220697025 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 47361442 ps |
| CPU time | 1.02 seconds |
| Started | Jul 18 05:41:24 PM PDT 24 |
| Finished | Jul 18 05:41:35 PM PDT 24 |
| Peak memory | 196100 kb |
| Host | smart-233957e5-7b87-4e13-92d7-3b58acc50eec |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220697025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu p_pulldown.2220697025 |
| Directory | /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1747393938 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 563182190 ps |
| CPU time | 6.63 seconds |
| Started | Jul 18 05:41:27 PM PDT 24 |
| Finished | Jul 18 05:41:47 PM PDT 24 |
| Peak memory | 198388 kb |
| Host | smart-72a71e93-5d28-4913-aec4-717bdc14f56a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747393938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra ndom_long_reg_writes_reg_reads.1747393938 |
| Directory | /workspace/23.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/23.gpio_smoke.3397471101 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 220785227 ps |
| CPU time | 1.42 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:41:44 PM PDT 24 |
| Peak memory | 197116 kb |
| Host | smart-f0e8bfa0-40c9-4311-89ce-ebcf1338aafc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397471101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3397471101 |
| Directory | /workspace/23.gpio_smoke/latest |
| Test location | /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3562272723 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 261478207 ps |
| CPU time | 1.11 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:41:44 PM PDT 24 |
| Peak memory | 196776 kb |
| Host | smart-a68c5f1b-653f-4f37-8aa2-bb2e0990eaeb |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562272723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3562272723 |
| Directory | /workspace/23.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/23.gpio_stress_all.3756433342 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 14971075779 ps |
| CPU time | 205.16 seconds |
| Started | Jul 18 05:41:24 PM PDT 24 |
| Finished | Jul 18 05:45:00 PM PDT 24 |
| Peak memory | 198356 kb |
| Host | smart-a2005f2c-3d2b-40d0-ab4c-7e306aff15ab |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756433342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. gpio_stress_all.3756433342 |
| Directory | /workspace/23.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/24.gpio_alert_test.2345139325 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 29514382 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:41:52 PM PDT 24 |
| Finished | Jul 18 05:42:05 PM PDT 24 |
| Peak memory | 194160 kb |
| Host | smart-081387bd-c725-4d17-a9da-c3e49ff5f2b6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345139325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2345139325 |
| Directory | /workspace/24.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2426779425 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 71175548 ps |
| CPU time | 0.82 seconds |
| Started | Jul 18 05:41:29 PM PDT 24 |
| Finished | Jul 18 05:41:45 PM PDT 24 |
| Peak memory | 195592 kb |
| Host | smart-e893de34-81b2-4ab3-b966-81e701383016 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2426779425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2426779425 |
| Directory | /workspace/24.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/24.gpio_filter_stress.3739195346 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 928672471 ps |
| CPU time | 14.77 seconds |
| Started | Jul 18 05:41:40 PM PDT 24 |
| Finished | Jul 18 05:42:11 PM PDT 24 |
| Peak memory | 197216 kb |
| Host | smart-0b6b7f97-5a79-45c9-9496-cacf1dbec963 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739195346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre ss.3739195346 |
| Directory | /workspace/24.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/24.gpio_full_random.480062417 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 311215627 ps |
| CPU time | 0.92 seconds |
| Started | Jul 18 05:41:39 PM PDT 24 |
| Finished | Jul 18 05:41:58 PM PDT 24 |
| Peak memory | 196308 kb |
| Host | smart-e5309d5f-dc9f-4879-8ae4-f1731e2e6bd3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480062417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.480062417 |
| Directory | /workspace/24.gpio_full_random/latest |
| Test location | /workspace/coverage/default/24.gpio_intr_rand_pgm.1504892179 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 139622190 ps |
| CPU time | 0.77 seconds |
| Started | Jul 18 05:41:34 PM PDT 24 |
| Finished | Jul 18 05:41:50 PM PDT 24 |
| Peak memory | 196468 kb |
| Host | smart-de689225-9763-4781-9afd-c76433c6a72d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504892179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1504892179 |
| Directory | /workspace/24.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1802206625 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 399211283 ps |
| CPU time | 2.45 seconds |
| Started | Jul 18 05:41:35 PM PDT 24 |
| Finished | Jul 18 05:41:54 PM PDT 24 |
| Peak memory | 198260 kb |
| Host | smart-1b1f486f-e431-4530-af5a-e14defa9c891 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802206625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1802206625 |
| Directory | /workspace/24.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/24.gpio_rand_intr_trigger.1525875683 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 208458379 ps |
| CPU time | 2.96 seconds |
| Started | Jul 18 05:41:34 PM PDT 24 |
| Finished | Jul 18 05:41:52 PM PDT 24 |
| Peak memory | 196040 kb |
| Host | smart-afaba9e3-78f3-42b0-bff3-8acd20547945 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525875683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger .1525875683 |
| Directory | /workspace/24.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/24.gpio_random_dout_din.3709761040 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 133033091 ps |
| CPU time | 1 seconds |
| Started | Jul 18 05:41:31 PM PDT 24 |
| Finished | Jul 18 05:41:48 PM PDT 24 |
| Peak memory | 196176 kb |
| Host | smart-c3546e67-6bf1-4f0a-b305-d776b4a1bdb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3709761040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3709761040 |
| Directory | /workspace/24.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.72723621 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 95970240 ps |
| CPU time | 0.86 seconds |
| Started | Jul 18 05:41:34 PM PDT 24 |
| Finished | Jul 18 05:41:50 PM PDT 24 |
| Peak memory | 196204 kb |
| Host | smart-ae1ebde0-567b-45bf-9359-0313353b379c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72723621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup_ pulldown.72723621 |
| Directory | /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2070234336 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 432243575 ps |
| CPU time | 5.27 seconds |
| Started | Jul 18 05:41:36 PM PDT 24 |
| Finished | Jul 18 05:41:57 PM PDT 24 |
| Peak memory | 198148 kb |
| Host | smart-919fef5e-1ff3-4bb6-9883-a7b5de20de7a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070234336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra ndom_long_reg_writes_reg_reads.2070234336 |
| Directory | /workspace/24.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/24.gpio_smoke.2604454023 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 330175074 ps |
| CPU time | 1.32 seconds |
| Started | Jul 18 05:41:30 PM PDT 24 |
| Finished | Jul 18 05:41:47 PM PDT 24 |
| Peak memory | 198220 kb |
| Host | smart-ccb228ab-786e-42ec-a1f4-a6b5efb4f5fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2604454023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2604454023 |
| Directory | /workspace/24.gpio_smoke/latest |
| Test location | /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.687468654 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 66232715 ps |
| CPU time | 1.27 seconds |
| Started | Jul 18 05:41:27 PM PDT 24 |
| Finished | Jul 18 05:41:41 PM PDT 24 |
| Peak memory | 197496 kb |
| Host | smart-da7104fa-3d39-4cbe-a58c-71dedde3f8d3 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687468654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.687468654 |
| Directory | /workspace/24.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/24.gpio_stress_all.4025172408 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1797867638 ps |
| CPU time | 21.86 seconds |
| Started | Jul 18 05:41:43 PM PDT 24 |
| Finished | Jul 18 05:42:21 PM PDT 24 |
| Peak memory | 198244 kb |
| Host | smart-c6333eb9-f28a-4d46-8f42-f2c34fc6edf4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025172408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. gpio_stress_all.4025172408 |
| Directory | /workspace/24.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.402963874 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 71313898732 ps |
| CPU time | 1253.23 seconds |
| Started | Jul 18 05:41:44 PM PDT 24 |
| Finished | Jul 18 06:02:53 PM PDT 24 |
| Peak memory | 198552 kb |
| Host | smart-85a18f6e-5c7e-4d1d-9c1c-3615542bae5f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =402963874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.402963874 |
| Directory | /workspace/24.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.gpio_alert_test.1979557729 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 19362272 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:41:39 PM PDT 24 |
| Finished | Jul 18 05:41:55 PM PDT 24 |
| Peak memory | 194164 kb |
| Host | smart-be9595cd-93d7-4d04-af28-d7461455e9aa |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979557729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1979557729 |
| Directory | /workspace/25.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2343428996 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 107367924 ps |
| CPU time | 0.93 seconds |
| Started | Jul 18 05:41:39 PM PDT 24 |
| Finished | Jul 18 05:41:56 PM PDT 24 |
| Peak memory | 194468 kb |
| Host | smart-92695c44-650b-4cc2-be3d-0fd2f41ba54a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2343428996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2343428996 |
| Directory | /workspace/25.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/25.gpio_filter_stress.2804811891 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1475192990 ps |
| CPU time | 11.15 seconds |
| Started | Jul 18 05:41:35 PM PDT 24 |
| Finished | Jul 18 05:42:02 PM PDT 24 |
| Peak memory | 197060 kb |
| Host | smart-c68b4371-9ad2-4196-876e-e592a8a6aaca |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804811891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre ss.2804811891 |
| Directory | /workspace/25.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/25.gpio_full_random.1509558011 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 293115187 ps |
| CPU time | 0.77 seconds |
| Started | Jul 18 05:41:39 PM PDT 24 |
| Finished | Jul 18 05:41:56 PM PDT 24 |
| Peak memory | 196180 kb |
| Host | smart-982a82e8-0a3d-4f01-b053-baa73b4e84c9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509558011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1509558011 |
| Directory | /workspace/25.gpio_full_random/latest |
| Test location | /workspace/coverage/default/25.gpio_intr_rand_pgm.3900020835 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 469532662 ps |
| CPU time | 1.42 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:55 PM PDT 24 |
| Peak memory | 197244 kb |
| Host | smart-f3c8bfb4-4dde-499d-b07f-4eeef2475a7d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900020835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3900020835 |
| Directory | /workspace/25.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1518999900 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 65853731 ps |
| CPU time | 2.35 seconds |
| Started | Jul 18 05:41:51 PM PDT 24 |
| Finished | Jul 18 05:42:06 PM PDT 24 |
| Peak memory | 198248 kb |
| Host | smart-f2852aa2-8dc7-45e5-b138-858ba08fe3ba |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518999900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1518999900 |
| Directory | /workspace/25.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/25.gpio_rand_intr_trigger.1005456141 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 85328809 ps |
| CPU time | 2.59 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:56 PM PDT 24 |
| Peak memory | 197456 kb |
| Host | smart-10dd50d9-78e9-49f2-9589-e9271c6b2557 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005456141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger .1005456141 |
| Directory | /workspace/25.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/25.gpio_random_dout_din.3470430357 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 141806843 ps |
| CPU time | 1.08 seconds |
| Started | Jul 18 05:41:47 PM PDT 24 |
| Finished | Jul 18 05:42:02 PM PDT 24 |
| Peak memory | 196156 kb |
| Host | smart-9ec0ee46-e044-458f-9292-70132faafb1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470430357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3470430357 |
| Directory | /workspace/25.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.835174189 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 52538123 ps |
| CPU time | 1.23 seconds |
| Started | Jul 18 05:41:49 PM PDT 24 |
| Finished | Jul 18 05:42:04 PM PDT 24 |
| Peak memory | 198220 kb |
| Host | smart-1b8d5883-e864-4c8c-8cd0-4c57232934ab |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835174189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup _pulldown.835174189 |
| Directory | /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2291923565 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 305238027 ps |
| CPU time | 3.05 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:57 PM PDT 24 |
| Peak memory | 198188 kb |
| Host | smart-ee95800d-7031-4575-a897-e8d20677d4ab |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291923565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra ndom_long_reg_writes_reg_reads.2291923565 |
| Directory | /workspace/25.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/25.gpio_smoke.4157242317 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 67132541 ps |
| CPU time | 1.39 seconds |
| Started | Jul 18 05:41:39 PM PDT 24 |
| Finished | Jul 18 05:41:57 PM PDT 24 |
| Peak memory | 196732 kb |
| Host | smart-097b2bf2-52a2-4b08-905e-a51d0dbc211d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4157242317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.4157242317 |
| Directory | /workspace/25.gpio_smoke/latest |
| Test location | /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3411213717 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 74456876 ps |
| CPU time | 0.94 seconds |
| Started | Jul 18 05:42:31 PM PDT 24 |
| Finished | Jul 18 05:42:47 PM PDT 24 |
| Peak memory | 195964 kb |
| Host | smart-4c2bf674-e231-4439-81c4-96a23b89d532 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411213717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3411213717 |
| Directory | /workspace/25.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/25.gpio_stress_all.841940313 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 72401358663 ps |
| CPU time | 203.32 seconds |
| Started | Jul 18 05:41:35 PM PDT 24 |
| Finished | Jul 18 05:45:14 PM PDT 24 |
| Peak memory | 198348 kb |
| Host | smart-0dca817c-b5f0-4c00-bc91-4066b4ef5de9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841940313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g pio_stress_all.841940313 |
| Directory | /workspace/25.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3271582626 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 112766310078 ps |
| CPU time | 1537.03 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 06:07:31 PM PDT 24 |
| Peak memory | 198520 kb |
| Host | smart-bef66d34-71f9-41be-85bd-a48b553565da |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3271582626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3271582626 |
| Directory | /workspace/25.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.gpio_alert_test.1790376674 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 19112025 ps |
| CPU time | 0.6 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:54 PM PDT 24 |
| Peak memory | 194224 kb |
| Host | smart-0505e239-572e-4181-b0a4-cbf955470fca |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790376674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1790376674 |
| Directory | /workspace/26.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.4100594177 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 18060029 ps |
| CPU time | 0.61 seconds |
| Started | Jul 18 05:41:35 PM PDT 24 |
| Finished | Jul 18 05:41:52 PM PDT 24 |
| Peak memory | 194776 kb |
| Host | smart-0e137b3f-6acc-4077-892e-ca9d54a19f66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4100594177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.4100594177 |
| Directory | /workspace/26.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/26.gpio_filter_stress.3989868746 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1345571583 ps |
| CPU time | 8.59 seconds |
| Started | Jul 18 05:41:35 PM PDT 24 |
| Finished | Jul 18 05:42:00 PM PDT 24 |
| Peak memory | 198204 kb |
| Host | smart-172ab4cb-ef1b-47d3-b531-f7b1448dd86e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989868746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre ss.3989868746 |
| Directory | /workspace/26.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/26.gpio_full_random.423105879 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 204347661 ps |
| CPU time | 0.77 seconds |
| Started | Jul 18 05:41:40 PM PDT 24 |
| Finished | Jul 18 05:41:57 PM PDT 24 |
| Peak memory | 196172 kb |
| Host | smart-fd8d425f-40da-4a65-a8a2-c72798e2cc63 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423105879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.423105879 |
| Directory | /workspace/26.gpio_full_random/latest |
| Test location | /workspace/coverage/default/26.gpio_intr_rand_pgm.2793206461 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 23605057 ps |
| CPU time | 0.73 seconds |
| Started | Jul 18 05:41:45 PM PDT 24 |
| Finished | Jul 18 05:42:01 PM PDT 24 |
| Peak memory | 194476 kb |
| Host | smart-e0a02f2f-4dd6-47c0-8d07-224161060c92 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793206461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2793206461 |
| Directory | /workspace/26.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1059482860 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 151918706 ps |
| CPU time | 1.75 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:56 PM PDT 24 |
| Peak memory | 196496 kb |
| Host | smart-ab79697b-f1f9-4967-8551-b2cb9fd4eec3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059482860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1059482860 |
| Directory | /workspace/26.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/26.gpio_rand_intr_trigger.934828456 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 103508957 ps |
| CPU time | 3.02 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:56 PM PDT 24 |
| Peak memory | 198332 kb |
| Host | smart-d54a82af-6da7-42ec-b777-ef4b06189b60 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934828456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger. 934828456 |
| Directory | /workspace/26.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/26.gpio_random_dout_din.2923701402 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 35662467 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:41:40 PM PDT 24 |
| Finished | Jul 18 05:41:58 PM PDT 24 |
| Peak memory | 196020 kb |
| Host | smart-fe6192a0-2491-4fcb-a303-0d4f2e3ac3fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923701402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2923701402 |
| Directory | /workspace/26.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3781317546 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 280780886 ps |
| CPU time | 1.37 seconds |
| Started | Jul 18 05:41:37 PM PDT 24 |
| Finished | Jul 18 05:41:53 PM PDT 24 |
| Peak memory | 198244 kb |
| Host | smart-86e7d8b1-33c6-40d3-b84c-b6c60d1df405 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781317546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu p_pulldown.3781317546 |
| Directory | /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2793958088 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 374534240 ps |
| CPU time | 4.76 seconds |
| Started | Jul 18 05:41:37 PM PDT 24 |
| Finished | Jul 18 05:41:57 PM PDT 24 |
| Peak memory | 198140 kb |
| Host | smart-18c802f9-ab41-4861-a183-7c63d06b5c52 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793958088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra ndom_long_reg_writes_reg_reads.2793958088 |
| Directory | /workspace/26.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/26.gpio_smoke.2524295607 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 62108949 ps |
| CPU time | 0.96 seconds |
| Started | Jul 18 05:41:36 PM PDT 24 |
| Finished | Jul 18 05:41:58 PM PDT 24 |
| Peak memory | 195792 kb |
| Host | smart-5e7e4af1-cd0e-4f9c-940f-98d2b8447d3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524295607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2524295607 |
| Directory | /workspace/26.gpio_smoke/latest |
| Test location | /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2485887940 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 164371325 ps |
| CPU time | 1.28 seconds |
| Started | Jul 18 05:41:36 PM PDT 24 |
| Finished | Jul 18 05:41:53 PM PDT 24 |
| Peak memory | 196912 kb |
| Host | smart-39fb449c-3e82-408e-8d1b-7a0de567651d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485887940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2485887940 |
| Directory | /workspace/26.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/26.gpio_stress_all.3702855854 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1848164856 ps |
| CPU time | 51.31 seconds |
| Started | Jul 18 05:41:44 PM PDT 24 |
| Finished | Jul 18 05:42:51 PM PDT 24 |
| Peak memory | 198284 kb |
| Host | smart-edb83e77-7a4f-41ab-bf97-e3ce3fa9be57 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702855854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. gpio_stress_all.3702855854 |
| Directory | /workspace/26.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/27.gpio_alert_test.3406829845 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 17249030 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:41:52 PM PDT 24 |
| Finished | Jul 18 05:42:05 PM PDT 24 |
| Peak memory | 194428 kb |
| Host | smart-4dd4f74e-13c6-4ffa-8d21-36b2f4dd3d2a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406829845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3406829845 |
| Directory | /workspace/27.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1761704313 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 19263176 ps |
| CPU time | 0.64 seconds |
| Started | Jul 18 05:41:33 PM PDT 24 |
| Finished | Jul 18 05:41:49 PM PDT 24 |
| Peak memory | 194828 kb |
| Host | smart-e4f16473-27b4-4d68-8fc8-d0be08a33680 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1761704313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1761704313 |
| Directory | /workspace/27.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/27.gpio_filter_stress.1865743216 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1534090395 ps |
| CPU time | 25.86 seconds |
| Started | Jul 18 05:41:35 PM PDT 24 |
| Finished | Jul 18 05:42:17 PM PDT 24 |
| Peak memory | 198240 kb |
| Host | smart-ac455d2f-10cf-4669-9504-94a504ab3286 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865743216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre ss.1865743216 |
| Directory | /workspace/27.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/27.gpio_full_random.3886708047 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 125795529 ps |
| CPU time | 0.91 seconds |
| Started | Jul 18 05:41:35 PM PDT 24 |
| Finished | Jul 18 05:41:51 PM PDT 24 |
| Peak memory | 197372 kb |
| Host | smart-5329d743-df05-4101-b399-f88af09ec4f8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886708047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3886708047 |
| Directory | /workspace/27.gpio_full_random/latest |
| Test location | /workspace/coverage/default/27.gpio_intr_rand_pgm.1291372140 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 70494459 ps |
| CPU time | 0.64 seconds |
| Started | Jul 18 05:41:37 PM PDT 24 |
| Finished | Jul 18 05:41:53 PM PDT 24 |
| Peak memory | 195160 kb |
| Host | smart-3b65e07d-2c16-4458-b540-eeb7ed29cc97 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291372140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1291372140 |
| Directory | /workspace/27.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2328825632 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 62159178 ps |
| CPU time | 2.67 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:57 PM PDT 24 |
| Peak memory | 198280 kb |
| Host | smart-ceb85b4a-5854-4239-b5ba-caa32869c0d3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328825632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2328825632 |
| Directory | /workspace/27.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/27.gpio_rand_intr_trigger.2751105485 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 322553618 ps |
| CPU time | 2.08 seconds |
| Started | Jul 18 05:41:54 PM PDT 24 |
| Finished | Jul 18 05:42:08 PM PDT 24 |
| Peak memory | 196084 kb |
| Host | smart-f159edf8-f3a8-4540-8561-9c28e29ff41a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751105485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger .2751105485 |
| Directory | /workspace/27.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/27.gpio_random_dout_din.3333346188 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 121889289 ps |
| CPU time | 0.92 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:55 PM PDT 24 |
| Peak memory | 197520 kb |
| Host | smart-a23a1ac0-e508-4521-8987-6cc5656bd0dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3333346188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3333346188 |
| Directory | /workspace/27.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1016061835 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 73318771 ps |
| CPU time | 1.26 seconds |
| Started | Jul 18 05:41:51 PM PDT 24 |
| Finished | Jul 18 05:42:05 PM PDT 24 |
| Peak memory | 197060 kb |
| Host | smart-92e4496d-1b76-4cf9-98a0-2b661c16ffe2 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016061835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu p_pulldown.1016061835 |
| Directory | /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.752676302 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 751025532 ps |
| CPU time | 3.06 seconds |
| Started | Jul 18 05:41:39 PM PDT 24 |
| Finished | Jul 18 05:41:58 PM PDT 24 |
| Peak memory | 196124 kb |
| Host | smart-ca24b09f-8a7f-4bc3-9074-065e3cb89bd7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752676302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran dom_long_reg_writes_reg_reads.752676302 |
| Directory | /workspace/27.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/27.gpio_smoke.3522863817 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 181573862 ps |
| CPU time | 1.11 seconds |
| Started | Jul 18 05:41:52 PM PDT 24 |
| Finished | Jul 18 05:42:05 PM PDT 24 |
| Peak memory | 196596 kb |
| Host | smart-051fb432-14ac-4d9c-a672-c2c78cf9536f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3522863817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3522863817 |
| Directory | /workspace/27.gpio_smoke/latest |
| Test location | /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2446583362 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 38443899 ps |
| CPU time | 0.88 seconds |
| Started | Jul 18 05:41:36 PM PDT 24 |
| Finished | Jul 18 05:41:53 PM PDT 24 |
| Peak memory | 195612 kb |
| Host | smart-324489fb-5073-458b-99b7-e51e21742a87 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446583362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2446583362 |
| Directory | /workspace/27.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/27.gpio_stress_all.3401580634 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4302393920 ps |
| CPU time | 57.68 seconds |
| Started | Jul 18 05:41:35 PM PDT 24 |
| Finished | Jul 18 05:42:49 PM PDT 24 |
| Peak memory | 198320 kb |
| Host | smart-9094c56b-928d-46f7-9865-29f9498537a2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401580634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. gpio_stress_all.3401580634 |
| Directory | /workspace/27.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/28.gpio_alert_test.1394085707 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 46805731 ps |
| CPU time | 0.57 seconds |
| Started | Jul 18 05:41:39 PM PDT 24 |
| Finished | Jul 18 05:41:55 PM PDT 24 |
| Peak memory | 194204 kb |
| Host | smart-9aed1379-e084-4dfa-aacb-7dcac5f74bbb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394085707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1394085707 |
| Directory | /workspace/28.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.4252128354 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 137968076 ps |
| CPU time | 0.95 seconds |
| Started | Jul 18 05:41:54 PM PDT 24 |
| Finished | Jul 18 05:42:07 PM PDT 24 |
| Peak memory | 196132 kb |
| Host | smart-ee751c94-f2b0-44f0-9e50-685ffb65151b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4252128354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.4252128354 |
| Directory | /workspace/28.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/28.gpio_filter_stress.4016356007 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1223336587 ps |
| CPU time | 11.02 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:42:05 PM PDT 24 |
| Peak memory | 197216 kb |
| Host | smart-eb6a347b-04ff-4c19-8327-f9b35627afa8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016356007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre ss.4016356007 |
| Directory | /workspace/28.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/28.gpio_full_random.759531417 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 333975853 ps |
| CPU time | 0.79 seconds |
| Started | Jul 18 05:41:50 PM PDT 24 |
| Finished | Jul 18 05:42:04 PM PDT 24 |
| Peak memory | 196168 kb |
| Host | smart-7510d49c-de72-4236-a111-e24a932e5b30 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759531417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.759531417 |
| Directory | /workspace/28.gpio_full_random/latest |
| Test location | /workspace/coverage/default/28.gpio_intr_rand_pgm.2671134313 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 225057967 ps |
| CPU time | 1.53 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:55 PM PDT 24 |
| Peak memory | 196124 kb |
| Host | smart-6c425361-083d-4c0c-a19c-7acdccbe3584 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671134313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2671134313 |
| Directory | /workspace/28.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.234026043 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 104012078 ps |
| CPU time | 1.24 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:55 PM PDT 24 |
| Peak memory | 196756 kb |
| Host | smart-a141e507-1ff1-4fea-901a-ea0ca6b7a642 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234026043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 28.gpio_intr_with_filter_rand_intr_event.234026043 |
| Directory | /workspace/28.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/28.gpio_rand_intr_trigger.2092103069 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 118142183 ps |
| CPU time | 2.42 seconds |
| Started | Jul 18 05:41:45 PM PDT 24 |
| Finished | Jul 18 05:42:03 PM PDT 24 |
| Peak memory | 197400 kb |
| Host | smart-21e6172e-89bd-4667-8d0a-41772cccbf3b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092103069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger .2092103069 |
| Directory | /workspace/28.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/28.gpio_random_dout_din.2435767273 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 84602622 ps |
| CPU time | 1.03 seconds |
| Started | Jul 18 05:41:37 PM PDT 24 |
| Finished | Jul 18 05:41:54 PM PDT 24 |
| Peak memory | 196868 kb |
| Host | smart-0e4525f3-8477-4823-b403-ca47782d3860 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2435767273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2435767273 |
| Directory | /workspace/28.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1278620113 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 203093641 ps |
| CPU time | 1.19 seconds |
| Started | Jul 18 05:41:52 PM PDT 24 |
| Finished | Jul 18 05:42:06 PM PDT 24 |
| Peak memory | 197492 kb |
| Host | smart-00e4555a-dd97-4257-be84-a8083d074b44 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278620113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu p_pulldown.1278620113 |
| Directory | /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.966742563 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 366470536 ps |
| CPU time | 6.16 seconds |
| Started | Jul 18 05:41:51 PM PDT 24 |
| Finished | Jul 18 05:42:10 PM PDT 24 |
| Peak memory | 198180 kb |
| Host | smart-65135f23-86b4-465c-9714-c5f417134ebc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966742563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran dom_long_reg_writes_reg_reads.966742563 |
| Directory | /workspace/28.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/28.gpio_smoke.620007614 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 49879944 ps |
| CPU time | 1.1 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:55 PM PDT 24 |
| Peak memory | 196488 kb |
| Host | smart-688c110a-cce8-40eb-a792-2d7ccd4f82f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620007614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.620007614 |
| Directory | /workspace/28.gpio_smoke/latest |
| Test location | /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.393019120 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 41994606 ps |
| CPU time | 1.07 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:54 PM PDT 24 |
| Peak memory | 196488 kb |
| Host | smart-c0ebde3a-c41a-42fd-8c1c-f309cf09b27c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393019120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.393019120 |
| Directory | /workspace/28.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/28.gpio_stress_all.3236990197 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3594060234 ps |
| CPU time | 94.7 seconds |
| Started | Jul 18 05:41:43 PM PDT 24 |
| Finished | Jul 18 05:43:34 PM PDT 24 |
| Peak memory | 198320 kb |
| Host | smart-9669540e-fe3b-444e-b069-de50767d5fe0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236990197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. gpio_stress_all.3236990197 |
| Directory | /workspace/28.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/29.gpio_alert_test.56484749 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 13233593 ps |
| CPU time | 0.56 seconds |
| Started | Jul 18 05:41:41 PM PDT 24 |
| Finished | Jul 18 05:41:59 PM PDT 24 |
| Peak memory | 194156 kb |
| Host | smart-20c12b4d-2610-4d3e-bd8e-e68e617178dd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56484749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.56484749 |
| Directory | /workspace/29.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1067603261 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 18472750 ps |
| CPU time | 0.62 seconds |
| Started | Jul 18 05:41:41 PM PDT 24 |
| Finished | Jul 18 05:41:59 PM PDT 24 |
| Peak memory | 194892 kb |
| Host | smart-8a8c7294-a198-4fec-8619-5e8d014c3320 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067603261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1067603261 |
| Directory | /workspace/29.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/29.gpio_filter_stress.23899892 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 1205657356 ps |
| CPU time | 12.37 seconds |
| Started | Jul 18 05:41:43 PM PDT 24 |
| Finished | Jul 18 05:42:12 PM PDT 24 |
| Peak memory | 197000 kb |
| Host | smart-ae1c696b-e80c-4a1b-8269-efc09443fcce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23899892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_ stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stress .23899892 |
| Directory | /workspace/29.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/29.gpio_full_random.263207804 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 63689414 ps |
| CPU time | 0.95 seconds |
| Started | Jul 18 05:41:52 PM PDT 24 |
| Finished | Jul 18 05:42:06 PM PDT 24 |
| Peak memory | 196828 kb |
| Host | smart-7a4ad04b-b00d-4f56-82bc-54c6a131dd49 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263207804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.263207804 |
| Directory | /workspace/29.gpio_full_random/latest |
| Test location | /workspace/coverage/default/29.gpio_intr_rand_pgm.527156983 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 30022799 ps |
| CPU time | 0.81 seconds |
| Started | Jul 18 05:41:45 PM PDT 24 |
| Finished | Jul 18 05:42:01 PM PDT 24 |
| Peak memory | 196224 kb |
| Host | smart-4d1a6b76-867c-43a4-afe7-eca1d1520ba5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527156983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.527156983 |
| Directory | /workspace/29.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3016261231 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 241987881 ps |
| CPU time | 2.79 seconds |
| Started | Jul 18 05:41:51 PM PDT 24 |
| Finished | Jul 18 05:42:07 PM PDT 24 |
| Peak memory | 198256 kb |
| Host | smart-8d5f9fad-3820-4512-b14a-94c4a601a65c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016261231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3016261231 |
| Directory | /workspace/29.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/29.gpio_rand_intr_trigger.1538699671 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 365598560 ps |
| CPU time | 2.09 seconds |
| Started | Jul 18 05:41:48 PM PDT 24 |
| Finished | Jul 18 05:42:04 PM PDT 24 |
| Peak memory | 196444 kb |
| Host | smart-42aebf37-81b8-45ba-8948-23ee27ad2042 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538699671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger .1538699671 |
| Directory | /workspace/29.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/29.gpio_random_dout_din.1063034693 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 273927135 ps |
| CPU time | 1.34 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:54 PM PDT 24 |
| Peak memory | 196792 kb |
| Host | smart-ca08da49-d9da-42af-a232-731617263384 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063034693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1063034693 |
| Directory | /workspace/29.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3319361369 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 164367326 ps |
| CPU time | 1.08 seconds |
| Started | Jul 18 05:41:41 PM PDT 24 |
| Finished | Jul 18 05:41:58 PM PDT 24 |
| Peak memory | 196896 kb |
| Host | smart-c6423990-f6f7-423a-a793-b59db08ecd39 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319361369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu p_pulldown.3319361369 |
| Directory | /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3304551613 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 185880524 ps |
| CPU time | 2.27 seconds |
| Started | Jul 18 05:41:43 PM PDT 24 |
| Finished | Jul 18 05:42:01 PM PDT 24 |
| Peak memory | 198160 kb |
| Host | smart-ff648c68-8447-43df-a70a-823880eaef6c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304551613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra ndom_long_reg_writes_reg_reads.3304551613 |
| Directory | /workspace/29.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/29.gpio_smoke.2957008527 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 76063885 ps |
| CPU time | 1.39 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:55 PM PDT 24 |
| Peak memory | 198216 kb |
| Host | smart-28601edb-5e6a-4c35-87d6-3a852aecb282 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2957008527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2957008527 |
| Directory | /workspace/29.gpio_smoke/latest |
| Test location | /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1342614759 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 52473375 ps |
| CPU time | 1 seconds |
| Started | Jul 18 05:41:53 PM PDT 24 |
| Finished | Jul 18 05:42:07 PM PDT 24 |
| Peak memory | 196496 kb |
| Host | smart-132376a0-a3ca-475c-9a3a-d45091298947 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342614759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1342614759 |
| Directory | /workspace/29.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/29.gpio_stress_all.1874250154 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 27284765699 ps |
| CPU time | 91.94 seconds |
| Started | Jul 18 05:41:49 PM PDT 24 |
| Finished | Jul 18 05:43:35 PM PDT 24 |
| Peak memory | 198308 kb |
| Host | smart-63a339a8-fc3c-4091-92e4-73a0f3766423 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874250154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. gpio_stress_all.1874250154 |
| Directory | /workspace/29.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/3.gpio_alert_test.164816062 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12260388 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:40:50 PM PDT 24 |
| Finished | Jul 18 05:40:56 PM PDT 24 |
| Peak memory | 194372 kb |
| Host | smart-358ca4e8-a8ce-411b-b42a-084ec0f06dfc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164816062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.164816062 |
| Directory | /workspace/3.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.171165035 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 41625445 ps |
| CPU time | 0.84 seconds |
| Started | Jul 18 05:40:51 PM PDT 24 |
| Finished | Jul 18 05:40:57 PM PDT 24 |
| Peak memory | 195416 kb |
| Host | smart-1e577c15-fdf9-4a5b-ba88-4254dc2bea69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=171165035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.171165035 |
| Directory | /workspace/3.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/3.gpio_filter_stress.2930626904 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 491124890 ps |
| CPU time | 7.56 seconds |
| Started | Jul 18 05:40:46 PM PDT 24 |
| Finished | Jul 18 05:40:57 PM PDT 24 |
| Peak memory | 196840 kb |
| Host | smart-e388c121-7df8-4a90-aec5-eee8ec7ed02e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930626904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres s.2930626904 |
| Directory | /workspace/3.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/3.gpio_full_random.3845960646 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 86726571 ps |
| CPU time | 1.15 seconds |
| Started | Jul 18 05:40:52 PM PDT 24 |
| Finished | Jul 18 05:40:59 PM PDT 24 |
| Peak memory | 196944 kb |
| Host | smart-e1c65bf8-bbd9-421f-a124-dbc020116adf |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845960646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3845960646 |
| Directory | /workspace/3.gpio_full_random/latest |
| Test location | /workspace/coverage/default/3.gpio_intr_rand_pgm.2821583836 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 196856893 ps |
| CPU time | 1.62 seconds |
| Started | Jul 18 05:40:48 PM PDT 24 |
| Finished | Jul 18 05:40:54 PM PDT 24 |
| Peak memory | 197328 kb |
| Host | smart-d05e47a5-08da-4505-881d-425309526eed |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821583836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2821583836 |
| Directory | /workspace/3.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1383009090 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 545051821 ps |
| CPU time | 2.14 seconds |
| Started | Jul 18 05:40:46 PM PDT 24 |
| Finished | Jul 18 05:40:53 PM PDT 24 |
| Peak memory | 198244 kb |
| Host | smart-21ecaf55-e6c0-4c6b-affa-d342bd187c33 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383009090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1383009090 |
| Directory | /workspace/3.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/3.gpio_rand_intr_trigger.1166783154 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 136973437 ps |
| CPU time | 2.35 seconds |
| Started | Jul 18 05:40:49 PM PDT 24 |
| Finished | Jul 18 05:40:57 PM PDT 24 |
| Peak memory | 196056 kb |
| Host | smart-a80bfa24-da95-4b3f-8450-bc90182710df |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166783154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger. 1166783154 |
| Directory | /workspace/3.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/3.gpio_random_dout_din.3979745693 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 73219661 ps |
| CPU time | 0.99 seconds |
| Started | Jul 18 05:40:43 PM PDT 24 |
| Finished | Jul 18 05:40:47 PM PDT 24 |
| Peak memory | 196024 kb |
| Host | smart-53ee1db2-5856-4e11-8950-72db8b8f3904 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3979745693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3979745693 |
| Directory | /workspace/3.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2939606048 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 52238322 ps |
| CPU time | 1.35 seconds |
| Started | Jul 18 05:40:45 PM PDT 24 |
| Finished | Jul 18 05:40:49 PM PDT 24 |
| Peak memory | 198304 kb |
| Host | smart-227836aa-0405-44a6-b832-2aff5fe3a903 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939606048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup _pulldown.2939606048 |
| Directory | /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1439845679 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 553826009 ps |
| CPU time | 4.99 seconds |
| Started | Jul 18 05:40:48 PM PDT 24 |
| Finished | Jul 18 05:40:58 PM PDT 24 |
| Peak memory | 198196 kb |
| Host | smart-929b9693-f24e-4e16-8e46-6c6d8c26029c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439845679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran dom_long_reg_writes_reg_reads.1439845679 |
| Directory | /workspace/3.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/3.gpio_sec_cm.2059732076 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 119714762 ps |
| CPU time | 0.81 seconds |
| Started | Jul 18 05:40:50 PM PDT 24 |
| Finished | Jul 18 05:40:56 PM PDT 24 |
| Peak memory | 214272 kb |
| Host | smart-f8f2a4c3-49d4-4268-b0da-b4e915549e57 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059732076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2059732076 |
| Directory | /workspace/3.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/3.gpio_smoke.3579981713 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 263017569 ps |
| CPU time | 1.18 seconds |
| Started | Jul 18 05:40:44 PM PDT 24 |
| Finished | Jul 18 05:40:48 PM PDT 24 |
| Peak memory | 197108 kb |
| Host | smart-1126c6db-362c-46f0-9cde-f673ff7edb5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579981713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3579981713 |
| Directory | /workspace/3.gpio_smoke/latest |
| Test location | /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3471687180 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 33175576 ps |
| CPU time | 1.04 seconds |
| Started | Jul 18 05:40:44 PM PDT 24 |
| Finished | Jul 18 05:40:48 PM PDT 24 |
| Peak memory | 196488 kb |
| Host | smart-b9fca846-a90e-477a-ac1f-9e6e4300c4f3 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471687180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3471687180 |
| Directory | /workspace/3.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/3.gpio_stress_all.1347262411 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 7127336448 ps |
| CPU time | 159.97 seconds |
| Started | Jul 18 05:40:52 PM PDT 24 |
| Finished | Jul 18 05:43:38 PM PDT 24 |
| Peak memory | 198336 kb |
| Host | smart-56d8f598-b5be-422f-af33-143581599108 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347262411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g pio_stress_all.1347262411 |
| Directory | /workspace/3.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/30.gpio_alert_test.175051109 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 14571356 ps |
| CPU time | 0.61 seconds |
| Started | Jul 18 05:41:54 PM PDT 24 |
| Finished | Jul 18 05:42:07 PM PDT 24 |
| Peak memory | 194176 kb |
| Host | smart-83c3addb-b91b-4191-b0ab-b8832acdd9b7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175051109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.175051109 |
| Directory | /workspace/30.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3664843996 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 61676570 ps |
| CPU time | 0.6 seconds |
| Started | Jul 18 05:41:50 PM PDT 24 |
| Finished | Jul 18 05:42:04 PM PDT 24 |
| Peak memory | 194048 kb |
| Host | smart-7e2e5673-b6fb-4e55-bf90-e9e0e5d0fa61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3664843996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3664843996 |
| Directory | /workspace/30.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/30.gpio_filter_stress.119238438 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 361664230 ps |
| CPU time | 4.47 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:57 PM PDT 24 |
| Peak memory | 195828 kb |
| Host | smart-ceafaaf9-1b43-4f44-8427-bce1d2cd7d95 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119238438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres s.119238438 |
| Directory | /workspace/30.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/30.gpio_full_random.3872978795 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 64086966 ps |
| CPU time | 0.85 seconds |
| Started | Jul 18 05:41:54 PM PDT 24 |
| Finished | Jul 18 05:42:07 PM PDT 24 |
| Peak memory | 196220 kb |
| Host | smart-3e1c13a9-9f8a-44d2-9119-a9000c3a0249 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872978795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3872978795 |
| Directory | /workspace/30.gpio_full_random/latest |
| Test location | /workspace/coverage/default/30.gpio_intr_rand_pgm.1485911475 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 684671261 ps |
| CPU time | 1.19 seconds |
| Started | Jul 18 05:41:54 PM PDT 24 |
| Finished | Jul 18 05:42:07 PM PDT 24 |
| Peak memory | 197280 kb |
| Host | smart-ddaa06cd-ddd6-45fb-b2bf-9326f3243130 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485911475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1485911475 |
| Directory | /workspace/30.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2284765853 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 31047955 ps |
| CPU time | 1.33 seconds |
| Started | Jul 18 05:41:46 PM PDT 24 |
| Finished | Jul 18 05:42:03 PM PDT 24 |
| Peak memory | 196852 kb |
| Host | smart-a4190b8f-b48c-45d9-a472-37dc034d7691 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284765853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2284765853 |
| Directory | /workspace/30.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/30.gpio_rand_intr_trigger.2501995543 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 267333038 ps |
| CPU time | 1.63 seconds |
| Started | Jul 18 05:41:55 PM PDT 24 |
| Finished | Jul 18 05:42:08 PM PDT 24 |
| Peak memory | 196676 kb |
| Host | smart-98a090d9-9c21-4514-ac4c-e19f2df58657 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501995543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger .2501995543 |
| Directory | /workspace/30.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/30.gpio_random_dout_din.761742820 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 19865468 ps |
| CPU time | 0.79 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:54 PM PDT 24 |
| Peak memory | 196624 kb |
| Host | smart-959ca464-b091-464e-b3eb-2f5419063347 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=761742820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.761742820 |
| Directory | /workspace/30.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3709498328 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 18810618 ps |
| CPU time | 0.82 seconds |
| Started | Jul 18 05:41:54 PM PDT 24 |
| Finished | Jul 18 05:42:07 PM PDT 24 |
| Peak memory | 196436 kb |
| Host | smart-e5c98258-5e32-4fad-a4fd-3e0e46109d1e |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709498328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu p_pulldown.3709498328 |
| Directory | /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3320312933 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 222661689 ps |
| CPU time | 2.82 seconds |
| Started | Jul 18 05:41:52 PM PDT 24 |
| Finished | Jul 18 05:42:08 PM PDT 24 |
| Peak memory | 198216 kb |
| Host | smart-476a715e-bd99-45ad-af30-0a76c5423693 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320312933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra ndom_long_reg_writes_reg_reads.3320312933 |
| Directory | /workspace/30.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/30.gpio_smoke.2184512433 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 456625829 ps |
| CPU time | 1.03 seconds |
| Started | Jul 18 05:41:57 PM PDT 24 |
| Finished | Jul 18 05:42:09 PM PDT 24 |
| Peak memory | 196448 kb |
| Host | smart-54e07d1b-57df-4cb8-ad95-b1ea156b51ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2184512433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2184512433 |
| Directory | /workspace/30.gpio_smoke/latest |
| Test location | /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.949455998 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 197303539 ps |
| CPU time | 1.1 seconds |
| Started | Jul 18 05:41:55 PM PDT 24 |
| Finished | Jul 18 05:42:08 PM PDT 24 |
| Peak memory | 195968 kb |
| Host | smart-0903199c-a2bf-463c-993b-77028d85f219 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949455998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.949455998 |
| Directory | /workspace/30.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/30.gpio_stress_all.2254097984 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 71921748147 ps |
| CPU time | 138.67 seconds |
| Started | Jul 18 05:41:56 PM PDT 24 |
| Finished | Jul 18 05:44:26 PM PDT 24 |
| Peak memory | 198316 kb |
| Host | smart-0732fa38-f478-4e68-8f9b-352083a838f0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254097984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. gpio_stress_all.2254097984 |
| Directory | /workspace/30.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/31.gpio_alert_test.380838881 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 15155791 ps |
| CPU time | 0.57 seconds |
| Started | Jul 18 05:41:52 PM PDT 24 |
| Finished | Jul 18 05:42:05 PM PDT 24 |
| Peak memory | 194876 kb |
| Host | smart-4a717a7e-fceb-4589-bc4b-28eae9f95d2c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380838881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.380838881 |
| Directory | /workspace/31.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2007260907 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 50289943 ps |
| CPU time | 0.84 seconds |
| Started | Jul 18 05:41:56 PM PDT 24 |
| Finished | Jul 18 05:42:08 PM PDT 24 |
| Peak memory | 196776 kb |
| Host | smart-c006c8d9-9123-4982-be1e-2a4d17420d18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007260907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2007260907 |
| Directory | /workspace/31.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/31.gpio_filter_stress.2349936829 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 18360941524 ps |
| CPU time | 25.71 seconds |
| Started | Jul 18 05:41:39 PM PDT 24 |
| Finished | Jul 18 05:42:20 PM PDT 24 |
| Peak memory | 197040 kb |
| Host | smart-8cf54658-ed45-4106-9c89-2600d2728799 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349936829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre ss.2349936829 |
| Directory | /workspace/31.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/31.gpio_full_random.1884139173 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 214696230 ps |
| CPU time | 0.86 seconds |
| Started | Jul 18 05:41:38 PM PDT 24 |
| Finished | Jul 18 05:41:54 PM PDT 24 |
| Peak memory | 196320 kb |
| Host | smart-05e1f24d-1027-496b-9b64-e9268267cb7d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884139173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1884139173 |
| Directory | /workspace/31.gpio_full_random/latest |
| Test location | /workspace/coverage/default/31.gpio_intr_rand_pgm.3783911679 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 127656877 ps |
| CPU time | 0.9 seconds |
| Started | Jul 18 05:41:47 PM PDT 24 |
| Finished | Jul 18 05:42:02 PM PDT 24 |
| Peak memory | 196956 kb |
| Host | smart-d89436bb-9abf-46b9-bd46-cbcbdbcade9c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783911679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3783911679 |
| Directory | /workspace/31.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2042863004 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 453938274 ps |
| CPU time | 1.71 seconds |
| Started | Jul 18 05:41:54 PM PDT 24 |
| Finished | Jul 18 05:42:08 PM PDT 24 |
| Peak memory | 197052 kb |
| Host | smart-baa935b4-d971-44e3-be01-ae9599b7dbfe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042863004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2042863004 |
| Directory | /workspace/31.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/31.gpio_rand_intr_trigger.333331569 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 449056433 ps |
| CPU time | 2.89 seconds |
| Started | Jul 18 05:41:54 PM PDT 24 |
| Finished | Jul 18 05:42:09 PM PDT 24 |
| Peak memory | 197484 kb |
| Host | smart-53be50ac-f64c-483b-b93b-c02cc60e1de9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333331569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger. 333331569 |
| Directory | /workspace/31.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/31.gpio_random_dout_din.2180049631 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 40476206 ps |
| CPU time | 0.9 seconds |
| Started | Jul 18 05:41:50 PM PDT 24 |
| Finished | Jul 18 05:42:04 PM PDT 24 |
| Peak memory | 196132 kb |
| Host | smart-0e8f82d3-3854-4b3d-ad86-4e614ecdf8d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2180049631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2180049631 |
| Directory | /workspace/31.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2641576817 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 19960292 ps |
| CPU time | 0.77 seconds |
| Started | Jul 18 05:41:41 PM PDT 24 |
| Finished | Jul 18 05:41:59 PM PDT 24 |
| Peak memory | 195264 kb |
| Host | smart-11f7f00f-8887-4057-9b5f-49f4c8b5d07f |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641576817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu p_pulldown.2641576817 |
| Directory | /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1900540659 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 679486235 ps |
| CPU time | 5.28 seconds |
| Started | Jul 18 05:41:41 PM PDT 24 |
| Finished | Jul 18 05:42:03 PM PDT 24 |
| Peak memory | 198080 kb |
| Host | smart-aa9b96b0-e02c-47a8-967b-df03d54d06b8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900540659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra ndom_long_reg_writes_reg_reads.1900540659 |
| Directory | /workspace/31.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/31.gpio_smoke.2249954372 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 148266784 ps |
| CPU time | 1.27 seconds |
| Started | Jul 18 05:41:56 PM PDT 24 |
| Finished | Jul 18 05:42:09 PM PDT 24 |
| Peak memory | 197072 kb |
| Host | smart-c93b5642-6f7f-4de3-93d2-c1ffa9d3c760 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2249954372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2249954372 |
| Directory | /workspace/31.gpio_smoke/latest |
| Test location | /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3810694367 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 315046602 ps |
| CPU time | 1.52 seconds |
| Started | Jul 18 05:41:47 PM PDT 24 |
| Finished | Jul 18 05:42:03 PM PDT 24 |
| Peak memory | 196944 kb |
| Host | smart-85bf0d5c-c2bc-4d39-aafc-b925f9c8e7d7 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810694367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3810694367 |
| Directory | /workspace/31.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/31.gpio_stress_all.1713198587 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 15864303053 ps |
| CPU time | 113.74 seconds |
| Started | Jul 18 05:41:46 PM PDT 24 |
| Finished | Jul 18 05:43:55 PM PDT 24 |
| Peak memory | 198292 kb |
| Host | smart-91c0c14c-8079-4e03-b1bd-d81a9a9c113b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713198587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. gpio_stress_all.1713198587 |
| Directory | /workspace/31.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/32.gpio_alert_test.4221539220 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 13379430 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:41:55 PM PDT 24 |
| Finished | Jul 18 05:42:07 PM PDT 24 |
| Peak memory | 195256 kb |
| Host | smart-084eb0ec-935a-4ed3-8b5a-441aaa60db7c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221539220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.4221539220 |
| Directory | /workspace/32.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1444157490 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 257697680 ps |
| CPU time | 0.76 seconds |
| Started | Jul 18 05:41:43 PM PDT 24 |
| Finished | Jul 18 05:42:00 PM PDT 24 |
| Peak memory | 195560 kb |
| Host | smart-2d4b44cf-d129-4383-a32a-1699e68a7820 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1444157490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1444157490 |
| Directory | /workspace/32.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/32.gpio_filter_stress.583779941 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 293354531 ps |
| CPU time | 3.99 seconds |
| Started | Jul 18 05:41:39 PM PDT 24 |
| Finished | Jul 18 05:41:59 PM PDT 24 |
| Peak memory | 196204 kb |
| Host | smart-8ac078cd-14d5-47cc-b723-a8de0899a047 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583779941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres s.583779941 |
| Directory | /workspace/32.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/32.gpio_full_random.1108932400 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 78900027 ps |
| CPU time | 0.81 seconds |
| Started | Jul 18 05:41:50 PM PDT 24 |
| Finished | Jul 18 05:42:04 PM PDT 24 |
| Peak memory | 196776 kb |
| Host | smart-6d0ab17c-90b0-419a-a604-e326fa7fda4c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108932400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1108932400 |
| Directory | /workspace/32.gpio_full_random/latest |
| Test location | /workspace/coverage/default/32.gpio_intr_rand_pgm.3224056003 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 93758276 ps |
| CPU time | 1.29 seconds |
| Started | Jul 18 05:41:40 PM PDT 24 |
| Finished | Jul 18 05:41:59 PM PDT 24 |
| Peak memory | 197164 kb |
| Host | smart-53a07c9b-862f-4e14-a7d2-c15b70f67e69 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224056003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3224056003 |
| Directory | /workspace/32.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.549381652 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 342758054 ps |
| CPU time | 3.54 seconds |
| Started | Jul 18 05:41:49 PM PDT 24 |
| Finished | Jul 18 05:42:06 PM PDT 24 |
| Peak memory | 198316 kb |
| Host | smart-00368007-c776-4885-83ee-b610a2eb5870 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549381652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 32.gpio_intr_with_filter_rand_intr_event.549381652 |
| Directory | /workspace/32.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/32.gpio_rand_intr_trigger.3334846373 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 151299169 ps |
| CPU time | 2.47 seconds |
| Started | Jul 18 05:41:47 PM PDT 24 |
| Finished | Jul 18 05:42:04 PM PDT 24 |
| Peak memory | 197448 kb |
| Host | smart-111ba955-04e1-4b80-a0c0-9b66a7d14609 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334846373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger .3334846373 |
| Directory | /workspace/32.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/32.gpio_random_dout_din.2100737255 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 90240328 ps |
| CPU time | 0.96 seconds |
| Started | Jul 18 05:41:49 PM PDT 24 |
| Finished | Jul 18 05:42:03 PM PDT 24 |
| Peak memory | 196140 kb |
| Host | smart-bca4f597-4e03-403b-beae-88e6db37b628 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2100737255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2100737255 |
| Directory | /workspace/32.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3458795 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 53508282 ps |
| CPU time | 1.22 seconds |
| Started | Jul 18 05:41:48 PM PDT 24 |
| Finished | Jul 18 05:42:03 PM PDT 24 |
| Peak memory | 197012 kb |
| Host | smart-b92c6b85-fb1b-42a5-bbf0-4139b13d883d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup_p ulldown.3458795 |
| Directory | /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2186027927 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1398026910 ps |
| CPU time | 3.58 seconds |
| Started | Jul 18 05:41:37 PM PDT 24 |
| Finished | Jul 18 05:41:56 PM PDT 24 |
| Peak memory | 198252 kb |
| Host | smart-7eb58fec-5942-4c37-9bbd-5b86bb8784f1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186027927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra ndom_long_reg_writes_reg_reads.2186027927 |
| Directory | /workspace/32.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/32.gpio_smoke.520038535 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 154142575 ps |
| CPU time | 1.14 seconds |
| Started | Jul 18 05:41:39 PM PDT 24 |
| Finished | Jul 18 05:41:56 PM PDT 24 |
| Peak memory | 195816 kb |
| Host | smart-5dcd1c0d-05e8-4e97-a888-9b780d242819 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=520038535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.520038535 |
| Directory | /workspace/32.gpio_smoke/latest |
| Test location | /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3111386819 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 67673464 ps |
| CPU time | 1.32 seconds |
| Started | Jul 18 05:41:51 PM PDT 24 |
| Finished | Jul 18 05:42:05 PM PDT 24 |
| Peak memory | 198192 kb |
| Host | smart-09be8f56-a45e-418a-9f2c-1f4848a179cd |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111386819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3111386819 |
| Directory | /workspace/32.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/32.gpio_stress_all.3955453055 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 17697996609 ps |
| CPU time | 102.82 seconds |
| Started | Jul 18 05:41:40 PM PDT 24 |
| Finished | Jul 18 05:43:40 PM PDT 24 |
| Peak memory | 198344 kb |
| Host | smart-29ad82ac-c453-4f6a-a34f-e07aa6b0dffe |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955453055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. gpio_stress_all.3955453055 |
| Directory | /workspace/32.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/33.gpio_alert_test.4110273405 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 12999347 ps |
| CPU time | 0.57 seconds |
| Started | Jul 18 05:42:06 PM PDT 24 |
| Finished | Jul 18 05:42:17 PM PDT 24 |
| Peak memory | 194864 kb |
| Host | smart-d5ba085c-daaa-4d8b-9ff0-d270f8290f7a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110273405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.4110273405 |
| Directory | /workspace/33.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.71323823 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 248880031 ps |
| CPU time | 0.91 seconds |
| Started | Jul 18 05:42:06 PM PDT 24 |
| Finished | Jul 18 05:42:18 PM PDT 24 |
| Peak memory | 196464 kb |
| Host | smart-82ce2977-5688-4fdf-8a66-b8a3b851cb31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71323823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.71323823 |
| Directory | /workspace/33.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/33.gpio_filter_stress.3839375144 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 576990620 ps |
| CPU time | 18.82 seconds |
| Started | Jul 18 05:42:03 PM PDT 24 |
| Finished | Jul 18 05:42:33 PM PDT 24 |
| Peak memory | 198176 kb |
| Host | smart-c3003765-d9e6-4e0b-88b2-0dd95537872a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839375144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre ss.3839375144 |
| Directory | /workspace/33.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/33.gpio_full_random.4196384266 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 268918685 ps |
| CPU time | 1 seconds |
| Started | Jul 18 05:42:06 PM PDT 24 |
| Finished | Jul 18 05:42:18 PM PDT 24 |
| Peak memory | 196920 kb |
| Host | smart-8163c0bd-acdc-4f1a-b777-e75603a9284c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196384266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.4196384266 |
| Directory | /workspace/33.gpio_full_random/latest |
| Test location | /workspace/coverage/default/33.gpio_intr_rand_pgm.217609833 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 49059897 ps |
| CPU time | 1.49 seconds |
| Started | Jul 18 05:42:06 PM PDT 24 |
| Finished | Jul 18 05:42:19 PM PDT 24 |
| Peak memory | 197368 kb |
| Host | smart-5d084f53-9f77-4fff-ba3e-6fd69d7e80ab |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217609833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.217609833 |
| Directory | /workspace/33.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1008346035 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 994807067 ps |
| CPU time | 2.2 seconds |
| Started | Jul 18 05:42:09 PM PDT 24 |
| Finished | Jul 18 05:42:24 PM PDT 24 |
| Peak memory | 196704 kb |
| Host | smart-ad4bb137-9002-4c80-8755-fdd43c17e80c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008346035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1008346035 |
| Directory | /workspace/33.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/33.gpio_rand_intr_trigger.2211485914 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 81375036 ps |
| CPU time | 1.5 seconds |
| Started | Jul 18 05:42:06 PM PDT 24 |
| Finished | Jul 18 05:42:19 PM PDT 24 |
| Peak memory | 196196 kb |
| Host | smart-8e13996e-c849-4916-8793-a4306dcf6a93 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211485914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger .2211485914 |
| Directory | /workspace/33.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/33.gpio_random_dout_din.1518737414 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 121945237 ps |
| CPU time | 1.01 seconds |
| Started | Jul 18 05:41:52 PM PDT 24 |
| Finished | Jul 18 05:42:06 PM PDT 24 |
| Peak memory | 196908 kb |
| Host | smart-28189f8c-7715-4a88-a03f-786cc86ad0bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1518737414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1518737414 |
| Directory | /workspace/33.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3214990469 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 81282087 ps |
| CPU time | 1.05 seconds |
| Started | Jul 18 05:42:05 PM PDT 24 |
| Finished | Jul 18 05:42:17 PM PDT 24 |
| Peak memory | 196064 kb |
| Host | smart-3e750f14-e2d3-4d82-a97d-41b1a051fae1 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214990469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu p_pulldown.3214990469 |
| Directory | /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.753280707 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 52261213 ps |
| CPU time | 1.26 seconds |
| Started | Jul 18 05:42:08 PM PDT 24 |
| Finished | Jul 18 05:42:21 PM PDT 24 |
| Peak memory | 198164 kb |
| Host | smart-fb662701-e13e-4e0b-b2ba-70d4a7dd84eb |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753280707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran dom_long_reg_writes_reg_reads.753280707 |
| Directory | /workspace/33.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/33.gpio_smoke.378320215 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 111772952 ps |
| CPU time | 0.86 seconds |
| Started | Jul 18 05:41:48 PM PDT 24 |
| Finished | Jul 18 05:42:02 PM PDT 24 |
| Peak memory | 195432 kb |
| Host | smart-ea8cba08-2ca0-48b0-b293-c4a25d46a298 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=378320215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.378320215 |
| Directory | /workspace/33.gpio_smoke/latest |
| Test location | /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.676099048 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 55376207 ps |
| CPU time | 1.04 seconds |
| Started | Jul 18 05:41:47 PM PDT 24 |
| Finished | Jul 18 05:42:02 PM PDT 24 |
| Peak memory | 195744 kb |
| Host | smart-2a4dfe6a-8a29-48be-8cb4-ff80f2e516b5 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676099048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.676099048 |
| Directory | /workspace/33.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/33.gpio_stress_all.1628715492 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 116785523260 ps |
| CPU time | 195.14 seconds |
| Started | Jul 18 05:42:07 PM PDT 24 |
| Finished | Jul 18 05:45:34 PM PDT 24 |
| Peak memory | 198400 kb |
| Host | smart-a84c45e7-7732-43d4-b8c3-3b28f46316e6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628715492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. gpio_stress_all.1628715492 |
| Directory | /workspace/33.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/34.gpio_alert_test.1269353990 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 14879252 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:42:05 PM PDT 24 |
| Finished | Jul 18 05:42:16 PM PDT 24 |
| Peak memory | 194896 kb |
| Host | smart-0d352097-7c9a-45a9-a63b-2ac7db725f9d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269353990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1269353990 |
| Directory | /workspace/34.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2487109476 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 22385769 ps |
| CPU time | 0.78 seconds |
| Started | Jul 18 05:42:09 PM PDT 24 |
| Finished | Jul 18 05:42:23 PM PDT 24 |
| Peak memory | 196268 kb |
| Host | smart-d142adf7-0a2f-4476-a76f-a9c667e94fe2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487109476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2487109476 |
| Directory | /workspace/34.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/34.gpio_filter_stress.3390663255 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 260579542 ps |
| CPU time | 8.95 seconds |
| Started | Jul 18 05:42:07 PM PDT 24 |
| Finished | Jul 18 05:42:27 PM PDT 24 |
| Peak memory | 197156 kb |
| Host | smart-49b54561-03fb-42e3-b8bb-fa8f5c92ef19 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390663255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre ss.3390663255 |
| Directory | /workspace/34.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/34.gpio_full_random.3989012285 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 157198566 ps |
| CPU time | 0.74 seconds |
| Started | Jul 18 05:42:05 PM PDT 24 |
| Finished | Jul 18 05:42:16 PM PDT 24 |
| Peak memory | 194800 kb |
| Host | smart-fbb3c109-46c2-40ae-9965-0e5171c39ebc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989012285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3989012285 |
| Directory | /workspace/34.gpio_full_random/latest |
| Test location | /workspace/coverage/default/34.gpio_intr_rand_pgm.1859916976 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 41648881 ps |
| CPU time | 0.8 seconds |
| Started | Jul 18 05:42:09 PM PDT 24 |
| Finished | Jul 18 05:42:22 PM PDT 24 |
| Peak memory | 195764 kb |
| Host | smart-c4c227e5-dbcf-4ae0-9329-f0e1809fa978 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859916976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1859916976 |
| Directory | /workspace/34.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.4016739015 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 72564517 ps |
| CPU time | 3.03 seconds |
| Started | Jul 18 05:42:04 PM PDT 24 |
| Finished | Jul 18 05:42:18 PM PDT 24 |
| Peak memory | 198216 kb |
| Host | smart-4c91fd91-6419-4981-a845-fb383843851a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016739015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.gpio_intr_with_filter_rand_intr_event.4016739015 |
| Directory | /workspace/34.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/34.gpio_rand_intr_trigger.187426890 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 48988437 ps |
| CPU time | 0.99 seconds |
| Started | Jul 18 05:42:00 PM PDT 24 |
| Finished | Jul 18 05:42:10 PM PDT 24 |
| Peak memory | 195576 kb |
| Host | smart-7bbcdf94-e4b5-4b94-8889-7c0d0e8b0af2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187426890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger. 187426890 |
| Directory | /workspace/34.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/34.gpio_random_dout_din.2014450262 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 120972476 ps |
| CPU time | 0.96 seconds |
| Started | Jul 18 05:42:04 PM PDT 24 |
| Finished | Jul 18 05:42:16 PM PDT 24 |
| Peak memory | 196888 kb |
| Host | smart-3bd57c09-d789-466b-8180-81b8751b623f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014450262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2014450262 |
| Directory | /workspace/34.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.595592039 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 103714594 ps |
| CPU time | 1.24 seconds |
| Started | Jul 18 05:42:12 PM PDT 24 |
| Finished | Jul 18 05:42:26 PM PDT 24 |
| Peak memory | 197332 kb |
| Host | smart-090e4a3f-a79b-4e18-bc8d-7f44854f83d6 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595592039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup _pulldown.595592039 |
| Directory | /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3814239750 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 95826243 ps |
| CPU time | 1.33 seconds |
| Started | Jul 18 05:42:04 PM PDT 24 |
| Finished | Jul 18 05:42:16 PM PDT 24 |
| Peak memory | 198224 kb |
| Host | smart-12d1ae0a-f440-42b5-b991-2b828f9f107f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814239750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra ndom_long_reg_writes_reg_reads.3814239750 |
| Directory | /workspace/34.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/34.gpio_smoke.2117937893 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 112323577 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:42:07 PM PDT 24 |
| Finished | Jul 18 05:42:20 PM PDT 24 |
| Peak memory | 195368 kb |
| Host | smart-980c7c62-ac79-46e4-b51a-045c94673de3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117937893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2117937893 |
| Directory | /workspace/34.gpio_smoke/latest |
| Test location | /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2955901813 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 179497338 ps |
| CPU time | 1.32 seconds |
| Started | Jul 18 05:42:07 PM PDT 24 |
| Finished | Jul 18 05:42:20 PM PDT 24 |
| Peak memory | 196968 kb |
| Host | smart-5c2cc82b-2f26-4618-94df-4c8d3b719989 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955901813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2955901813 |
| Directory | /workspace/34.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/34.gpio_stress_all.523587198 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 2595796612 ps |
| CPU time | 48.49 seconds |
| Started | Jul 18 05:42:05 PM PDT 24 |
| Finished | Jul 18 05:43:04 PM PDT 24 |
| Peak memory | 198332 kb |
| Host | smart-849f03f6-59b1-49ad-978d-721500c40b3e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523587198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g pio_stress_all.523587198 |
| Directory | /workspace/34.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/35.gpio_alert_test.3117480445 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 27253879 ps |
| CPU time | 0.57 seconds |
| Started | Jul 18 05:42:04 PM PDT 24 |
| Finished | Jul 18 05:42:15 PM PDT 24 |
| Peak memory | 194160 kb |
| Host | smart-84c2925f-561e-4c96-909b-d19d0a87b8cb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117480445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3117480445 |
| Directory | /workspace/35.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2029152874 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 63044903 ps |
| CPU time | 0.84 seconds |
| Started | Jul 18 05:43:16 PM PDT 24 |
| Finished | Jul 18 05:43:34 PM PDT 24 |
| Peak memory | 196796 kb |
| Host | smart-57cb9104-e838-4dca-82f2-3e9887c0ec74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029152874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2029152874 |
| Directory | /workspace/35.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/35.gpio_filter_stress.878798971 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 763872641 ps |
| CPU time | 8.01 seconds |
| Started | Jul 18 05:42:04 PM PDT 24 |
| Finished | Jul 18 05:42:23 PM PDT 24 |
| Peak memory | 195756 kb |
| Host | smart-0498451a-d4c6-49ba-8d01-96903e57bb1d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878798971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres s.878798971 |
| Directory | /workspace/35.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/35.gpio_full_random.3810720936 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 62279471 ps |
| CPU time | 0.81 seconds |
| Started | Jul 18 05:42:10 PM PDT 24 |
| Finished | Jul 18 05:42:24 PM PDT 24 |
| Peak memory | 196000 kb |
| Host | smart-5acbb39a-3d89-4633-b974-c7ff47eb3d28 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810720936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3810720936 |
| Directory | /workspace/35.gpio_full_random/latest |
| Test location | /workspace/coverage/default/35.gpio_intr_rand_pgm.251081580 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 19096329 ps |
| CPU time | 0.82 seconds |
| Started | Jul 18 05:42:07 PM PDT 24 |
| Finished | Jul 18 05:42:19 PM PDT 24 |
| Peak memory | 195624 kb |
| Host | smart-ca47a889-d7bc-4fa2-b43e-a98b106bbc7f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251081580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.251081580 |
| Directory | /workspace/35.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2842906330 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 238219027 ps |
| CPU time | 2.66 seconds |
| Started | Jul 18 05:42:05 PM PDT 24 |
| Finished | Jul 18 05:42:18 PM PDT 24 |
| Peak memory | 198244 kb |
| Host | smart-f65e219a-b6be-486a-9478-a7d9d0268292 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842906330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2842906330 |
| Directory | /workspace/35.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/35.gpio_rand_intr_trigger.3789330001 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 106651952 ps |
| CPU time | 3.06 seconds |
| Started | Jul 18 05:42:08 PM PDT 24 |
| Finished | Jul 18 05:42:24 PM PDT 24 |
| Peak memory | 198296 kb |
| Host | smart-7eebaa9c-4242-407d-a97d-a8cb627b48d5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789330001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger .3789330001 |
| Directory | /workspace/35.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/35.gpio_random_dout_din.2597548596 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 120813434 ps |
| CPU time | 1.12 seconds |
| Started | Jul 18 05:42:06 PM PDT 24 |
| Finished | Jul 18 05:42:18 PM PDT 24 |
| Peak memory | 197520 kb |
| Host | smart-149d8f05-6fe6-495c-b68c-ba50f7d1191c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597548596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2597548596 |
| Directory | /workspace/35.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.326990422 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 55714398 ps |
| CPU time | 1.39 seconds |
| Started | Jul 18 05:42:06 PM PDT 24 |
| Finished | Jul 18 05:42:18 PM PDT 24 |
| Peak memory | 198304 kb |
| Host | smart-39e766a1-f7b9-4790-9979-c884cc6a0881 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326990422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup _pulldown.326990422 |
| Directory | /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/35.gpio_smoke.2915165747 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 147878488 ps |
| CPU time | 1.23 seconds |
| Started | Jul 18 05:42:03 PM PDT 24 |
| Finished | Jul 18 05:42:15 PM PDT 24 |
| Peak memory | 197180 kb |
| Host | smart-95c3acd8-4d2d-43a3-b982-c166e059349e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915165747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2915165747 |
| Directory | /workspace/35.gpio_smoke/latest |
| Test location | /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.75304793 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 70161194 ps |
| CPU time | 1.23 seconds |
| Started | Jul 18 05:42:07 PM PDT 24 |
| Finished | Jul 18 05:42:20 PM PDT 24 |
| Peak memory | 197080 kb |
| Host | smart-7188f410-5d09-48ea-b9ea-a91f6335fbb5 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75304793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.75304793 |
| Directory | /workspace/35.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/35.gpio_stress_all.2272933928 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 12449670340 ps |
| CPU time | 175.48 seconds |
| Started | Jul 18 05:42:04 PM PDT 24 |
| Finished | Jul 18 05:45:10 PM PDT 24 |
| Peak memory | 198344 kb |
| Host | smart-e510fe32-50a7-4cf2-ae0d-f2c98dc3657c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272933928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. gpio_stress_all.2272933928 |
| Directory | /workspace/35.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/36.gpio_alert_test.2579367647 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 15154407 ps |
| CPU time | 0.64 seconds |
| Started | Jul 18 05:42:08 PM PDT 24 |
| Finished | Jul 18 05:42:20 PM PDT 24 |
| Peak memory | 194220 kb |
| Host | smart-c3196869-bea2-4218-903c-1b68652d225f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579367647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2579367647 |
| Directory | /workspace/36.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3488033951 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 24389765 ps |
| CPU time | 0.81 seconds |
| Started | Jul 18 05:42:03 PM PDT 24 |
| Finished | Jul 18 05:42:15 PM PDT 24 |
| Peak memory | 195400 kb |
| Host | smart-75caee57-7a77-44d5-8b89-35d5be38a17f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3488033951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3488033951 |
| Directory | /workspace/36.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/36.gpio_filter_stress.255512623 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 243326014 ps |
| CPU time | 8.27 seconds |
| Started | Jul 18 05:42:00 PM PDT 24 |
| Finished | Jul 18 05:42:18 PM PDT 24 |
| Peak memory | 196976 kb |
| Host | smart-fbaaef6c-8347-4128-9037-b77135f64751 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255512623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres s.255512623 |
| Directory | /workspace/36.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/36.gpio_full_random.800548666 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 74765394 ps |
| CPU time | 1.11 seconds |
| Started | Jul 18 05:42:09 PM PDT 24 |
| Finished | Jul 18 05:42:22 PM PDT 24 |
| Peak memory | 197884 kb |
| Host | smart-f089d4df-52e1-41a9-bbb9-f5a8fcda02ce |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800548666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.800548666 |
| Directory | /workspace/36.gpio_full_random/latest |
| Test location | /workspace/coverage/default/36.gpio_intr_rand_pgm.931117655 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 170149992 ps |
| CPU time | 1.28 seconds |
| Started | Jul 18 05:42:07 PM PDT 24 |
| Finished | Jul 18 05:42:21 PM PDT 24 |
| Peak memory | 198280 kb |
| Host | smart-0d4686d0-be67-4578-8c78-191c2e9afb11 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931117655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.931117655 |
| Directory | /workspace/36.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3133372423 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 55234853 ps |
| CPU time | 1.23 seconds |
| Started | Jul 18 05:42:09 PM PDT 24 |
| Finished | Jul 18 05:42:22 PM PDT 24 |
| Peak memory | 196756 kb |
| Host | smart-bb99407c-a975-43a4-8045-3ac6ca9bf8c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133372423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3133372423 |
| Directory | /workspace/36.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/36.gpio_rand_intr_trigger.2156597561 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 132438824 ps |
| CPU time | 2.16 seconds |
| Started | Jul 18 05:42:06 PM PDT 24 |
| Finished | Jul 18 05:42:20 PM PDT 24 |
| Peak memory | 197428 kb |
| Host | smart-a460bdca-af9f-42e2-84ec-582d04d18a91 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156597561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger .2156597561 |
| Directory | /workspace/36.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/36.gpio_random_dout_din.1629692220 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 275555254 ps |
| CPU time | 1.28 seconds |
| Started | Jul 18 05:42:07 PM PDT 24 |
| Finished | Jul 18 05:42:20 PM PDT 24 |
| Peak memory | 197224 kb |
| Host | smart-c4985ec9-22d3-4e9f-adeb-a3fdd987de3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629692220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1629692220 |
| Directory | /workspace/36.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1999055290 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 45241718 ps |
| CPU time | 0.7 seconds |
| Started | Jul 18 05:42:07 PM PDT 24 |
| Finished | Jul 18 05:42:20 PM PDT 24 |
| Peak memory | 195592 kb |
| Host | smart-cc28571e-3137-4c35-86b1-5257f82d2607 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999055290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu p_pulldown.1999055290 |
| Directory | /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1656803793 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 84132286 ps |
| CPU time | 3.72 seconds |
| Started | Jul 18 05:42:08 PM PDT 24 |
| Finished | Jul 18 05:42:24 PM PDT 24 |
| Peak memory | 198068 kb |
| Host | smart-a161c91c-cbb2-4b61-9659-f5a2f4a5093a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656803793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra ndom_long_reg_writes_reg_reads.1656803793 |
| Directory | /workspace/36.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/36.gpio_smoke.2416675483 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 51628737 ps |
| CPU time | 0.9 seconds |
| Started | Jul 18 05:42:08 PM PDT 24 |
| Finished | Jul 18 05:42:21 PM PDT 24 |
| Peak memory | 196040 kb |
| Host | smart-56c2de28-c535-4215-8a87-07cddec1965d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416675483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2416675483 |
| Directory | /workspace/36.gpio_smoke/latest |
| Test location | /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.331223784 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 300163897 ps |
| CPU time | 1.26 seconds |
| Started | Jul 18 05:42:08 PM PDT 24 |
| Finished | Jul 18 05:42:22 PM PDT 24 |
| Peak memory | 195768 kb |
| Host | smart-28086070-303f-43ee-b621-90995bd5d968 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331223784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.331223784 |
| Directory | /workspace/36.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/36.gpio_stress_all.2939761138 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 49022421441 ps |
| CPU time | 182.56 seconds |
| Started | Jul 18 05:42:05 PM PDT 24 |
| Finished | Jul 18 05:45:18 PM PDT 24 |
| Peak memory | 198304 kb |
| Host | smart-cbe92aca-5743-467b-976d-dde186eb5d9a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939761138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. gpio_stress_all.2939761138 |
| Directory | /workspace/36.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/37.gpio_alert_test.3517537835 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 13207686 ps |
| CPU time | 0.57 seconds |
| Started | Jul 18 05:42:09 PM PDT 24 |
| Finished | Jul 18 05:42:22 PM PDT 24 |
| Peak memory | 194016 kb |
| Host | smart-41c3ec89-0a1b-433e-b79f-15f89823e66a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517537835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3517537835 |
| Directory | /workspace/37.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.646902878 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 129171600 ps |
| CPU time | 0.84 seconds |
| Started | Jul 18 05:42:05 PM PDT 24 |
| Finished | Jul 18 05:42:17 PM PDT 24 |
| Peak memory | 195380 kb |
| Host | smart-b0134192-108a-4384-9dde-2fd271534919 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=646902878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.646902878 |
| Directory | /workspace/37.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/37.gpio_filter_stress.3238658260 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1203147523 ps |
| CPU time | 15.64 seconds |
| Started | Jul 18 05:42:09 PM PDT 24 |
| Finished | Jul 18 05:42:37 PM PDT 24 |
| Peak memory | 196984 kb |
| Host | smart-446af54f-06e7-41eb-8a95-ea372f14bf4f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238658260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre ss.3238658260 |
| Directory | /workspace/37.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/37.gpio_full_random.2399772373 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 88138707 ps |
| CPU time | 0.8 seconds |
| Started | Jul 18 05:42:07 PM PDT 24 |
| Finished | Jul 18 05:42:19 PM PDT 24 |
| Peak memory | 196700 kb |
| Host | smart-b964dd6e-b263-4826-a3b1-3e0ab68b3fd9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399772373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2399772373 |
| Directory | /workspace/37.gpio_full_random/latest |
| Test location | /workspace/coverage/default/37.gpio_intr_rand_pgm.3711313637 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 348305577 ps |
| CPU time | 1.57 seconds |
| Started | Jul 18 05:42:05 PM PDT 24 |
| Finished | Jul 18 05:42:17 PM PDT 24 |
| Peak memory | 197360 kb |
| Host | smart-6cad932d-0069-43bf-9aee-42451ff27efd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711313637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3711313637 |
| Directory | /workspace/37.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.784934158 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 117719036 ps |
| CPU time | 2.59 seconds |
| Started | Jul 18 05:42:07 PM PDT 24 |
| Finished | Jul 18 05:42:21 PM PDT 24 |
| Peak memory | 198220 kb |
| Host | smart-61082208-cdb0-44cd-84d6-164bf4a85501 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784934158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 37.gpio_intr_with_filter_rand_intr_event.784934158 |
| Directory | /workspace/37.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/37.gpio_rand_intr_trigger.1363198436 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 140186709 ps |
| CPU time | 1.98 seconds |
| Started | Jul 18 05:42:05 PM PDT 24 |
| Finished | Jul 18 05:42:18 PM PDT 24 |
| Peak memory | 196600 kb |
| Host | smart-212e6174-db79-4b2d-abda-31e24ff74a35 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363198436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger .1363198436 |
| Directory | /workspace/37.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/37.gpio_random_dout_din.2948894418 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 27767378 ps |
| CPU time | 0.72 seconds |
| Started | Jul 18 05:42:07 PM PDT 24 |
| Finished | Jul 18 05:42:20 PM PDT 24 |
| Peak memory | 195548 kb |
| Host | smart-105521dc-ca85-48c1-abf6-52714f85b216 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2948894418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2948894418 |
| Directory | /workspace/37.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.253954965 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 45461093 ps |
| CPU time | 1.09 seconds |
| Started | Jul 18 05:42:06 PM PDT 24 |
| Finished | Jul 18 05:42:18 PM PDT 24 |
| Peak memory | 196732 kb |
| Host | smart-99cfe512-9a6f-473c-acab-e53ed5782bb0 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253954965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup _pulldown.253954965 |
| Directory | /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.811502860 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1098322691 ps |
| CPU time | 4.45 seconds |
| Started | Jul 18 05:42:08 PM PDT 24 |
| Finished | Jul 18 05:42:24 PM PDT 24 |
| Peak memory | 198228 kb |
| Host | smart-e07aa08d-d824-4ca5-901e-55304f77b295 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811502860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran dom_long_reg_writes_reg_reads.811502860 |
| Directory | /workspace/37.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/37.gpio_smoke.2482830026 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 174448230 ps |
| CPU time | 0.88 seconds |
| Started | Jul 18 05:42:07 PM PDT 24 |
| Finished | Jul 18 05:42:19 PM PDT 24 |
| Peak memory | 195456 kb |
| Host | smart-76249306-b9a1-43d2-bfe0-5c60fc127f14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2482830026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2482830026 |
| Directory | /workspace/37.gpio_smoke/latest |
| Test location | /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.141982117 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 37552941 ps |
| CPU time | 1.12 seconds |
| Started | Jul 18 05:42:09 PM PDT 24 |
| Finished | Jul 18 05:42:23 PM PDT 24 |
| Peak memory | 195952 kb |
| Host | smart-a6605ae9-3d15-4161-b61a-94ca95b2bdfb |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141982117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.141982117 |
| Directory | /workspace/37.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/37.gpio_stress_all.2685293072 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14001139872 ps |
| CPU time | 160.12 seconds |
| Started | Jul 18 05:42:06 PM PDT 24 |
| Finished | Jul 18 05:44:57 PM PDT 24 |
| Peak memory | 198332 kb |
| Host | smart-8f583997-d8c2-4586-a869-6e7cebdee944 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685293072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. gpio_stress_all.2685293072 |
| Directory | /workspace/37.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/38.gpio_alert_test.4192560736 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 89085710 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:42:10 PM PDT 24 |
| Finished | Jul 18 05:42:23 PM PDT 24 |
| Peak memory | 194204 kb |
| Host | smart-cf37066f-3680-488a-9309-ec90894a731a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192560736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.4192560736 |
| Directory | /workspace/38.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1044781057 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 20737514 ps |
| CPU time | 0.74 seconds |
| Started | Jul 18 05:42:10 PM PDT 24 |
| Finished | Jul 18 05:42:24 PM PDT 24 |
| Peak memory | 195536 kb |
| Host | smart-07fc39a5-31b0-4a05-be9d-4ba15b7904d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1044781057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1044781057 |
| Directory | /workspace/38.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/38.gpio_filter_stress.3819385950 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 977936882 ps |
| CPU time | 26.57 seconds |
| Started | Jul 18 05:42:06 PM PDT 24 |
| Finished | Jul 18 05:42:44 PM PDT 24 |
| Peak memory | 195760 kb |
| Host | smart-218cd941-fc9d-4aa9-b6e7-b433a433dea8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819385950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre ss.3819385950 |
| Directory | /workspace/38.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/38.gpio_full_random.2410832794 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 52964970 ps |
| CPU time | 0.86 seconds |
| Started | Jul 18 05:42:10 PM PDT 24 |
| Finished | Jul 18 05:42:23 PM PDT 24 |
| Peak memory | 196948 kb |
| Host | smart-d9fb2f8d-b555-4c27-80d8-03a44b4078ca |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410832794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2410832794 |
| Directory | /workspace/38.gpio_full_random/latest |
| Test location | /workspace/coverage/default/38.gpio_intr_rand_pgm.886591237 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 95030304 ps |
| CPU time | 1.35 seconds |
| Started | Jul 18 05:42:06 PM PDT 24 |
| Finished | Jul 18 05:42:19 PM PDT 24 |
| Peak memory | 198320 kb |
| Host | smart-7390162c-57e2-434f-9c5d-bfc9503d52b5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886591237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.886591237 |
| Directory | /workspace/38.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1407195762 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 45001930 ps |
| CPU time | 1.79 seconds |
| Started | Jul 18 05:42:11 PM PDT 24 |
| Finished | Jul 18 05:42:27 PM PDT 24 |
| Peak memory | 198260 kb |
| Host | smart-70427780-c710-4055-b9cb-380cf9c2a118 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407195762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1407195762 |
| Directory | /workspace/38.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/38.gpio_rand_intr_trigger.3050558770 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 161619328 ps |
| CPU time | 3.66 seconds |
| Started | Jul 18 05:42:08 PM PDT 24 |
| Finished | Jul 18 05:42:24 PM PDT 24 |
| Peak memory | 197260 kb |
| Host | smart-9453b7eb-2d01-40b8-9f43-f576f3d563ee |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050558770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger .3050558770 |
| Directory | /workspace/38.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/38.gpio_random_dout_din.1376108086 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 230576817 ps |
| CPU time | 0.72 seconds |
| Started | Jul 18 05:42:09 PM PDT 24 |
| Finished | Jul 18 05:42:23 PM PDT 24 |
| Peak memory | 196248 kb |
| Host | smart-93dc09fd-f39f-4465-ac80-52d47c4a5d40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1376108086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1376108086 |
| Directory | /workspace/38.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.11069897 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1070757273 ps |
| CPU time | 1.27 seconds |
| Started | Jul 18 05:42:06 PM PDT 24 |
| Finished | Jul 18 05:42:19 PM PDT 24 |
| Peak memory | 196020 kb |
| Host | smart-4922c6e8-c9c9-4a77-a373-00adcb5ddf38 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11069897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup_ pulldown.11069897 |
| Directory | /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2901312418 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 53443878 ps |
| CPU time | 2.16 seconds |
| Started | Jul 18 05:42:08 PM PDT 24 |
| Finished | Jul 18 05:42:21 PM PDT 24 |
| Peak memory | 198168 kb |
| Host | smart-ac48b2d3-2574-4610-852d-0a15d87bd06c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901312418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra ndom_long_reg_writes_reg_reads.2901312418 |
| Directory | /workspace/38.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/38.gpio_smoke.2823051209 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 55342588 ps |
| CPU time | 1.16 seconds |
| Started | Jul 18 05:42:08 PM PDT 24 |
| Finished | Jul 18 05:42:22 PM PDT 24 |
| Peak memory | 196780 kb |
| Host | smart-52f222c2-38e3-4720-a3fc-13b658ce91a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2823051209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2823051209 |
| Directory | /workspace/38.gpio_smoke/latest |
| Test location | /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2826043041 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 304530151 ps |
| CPU time | 1.06 seconds |
| Started | Jul 18 05:42:10 PM PDT 24 |
| Finished | Jul 18 05:42:23 PM PDT 24 |
| Peak memory | 195956 kb |
| Host | smart-76831bd1-6390-40cd-930e-4fde9afbe3f6 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826043041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2826043041 |
| Directory | /workspace/38.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/38.gpio_stress_all.766098277 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 43506350871 ps |
| CPU time | 90.91 seconds |
| Started | Jul 18 05:42:08 PM PDT 24 |
| Finished | Jul 18 05:43:51 PM PDT 24 |
| Peak memory | 198332 kb |
| Host | smart-5ab84e99-444f-48cf-8026-2ee6feea004a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766098277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g pio_stress_all.766098277 |
| Directory | /workspace/38.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/39.gpio_alert_test.1667730074 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 14124243 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:42:23 PM PDT 24 |
| Finished | Jul 18 05:42:38 PM PDT 24 |
| Peak memory | 194296 kb |
| Host | smart-956ac903-1486-4db3-9eb6-fcaf1dbbc313 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667730074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1667730074 |
| Directory | /workspace/39.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.444386616 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 50163059 ps |
| CPU time | 0.84 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:40 PM PDT 24 |
| Peak memory | 195384 kb |
| Host | smart-2a57078c-540f-4e74-ad5b-98a8a9c9dc10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=444386616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.444386616 |
| Directory | /workspace/39.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/39.gpio_filter_stress.2285673200 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1229633107 ps |
| CPU time | 15.67 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:55 PM PDT 24 |
| Peak memory | 197188 kb |
| Host | smart-10bef22d-8cd2-4266-9eac-5dad45bda37c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285673200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre ss.2285673200 |
| Directory | /workspace/39.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/39.gpio_full_random.611782534 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 135754383 ps |
| CPU time | 0.92 seconds |
| Started | Jul 18 05:42:24 PM PDT 24 |
| Finished | Jul 18 05:42:38 PM PDT 24 |
| Peak memory | 197860 kb |
| Host | smart-8fea1b18-ad63-40bd-9807-667ada38a086 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611782534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.611782534 |
| Directory | /workspace/39.gpio_full_random/latest |
| Test location | /workspace/coverage/default/39.gpio_intr_rand_pgm.3075525790 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 24056661 ps |
| CPU time | 0.93 seconds |
| Started | Jul 18 05:42:20 PM PDT 24 |
| Finished | Jul 18 05:42:35 PM PDT 24 |
| Peak memory | 196384 kb |
| Host | smart-e8465636-5b7e-435a-ab6f-1691ff7bc666 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075525790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3075525790 |
| Directory | /workspace/39.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2756942850 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 112503105 ps |
| CPU time | 1.48 seconds |
| Started | Jul 18 05:42:21 PM PDT 24 |
| Finished | Jul 18 05:42:36 PM PDT 24 |
| Peak memory | 198300 kb |
| Host | smart-28eb9b12-f744-43e1-8722-0f78fbac687e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756942850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2756942850 |
| Directory | /workspace/39.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/39.gpio_rand_intr_trigger.824833428 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 962650559 ps |
| CPU time | 3.65 seconds |
| Started | Jul 18 05:42:23 PM PDT 24 |
| Finished | Jul 18 05:42:39 PM PDT 24 |
| Peak memory | 196048 kb |
| Host | smart-a2647ec6-be2f-48f2-9529-4cff37c424dc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824833428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger. 824833428 |
| Directory | /workspace/39.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/39.gpio_random_dout_din.1296098966 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 30780730 ps |
| CPU time | 0.84 seconds |
| Started | Jul 18 05:42:24 PM PDT 24 |
| Finished | Jul 18 05:42:39 PM PDT 24 |
| Peak memory | 196340 kb |
| Host | smart-728abec0-dca6-4f3b-bc47-44ee90877296 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296098966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1296098966 |
| Directory | /workspace/39.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.54071209 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 74076476 ps |
| CPU time | 1.13 seconds |
| Started | Jul 18 05:42:21 PM PDT 24 |
| Finished | Jul 18 05:42:35 PM PDT 24 |
| Peak memory | 196108 kb |
| Host | smart-cad4fbf2-fd41-44a5-9823-838996a498b0 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54071209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup_ pulldown.54071209 |
| Directory | /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2783837177 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 295788006 ps |
| CPU time | 2.83 seconds |
| Started | Jul 18 05:42:22 PM PDT 24 |
| Finished | Jul 18 05:42:38 PM PDT 24 |
| Peak memory | 198176 kb |
| Host | smart-76d6ba7f-063c-485b-bcd8-545bdba5414a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783837177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra ndom_long_reg_writes_reg_reads.2783837177 |
| Directory | /workspace/39.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/39.gpio_smoke.1923530481 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 211078530 ps |
| CPU time | 0.99 seconds |
| Started | Jul 18 05:42:06 PM PDT 24 |
| Finished | Jul 18 05:42:18 PM PDT 24 |
| Peak memory | 195852 kb |
| Host | smart-5cbba604-cddf-4501-b94d-cd270e54481b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1923530481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1923530481 |
| Directory | /workspace/39.gpio_smoke/latest |
| Test location | /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3390352358 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 65090136 ps |
| CPU time | 1.12 seconds |
| Started | Jul 18 05:42:07 PM PDT 24 |
| Finished | Jul 18 05:42:19 PM PDT 24 |
| Peak memory | 195828 kb |
| Host | smart-82423d6e-1395-413f-bd9a-75688eead059 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390352358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3390352358 |
| Directory | /workspace/39.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/39.gpio_stress_all.655892995 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 22629265107 ps |
| CPU time | 118.06 seconds |
| Started | Jul 18 05:42:23 PM PDT 24 |
| Finished | Jul 18 05:44:35 PM PDT 24 |
| Peak memory | 198236 kb |
| Host | smart-92de3936-7042-40ab-a0de-eba43ab7c8b8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655892995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g pio_stress_all.655892995 |
| Directory | /workspace/39.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/4.gpio_alert_test.1378097627 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 12230209 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:40:45 PM PDT 24 |
| Finished | Jul 18 05:40:49 PM PDT 24 |
| Peak memory | 194188 kb |
| Host | smart-37ad3dbf-a26d-4bda-86a0-60f081e6a727 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378097627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1378097627 |
| Directory | /workspace/4.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2437277764 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 106488232 ps |
| CPU time | 0.96 seconds |
| Started | Jul 18 05:40:46 PM PDT 24 |
| Finished | Jul 18 05:40:50 PM PDT 24 |
| Peak memory | 196628 kb |
| Host | smart-3d5821e3-8995-482b-8c57-63ed513b08f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437277764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2437277764 |
| Directory | /workspace/4.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/4.gpio_filter_stress.2556260377 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 296460052 ps |
| CPU time | 15.21 seconds |
| Started | Jul 18 05:40:53 PM PDT 24 |
| Finished | Jul 18 05:41:15 PM PDT 24 |
| Peak memory | 197360 kb |
| Host | smart-b8c65d76-4f80-40f8-be57-379813a8e4fb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556260377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres s.2556260377 |
| Directory | /workspace/4.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/4.gpio_full_random.2117577283 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 107473744 ps |
| CPU time | 0.73 seconds |
| Started | Jul 18 05:40:53 PM PDT 24 |
| Finished | Jul 18 05:41:00 PM PDT 24 |
| Peak memory | 194988 kb |
| Host | smart-fe00c723-a23a-4700-bade-1cc2841c8e01 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117577283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2117577283 |
| Directory | /workspace/4.gpio_full_random/latest |
| Test location | /workspace/coverage/default/4.gpio_intr_rand_pgm.3127789441 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 38368172 ps |
| CPU time | 1.14 seconds |
| Started | Jul 18 05:40:53 PM PDT 24 |
| Finished | Jul 18 05:41:00 PM PDT 24 |
| Peak memory | 197044 kb |
| Host | smart-8634f853-7126-4fd6-a3af-8f5816fb5abb |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127789441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3127789441 |
| Directory | /workspace/4.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.640947368 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 873108478 ps |
| CPU time | 3.04 seconds |
| Started | Jul 18 05:40:46 PM PDT 24 |
| Finished | Jul 18 05:40:54 PM PDT 24 |
| Peak memory | 198216 kb |
| Host | smart-97cfe7d9-8e8b-4024-9711-5402928a3977 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640947368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 4.gpio_intr_with_filter_rand_intr_event.640947368 |
| Directory | /workspace/4.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/4.gpio_rand_intr_trigger.1351811630 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 127503275 ps |
| CPU time | 2.99 seconds |
| Started | Jul 18 05:40:51 PM PDT 24 |
| Finished | Jul 18 05:40:59 PM PDT 24 |
| Peak memory | 198292 kb |
| Host | smart-c22ababf-c73b-4010-9b15-92f117d4adf3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351811630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger. 1351811630 |
| Directory | /workspace/4.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/4.gpio_random_dout_din.3784602753 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 123179407 ps |
| CPU time | 0.84 seconds |
| Started | Jul 18 05:40:52 PM PDT 24 |
| Finished | Jul 18 05:40:59 PM PDT 24 |
| Peak memory | 196624 kb |
| Host | smart-10946a4c-7c54-432e-baaa-e2a8c6fc180a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3784602753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3784602753 |
| Directory | /workspace/4.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1892611125 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 35826750 ps |
| CPU time | 1.01 seconds |
| Started | Jul 18 05:40:46 PM PDT 24 |
| Finished | Jul 18 05:40:52 PM PDT 24 |
| Peak memory | 196180 kb |
| Host | smart-df6ee87c-6784-4113-b905-88e2e2bc4020 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892611125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup _pulldown.1892611125 |
| Directory | /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2318324476 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 1008092438 ps |
| CPU time | 2.76 seconds |
| Started | Jul 18 05:40:46 PM PDT 24 |
| Finished | Jul 18 05:40:52 PM PDT 24 |
| Peak memory | 198276 kb |
| Host | smart-f4fc483d-e3d7-42b9-818a-f96bbb4123d0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318324476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran dom_long_reg_writes_reg_reads.2318324476 |
| Directory | /workspace/4.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/4.gpio_sec_cm.1417015016 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 684705060 ps |
| CPU time | 0.91 seconds |
| Started | Jul 18 05:40:53 PM PDT 24 |
| Finished | Jul 18 05:41:00 PM PDT 24 |
| Peak memory | 214268 kb |
| Host | smart-d7ad20e9-add1-4c6b-b594-0becbf9e6ad2 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417015016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1417015016 |
| Directory | /workspace/4.gpio_sec_cm/latest |
| Test location | /workspace/coverage/default/4.gpio_smoke.3775302550 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 83526737 ps |
| CPU time | 1.56 seconds |
| Started | Jul 18 05:40:44 PM PDT 24 |
| Finished | Jul 18 05:40:49 PM PDT 24 |
| Peak memory | 198140 kb |
| Host | smart-1f8d8928-dcdd-4558-80e2-f62ac8df391e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3775302550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3775302550 |
| Directory | /workspace/4.gpio_smoke/latest |
| Test location | /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.738755552 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 47324738 ps |
| CPU time | 1.35 seconds |
| Started | Jul 18 05:40:50 PM PDT 24 |
| Finished | Jul 18 05:40:57 PM PDT 24 |
| Peak memory | 196988 kb |
| Host | smart-7bc3f91b-6c96-4792-a941-d74f075fba5b |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738755552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.738755552 |
| Directory | /workspace/4.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/4.gpio_stress_all.2099154738 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 52481886083 ps |
| CPU time | 138.05 seconds |
| Started | Jul 18 05:40:52 PM PDT 24 |
| Finished | Jul 18 05:43:16 PM PDT 24 |
| Peak memory | 198364 kb |
| Host | smart-d139b0d1-f5ac-4988-b770-0237bb887f3b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099154738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g pio_stress_all.2099154738 |
| Directory | /workspace/4.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.2992809250 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 291119484918 ps |
| CPU time | 1508.29 seconds |
| Started | Jul 18 05:40:47 PM PDT 24 |
| Finished | Jul 18 06:06:00 PM PDT 24 |
| Peak memory | 198424 kb |
| Host | smart-a67a4468-a0fa-403a-9af1-1e58941be4ae |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2992809250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.2992809250 |
| Directory | /workspace/4.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.gpio_alert_test.539860071 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 44867690 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:42:23 PM PDT 24 |
| Finished | Jul 18 05:42:37 PM PDT 24 |
| Peak memory | 194884 kb |
| Host | smart-c0cc3adb-a124-4107-864b-50de80e98968 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539860071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.539860071 |
| Directory | /workspace/40.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.42099572 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 16663506 ps |
| CPU time | 0.66 seconds |
| Started | Jul 18 05:42:21 PM PDT 24 |
| Finished | Jul 18 05:42:35 PM PDT 24 |
| Peak memory | 194084 kb |
| Host | smart-24a1b358-a89a-45cf-afc6-b26d3e82fe69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42099572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.42099572 |
| Directory | /workspace/40.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/40.gpio_filter_stress.631318244 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 938869995 ps |
| CPU time | 8.54 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:48 PM PDT 24 |
| Peak memory | 198176 kb |
| Host | smart-fe506ce7-3398-4c13-839e-e4db5aa60709 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631318244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres s.631318244 |
| Directory | /workspace/40.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/40.gpio_full_random.772229977 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 100807152 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:42:20 PM PDT 24 |
| Finished | Jul 18 05:42:34 PM PDT 24 |
| Peak memory | 196972 kb |
| Host | smart-f185533d-be52-49df-a50f-5da842337468 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772229977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.772229977 |
| Directory | /workspace/40.gpio_full_random/latest |
| Test location | /workspace/coverage/default/40.gpio_intr_rand_pgm.3515634799 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 188680250 ps |
| CPU time | 1 seconds |
| Started | Jul 18 05:42:22 PM PDT 24 |
| Finished | Jul 18 05:42:36 PM PDT 24 |
| Peak memory | 196008 kb |
| Host | smart-818bbc11-63f3-4166-8b53-27ddb7a6e3fc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515634799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3515634799 |
| Directory | /workspace/40.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2007823281 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 210348109 ps |
| CPU time | 2.29 seconds |
| Started | Jul 18 05:42:23 PM PDT 24 |
| Finished | Jul 18 05:42:38 PM PDT 24 |
| Peak memory | 198284 kb |
| Host | smart-5197eb9b-1134-4fae-b3dd-ee8a1c506fdf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007823281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2007823281 |
| Directory | /workspace/40.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/40.gpio_rand_intr_trigger.1595776915 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 222866265 ps |
| CPU time | 2.83 seconds |
| Started | Jul 18 05:42:18 PM PDT 24 |
| Finished | Jul 18 05:42:35 PM PDT 24 |
| Peak memory | 197072 kb |
| Host | smart-95636b9d-2e53-4e91-b04e-2730d0019414 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595776915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger .1595776915 |
| Directory | /workspace/40.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/40.gpio_random_dout_din.2653761361 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 97262031 ps |
| CPU time | 1.17 seconds |
| Started | Jul 18 05:42:21 PM PDT 24 |
| Finished | Jul 18 05:42:36 PM PDT 24 |
| Peak memory | 196928 kb |
| Host | smart-f428b8f7-bbe8-46f8-8097-e9c9db2af70c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2653761361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2653761361 |
| Directory | /workspace/40.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2159113836 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 224334652 ps |
| CPU time | 1.38 seconds |
| Started | Jul 18 05:42:22 PM PDT 24 |
| Finished | Jul 18 05:42:37 PM PDT 24 |
| Peak memory | 197220 kb |
| Host | smart-a52f39f4-29f1-4425-ae38-908d7a4e40d5 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159113836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu p_pulldown.2159113836 |
| Directory | /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2127639820 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 177333177 ps |
| CPU time | 2.42 seconds |
| Started | Jul 18 05:42:22 PM PDT 24 |
| Finished | Jul 18 05:42:38 PM PDT 24 |
| Peak memory | 197676 kb |
| Host | smart-9c92708c-4643-4580-8a51-c69439039b78 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127639820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra ndom_long_reg_writes_reg_reads.2127639820 |
| Directory | /workspace/40.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/40.gpio_smoke.284236759 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 102164404 ps |
| CPU time | 1.07 seconds |
| Started | Jul 18 05:42:23 PM PDT 24 |
| Finished | Jul 18 05:42:38 PM PDT 24 |
| Peak memory | 195924 kb |
| Host | smart-4e48fb6f-d942-4a99-b6ad-133748ad66f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=284236759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.284236759 |
| Directory | /workspace/40.gpio_smoke/latest |
| Test location | /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.272365474 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 44551508 ps |
| CPU time | 1.17 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:41 PM PDT 24 |
| Peak memory | 195764 kb |
| Host | smart-1399c9ef-07cb-4717-bda7-0cb6b4fbbf40 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272365474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.272365474 |
| Directory | /workspace/40.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/40.gpio_stress_all.1044445563 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 128228463641 ps |
| CPU time | 187.85 seconds |
| Started | Jul 18 05:42:23 PM PDT 24 |
| Finished | Jul 18 05:45:44 PM PDT 24 |
| Peak memory | 198336 kb |
| Host | smart-a9307abb-3b2a-4ac6-8fc1-1fa791e8c9cd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044445563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. gpio_stress_all.1044445563 |
| Directory | /workspace/40.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.144115377 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 237319981092 ps |
| CPU time | 1448.15 seconds |
| Started | Jul 18 05:42:22 PM PDT 24 |
| Finished | Jul 18 06:06:44 PM PDT 24 |
| Peak memory | 198472 kb |
| Host | smart-8158cb2f-2fe2-4bd9-8790-efa5e7bfcfc9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =144115377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.144115377 |
| Directory | /workspace/40.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.gpio_alert_test.2203910833 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 13927920 ps |
| CPU time | 0.65 seconds |
| Started | Jul 18 05:42:21 PM PDT 24 |
| Finished | Jul 18 05:42:35 PM PDT 24 |
| Peak memory | 194356 kb |
| Host | smart-e73cc7be-4aa1-4941-bd28-901fab6429f7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203910833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2203910833 |
| Directory | /workspace/41.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3152158768 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 34760225 ps |
| CPU time | 0.89 seconds |
| Started | Jul 18 05:42:26 PM PDT 24 |
| Finished | Jul 18 05:42:41 PM PDT 24 |
| Peak memory | 195464 kb |
| Host | smart-1ac930db-a48e-4034-810e-7d66a12889fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152158768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3152158768 |
| Directory | /workspace/41.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/41.gpio_filter_stress.3650163662 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 155375982 ps |
| CPU time | 7.95 seconds |
| Started | Jul 18 05:42:24 PM PDT 24 |
| Finished | Jul 18 05:42:46 PM PDT 24 |
| Peak memory | 197116 kb |
| Host | smart-087ee91d-2ccf-450e-8334-641542486e2b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650163662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre ss.3650163662 |
| Directory | /workspace/41.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/41.gpio_full_random.1418416406 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 25630248 ps |
| CPU time | 0.72 seconds |
| Started | Jul 18 05:42:23 PM PDT 24 |
| Finished | Jul 18 05:42:37 PM PDT 24 |
| Peak memory | 195464 kb |
| Host | smart-da062a3a-0ad3-4d7e-95d6-645e359c973e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418416406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1418416406 |
| Directory | /workspace/41.gpio_full_random/latest |
| Test location | /workspace/coverage/default/41.gpio_intr_rand_pgm.2796966859 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 347600831 ps |
| CPU time | 1.24 seconds |
| Started | Jul 18 05:42:19 PM PDT 24 |
| Finished | Jul 18 05:42:34 PM PDT 24 |
| Peak memory | 197092 kb |
| Host | smart-36404213-cd17-4b82-bf9a-8f6caf20d205 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796966859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2796966859 |
| Directory | /workspace/41.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.4074425720 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 48425042 ps |
| CPU time | 1.97 seconds |
| Started | Jul 18 05:42:22 PM PDT 24 |
| Finished | Jul 18 05:42:37 PM PDT 24 |
| Peak memory | 198216 kb |
| Host | smart-21295146-34e8-4f92-8200-8a8d91e649ad |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074425720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.gpio_intr_with_filter_rand_intr_event.4074425720 |
| Directory | /workspace/41.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/41.gpio_rand_intr_trigger.3662874538 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 360806683 ps |
| CPU time | 1.3 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:40 PM PDT 24 |
| Peak memory | 196756 kb |
| Host | smart-cf853a32-ea4b-48c9-8f6f-2a9724f7a876 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662874538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger .3662874538 |
| Directory | /workspace/41.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/41.gpio_random_dout_din.2401769522 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 126048034 ps |
| CPU time | 0.74 seconds |
| Started | Jul 18 05:42:23 PM PDT 24 |
| Finished | Jul 18 05:42:38 PM PDT 24 |
| Peak memory | 195136 kb |
| Host | smart-6ca428c3-21cd-4c57-958a-60f1ae5e3329 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2401769522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2401769522 |
| Directory | /workspace/41.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.4274962989 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 28181107 ps |
| CPU time | 1.02 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:40 PM PDT 24 |
| Peak memory | 196192 kb |
| Host | smart-3e2fe137-427e-4a30-bb34-77134af0685f |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274962989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu p_pulldown.4274962989 |
| Directory | /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1451717545 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3607370507 ps |
| CPU time | 4.75 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:44 PM PDT 24 |
| Peak memory | 198220 kb |
| Host | smart-25d2acd2-bdc3-44ab-841b-348addd161a1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451717545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra ndom_long_reg_writes_reg_reads.1451717545 |
| Directory | /workspace/41.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/41.gpio_smoke.299297373 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 195522966 ps |
| CPU time | 1.26 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:40 PM PDT 24 |
| Peak memory | 196760 kb |
| Host | smart-685b3b51-9437-42be-82ab-19013e2f9def |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=299297373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.299297373 |
| Directory | /workspace/41.gpio_smoke/latest |
| Test location | /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.702067369 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 913379038 ps |
| CPU time | 1.05 seconds |
| Started | Jul 18 05:42:21 PM PDT 24 |
| Finished | Jul 18 05:42:35 PM PDT 24 |
| Peak memory | 196012 kb |
| Host | smart-6e857640-f9c2-4a09-88aa-567c9af6c641 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702067369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.702067369 |
| Directory | /workspace/41.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/41.gpio_stress_all.180092641 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 22172087448 ps |
| CPU time | 68.84 seconds |
| Started | Jul 18 05:42:22 PM PDT 24 |
| Finished | Jul 18 05:43:44 PM PDT 24 |
| Peak memory | 197872 kb |
| Host | smart-df8d3521-2859-44d1-b6ad-3a06500ad89b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180092641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g pio_stress_all.180092641 |
| Directory | /workspace/41.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/42.gpio_alert_test.2679236589 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 55945249 ps |
| CPU time | 0.57 seconds |
| Started | Jul 18 05:42:23 PM PDT 24 |
| Finished | Jul 18 05:42:37 PM PDT 24 |
| Peak memory | 194436 kb |
| Host | smart-f9664bf9-4318-4e77-96cc-fdcb574a937e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679236589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2679236589 |
| Directory | /workspace/42.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2973501017 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 23028315 ps |
| CPU time | 0.78 seconds |
| Started | Jul 18 05:42:24 PM PDT 24 |
| Finished | Jul 18 05:42:39 PM PDT 24 |
| Peak memory | 195488 kb |
| Host | smart-ac422726-24df-4ef3-9c86-e83a6476e3e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2973501017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2973501017 |
| Directory | /workspace/42.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/42.gpio_filter_stress.3971191074 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 147393435 ps |
| CPU time | 3.93 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:42 PM PDT 24 |
| Peak memory | 196804 kb |
| Host | smart-5c8e1b26-582b-46c1-8a52-d5c11a907531 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971191074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre ss.3971191074 |
| Directory | /workspace/42.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/42.gpio_intr_rand_pgm.1680354790 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 66803827 ps |
| CPU time | 1.01 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:40 PM PDT 24 |
| Peak memory | 196376 kb |
| Host | smart-30f24a27-dc4f-405c-994f-11e7f3927d00 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680354790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1680354790 |
| Directory | /workspace/42.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1953034855 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 113377716 ps |
| CPU time | 1.03 seconds |
| Started | Jul 18 05:42:27 PM PDT 24 |
| Finished | Jul 18 05:42:43 PM PDT 24 |
| Peak memory | 196152 kb |
| Host | smart-001c405d-73f8-4fa3-9dc8-e08bc3c12856 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953034855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1953034855 |
| Directory | /workspace/42.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/42.gpio_rand_intr_trigger.1945963739 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 105589739 ps |
| CPU time | 1.35 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:40 PM PDT 24 |
| Peak memory | 196012 kb |
| Host | smart-584cd1fb-b16f-4fc8-8038-0ddfcfbfe5fd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945963739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger .1945963739 |
| Directory | /workspace/42.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/42.gpio_random_dout_din.755450450 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 236898522 ps |
| CPU time | 0.96 seconds |
| Started | Jul 18 05:42:24 PM PDT 24 |
| Finished | Jul 18 05:42:39 PM PDT 24 |
| Peak memory | 196788 kb |
| Host | smart-cbe5af7a-7805-4b9e-b46e-8e711f3fae7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755450450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.755450450 |
| Directory | /workspace/42.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2318033685 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 147590458 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:42:22 PM PDT 24 |
| Finished | Jul 18 05:42:36 PM PDT 24 |
| Peak memory | 195764 kb |
| Host | smart-1667ff1c-00e7-4c55-acf9-f338493fa4ea |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318033685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu p_pulldown.2318033685 |
| Directory | /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2070569711 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 238888619 ps |
| CPU time | 5.43 seconds |
| Started | Jul 18 05:42:26 PM PDT 24 |
| Finished | Jul 18 05:42:47 PM PDT 24 |
| Peak memory | 198208 kb |
| Host | smart-b1109393-b7e3-4214-b2bc-eeb388c26102 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070569711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra ndom_long_reg_writes_reg_reads.2070569711 |
| Directory | /workspace/42.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/42.gpio_smoke.3450060173 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 337924799 ps |
| CPU time | 1.4 seconds |
| Started | Jul 18 05:42:22 PM PDT 24 |
| Finished | Jul 18 05:42:36 PM PDT 24 |
| Peak memory | 195788 kb |
| Host | smart-24772fa7-3a03-4015-af3e-3339cc59afa7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450060173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3450060173 |
| Directory | /workspace/42.gpio_smoke/latest |
| Test location | /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3867674430 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 57625931 ps |
| CPU time | 1.02 seconds |
| Started | Jul 18 05:42:20 PM PDT 24 |
| Finished | Jul 18 05:42:34 PM PDT 24 |
| Peak memory | 195752 kb |
| Host | smart-2365e788-a629-40d4-b5cb-bc8eda747d1d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867674430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3867674430 |
| Directory | /workspace/42.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/42.gpio_stress_all.2696929241 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 17544619433 ps |
| CPU time | 122.07 seconds |
| Started | Jul 18 05:42:26 PM PDT 24 |
| Finished | Jul 18 05:44:44 PM PDT 24 |
| Peak memory | 198192 kb |
| Host | smart-b97feb88-a735-4498-ba84-7a61a10c0749 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696929241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. gpio_stress_all.2696929241 |
| Directory | /workspace/42.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/43.gpio_alert_test.4228912247 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 14159192 ps |
| CPU time | 0.6 seconds |
| Started | Jul 18 05:42:32 PM PDT 24 |
| Finished | Jul 18 05:42:50 PM PDT 24 |
| Peak memory | 195084 kb |
| Host | smart-2c1a8b8a-a712-4bad-a2a4-f285f6ffd581 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228912247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.4228912247 |
| Directory | /workspace/43.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3900333841 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 105972944 ps |
| CPU time | 0.89 seconds |
| Started | Jul 18 05:42:26 PM PDT 24 |
| Finished | Jul 18 05:42:42 PM PDT 24 |
| Peak memory | 196420 kb |
| Host | smart-d97003fe-5e6f-4f67-9335-8da332dc3921 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3900333841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3900333841 |
| Directory | /workspace/43.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/43.gpio_filter_stress.3902936212 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 601287877 ps |
| CPU time | 5.89 seconds |
| Started | Jul 18 05:42:29 PM PDT 24 |
| Finished | Jul 18 05:42:51 PM PDT 24 |
| Peak memory | 197296 kb |
| Host | smart-7168f63b-9752-4d0a-8453-6a9a9a0d81d9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902936212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre ss.3902936212 |
| Directory | /workspace/43.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/43.gpio_full_random.3216908824 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 48844151 ps |
| CPU time | 0.76 seconds |
| Started | Jul 18 05:42:32 PM PDT 24 |
| Finished | Jul 18 05:42:50 PM PDT 24 |
| Peak memory | 196056 kb |
| Host | smart-8cd8433d-cde2-4f34-b893-0dd12fde3e69 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216908824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3216908824 |
| Directory | /workspace/43.gpio_full_random/latest |
| Test location | /workspace/coverage/default/43.gpio_intr_rand_pgm.3860567396 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 110289286 ps |
| CPU time | 1.15 seconds |
| Started | Jul 18 05:42:28 PM PDT 24 |
| Finished | Jul 18 05:42:45 PM PDT 24 |
| Peak memory | 197060 kb |
| Host | smart-53fe1258-75ab-4023-9117-d5676db69085 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860567396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3860567396 |
| Directory | /workspace/43.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.4160734240 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 219091698 ps |
| CPU time | 2.26 seconds |
| Started | Jul 18 05:42:26 PM PDT 24 |
| Finished | Jul 18 05:42:44 PM PDT 24 |
| Peak memory | 198200 kb |
| Host | smart-e785ee0c-cf13-40a3-8398-b37031af8326 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160734240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.gpio_intr_with_filter_rand_intr_event.4160734240 |
| Directory | /workspace/43.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/43.gpio_rand_intr_trigger.2697040937 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 172162139 ps |
| CPU time | 2.49 seconds |
| Started | Jul 18 05:42:29 PM PDT 24 |
| Finished | Jul 18 05:42:46 PM PDT 24 |
| Peak memory | 197548 kb |
| Host | smart-726a4207-477e-44d8-be78-12cfe6abc3e0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697040937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger .2697040937 |
| Directory | /workspace/43.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/43.gpio_random_dout_din.308368093 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27680968 ps |
| CPU time | 0.84 seconds |
| Started | Jul 18 05:42:26 PM PDT 24 |
| Finished | Jul 18 05:42:42 PM PDT 24 |
| Peak memory | 195692 kb |
| Host | smart-dfeff76f-e983-4142-8062-0ee12e167257 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=308368093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.308368093 |
| Directory | /workspace/43.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1060828670 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 51286341 ps |
| CPU time | 1.08 seconds |
| Started | Jul 18 05:42:28 PM PDT 24 |
| Finished | Jul 18 05:42:45 PM PDT 24 |
| Peak memory | 196096 kb |
| Host | smart-03980274-1e15-4928-a3d4-6d1e52e8b866 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060828670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu p_pulldown.1060828670 |
| Directory | /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3278649005 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 303752314 ps |
| CPU time | 3.9 seconds |
| Started | Jul 18 05:42:33 PM PDT 24 |
| Finished | Jul 18 05:42:53 PM PDT 24 |
| Peak memory | 198160 kb |
| Host | smart-61c4b9c4-832c-45af-af3e-e5acef93baf1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278649005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra ndom_long_reg_writes_reg_reads.3278649005 |
| Directory | /workspace/43.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/43.gpio_smoke.1539375131 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 42641048 ps |
| CPU time | 1.18 seconds |
| Started | Jul 18 05:42:28 PM PDT 24 |
| Finished | Jul 18 05:42:44 PM PDT 24 |
| Peak memory | 196508 kb |
| Host | smart-189afa6f-0877-484c-bbdb-b054e8b8acb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539375131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1539375131 |
| Directory | /workspace/43.gpio_smoke/latest |
| Test location | /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1574188116 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 175563614 ps |
| CPU time | 1.03 seconds |
| Started | Jul 18 05:42:28 PM PDT 24 |
| Finished | Jul 18 05:42:45 PM PDT 24 |
| Peak memory | 196476 kb |
| Host | smart-43f8b734-8854-4e48-982a-beff1424dc68 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574188116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1574188116 |
| Directory | /workspace/43.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/43.gpio_stress_all.788309602 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1137188495 ps |
| CPU time | 27.45 seconds |
| Started | Jul 18 05:42:32 PM PDT 24 |
| Finished | Jul 18 05:43:17 PM PDT 24 |
| Peak memory | 198224 kb |
| Host | smart-b296f213-0840-485b-9136-7fa9eea16e3e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788309602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g pio_stress_all.788309602 |
| Directory | /workspace/43.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.3347153524 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 38260545995 ps |
| CPU time | 919.37 seconds |
| Started | Jul 18 05:42:33 PM PDT 24 |
| Finished | Jul 18 05:58:09 PM PDT 24 |
| Peak memory | 198448 kb |
| Host | smart-4ea03dd7-9039-4ab4-8854-3031980ce4a8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3347153524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.3347153524 |
| Directory | /workspace/43.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.gpio_alert_test.568514460 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 117539538 ps |
| CPU time | 0.58 seconds |
| Started | Jul 18 05:42:28 PM PDT 24 |
| Finished | Jul 18 05:42:43 PM PDT 24 |
| Peak memory | 192920 kb |
| Host | smart-04402dca-8dac-402c-8226-80bc214089c4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568514460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.568514460 |
| Directory | /workspace/44.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2532617244 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 137283231 ps |
| CPU time | 0.91 seconds |
| Started | Jul 18 05:42:24 PM PDT 24 |
| Finished | Jul 18 05:42:39 PM PDT 24 |
| Peak memory | 196160 kb |
| Host | smart-95b2af4d-c7bb-4cb2-b1bd-0f743ea4c321 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532617244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2532617244 |
| Directory | /workspace/44.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/44.gpio_filter_stress.3454438623 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 335939486 ps |
| CPU time | 11.49 seconds |
| Started | Jul 18 05:42:22 PM PDT 24 |
| Finished | Jul 18 05:42:46 PM PDT 24 |
| Peak memory | 195796 kb |
| Host | smart-10963a90-d372-4c79-926a-268a0d4c7e99 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454438623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre ss.3454438623 |
| Directory | /workspace/44.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/44.gpio_full_random.1296839371 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 102173938 ps |
| CPU time | 1.08 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:41 PM PDT 24 |
| Peak memory | 198112 kb |
| Host | smart-99e9f6ef-df20-43cc-82c0-7ce190c89ee9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296839371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1296839371 |
| Directory | /workspace/44.gpio_full_random/latest |
| Test location | /workspace/coverage/default/44.gpio_intr_rand_pgm.1382998026 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 72804186 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:40 PM PDT 24 |
| Peak memory | 196556 kb |
| Host | smart-60f26031-f393-4203-ad45-dd94fa2b5328 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382998026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1382998026 |
| Directory | /workspace/44.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2757211005 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 163598066 ps |
| CPU time | 3.4 seconds |
| Started | Jul 18 05:42:26 PM PDT 24 |
| Finished | Jul 18 05:42:44 PM PDT 24 |
| Peak memory | 198304 kb |
| Host | smart-5f0cb477-e5f2-4c5f-8ab1-5f35117f5101 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757211005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2757211005 |
| Directory | /workspace/44.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/44.gpio_rand_intr_trigger.3259878121 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 519203992 ps |
| CPU time | 2.87 seconds |
| Started | Jul 18 05:42:24 PM PDT 24 |
| Finished | Jul 18 05:42:41 PM PDT 24 |
| Peak memory | 197492 kb |
| Host | smart-72156af2-42fa-45f8-bcdc-ef5d95892c31 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259878121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger .3259878121 |
| Directory | /workspace/44.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/44.gpio_random_dout_din.2801509434 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 28955274 ps |
| CPU time | 0.74 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:40 PM PDT 24 |
| Peak memory | 195452 kb |
| Host | smart-efcf02f9-dd43-4228-b518-dc8e3c15824a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2801509434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2801509434 |
| Directory | /workspace/44.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3544773268 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 85825056 ps |
| CPU time | 0.75 seconds |
| Started | Jul 18 05:42:24 PM PDT 24 |
| Finished | Jul 18 05:42:39 PM PDT 24 |
| Peak memory | 195624 kb |
| Host | smart-a657c4b4-d86a-4639-b326-4a98d7353ccd |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544773268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu p_pulldown.3544773268 |
| Directory | /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1112616258 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 476799763 ps |
| CPU time | 2.44 seconds |
| Started | Jul 18 05:42:26 PM PDT 24 |
| Finished | Jul 18 05:42:43 PM PDT 24 |
| Peak memory | 198204 kb |
| Host | smart-1b75cfb6-ce48-47d9-aacb-662b2736d37c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112616258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra ndom_long_reg_writes_reg_reads.1112616258 |
| Directory | /workspace/44.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/44.gpio_smoke.3440603296 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 91686125 ps |
| CPU time | 1.52 seconds |
| Started | Jul 18 05:42:21 PM PDT 24 |
| Finished | Jul 18 05:42:35 PM PDT 24 |
| Peak memory | 195784 kb |
| Host | smart-4cdc5213-0d0b-4280-9843-1af37de89fd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3440603296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3440603296 |
| Directory | /workspace/44.gpio_smoke/latest |
| Test location | /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3787638508 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 255568693 ps |
| CPU time | 1.21 seconds |
| Started | Jul 18 05:42:22 PM PDT 24 |
| Finished | Jul 18 05:42:36 PM PDT 24 |
| Peak memory | 195828 kb |
| Host | smart-5c03043d-7846-4d33-8e00-e0dbb981ec0d |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787638508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3787638508 |
| Directory | /workspace/44.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/44.gpio_stress_all.2060878348 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 10022499677 ps |
| CPU time | 122.52 seconds |
| Started | Jul 18 05:42:24 PM PDT 24 |
| Finished | Jul 18 05:44:41 PM PDT 24 |
| Peak memory | 198284 kb |
| Host | smart-8a1dac72-c618-49ae-a73c-11e94ff2ad88 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060878348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. gpio_stress_all.2060878348 |
| Directory | /workspace/44.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.3477262921 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 22178463801 ps |
| CPU time | 321.64 seconds |
| Started | Jul 18 05:42:23 PM PDT 24 |
| Finished | Jul 18 05:47:59 PM PDT 24 |
| Peak memory | 206736 kb |
| Host | smart-5f357716-df96-45c5-b5e9-13b13ad4239f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3477262921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.3477262921 |
| Directory | /workspace/44.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.gpio_alert_test.3448696840 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 20803733 ps |
| CPU time | 0.57 seconds |
| Started | Jul 18 05:42:27 PM PDT 24 |
| Finished | Jul 18 05:42:43 PM PDT 24 |
| Peak memory | 194148 kb |
| Host | smart-2c94c905-7481-4b40-8af4-db52a5abfad1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448696840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3448696840 |
| Directory | /workspace/45.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3376364354 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 79298396 ps |
| CPU time | 0.78 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:40 PM PDT 24 |
| Peak memory | 195480 kb |
| Host | smart-a20422be-978f-4bf2-b9ed-e4a2680769ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376364354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3376364354 |
| Directory | /workspace/45.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/45.gpio_filter_stress.4156092736 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 168577689 ps |
| CPU time | 8.26 seconds |
| Started | Jul 18 05:42:26 PM PDT 24 |
| Finished | Jul 18 05:42:49 PM PDT 24 |
| Peak memory | 197064 kb |
| Host | smart-3c0f1660-05fc-4b1b-bc7e-7e12783b891a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156092736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre ss.4156092736 |
| Directory | /workspace/45.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/45.gpio_full_random.3334995724 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 245500480 ps |
| CPU time | 0.89 seconds |
| Started | Jul 18 05:42:29 PM PDT 24 |
| Finished | Jul 18 05:42:46 PM PDT 24 |
| Peak memory | 197412 kb |
| Host | smart-8782a125-7622-4512-9293-10c9008c46c1 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334995724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3334995724 |
| Directory | /workspace/45.gpio_full_random/latest |
| Test location | /workspace/coverage/default/45.gpio_intr_rand_pgm.1605813542 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 30935360 ps |
| CPU time | 0.92 seconds |
| Started | Jul 18 05:42:27 PM PDT 24 |
| Finished | Jul 18 05:42:43 PM PDT 24 |
| Peak memory | 197480 kb |
| Host | smart-2c5701dd-5ba6-4341-990d-24b4d3e31f2a |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605813542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1605813542 |
| Directory | /workspace/45.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2504869451 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 22958573 ps |
| CPU time | 1.02 seconds |
| Started | Jul 18 05:42:29 PM PDT 24 |
| Finished | Jul 18 05:42:45 PM PDT 24 |
| Peak memory | 196556 kb |
| Host | smart-e2bf70c6-eee9-411d-99e6-7e82613d09b8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504869451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2504869451 |
| Directory | /workspace/45.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/45.gpio_rand_intr_trigger.1160807399 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 174718563 ps |
| CPU time | 2.59 seconds |
| Started | Jul 18 05:42:28 PM PDT 24 |
| Finished | Jul 18 05:42:46 PM PDT 24 |
| Peak memory | 196020 kb |
| Host | smart-7a7842d1-9ec4-4c3d-a213-f94552cdef5b |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160807399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger .1160807399 |
| Directory | /workspace/45.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/45.gpio_random_dout_din.3191830544 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 54962682 ps |
| CPU time | 1.17 seconds |
| Started | Jul 18 05:42:28 PM PDT 24 |
| Finished | Jul 18 05:42:44 PM PDT 24 |
| Peak memory | 197352 kb |
| Host | smart-865c026e-ec53-40d6-b047-58ccdc171f68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3191830544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3191830544 |
| Directory | /workspace/45.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3078804688 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 186757495 ps |
| CPU time | 1.07 seconds |
| Started | Jul 18 05:42:26 PM PDT 24 |
| Finished | Jul 18 05:42:42 PM PDT 24 |
| Peak memory | 196188 kb |
| Host | smart-c0357f93-0372-4b34-9104-eb490e0f8876 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078804688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu p_pulldown.3078804688 |
| Directory | /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2745477193 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 59959730 ps |
| CPU time | 1.38 seconds |
| Started | Jul 18 05:42:30 PM PDT 24 |
| Finished | Jul 18 05:42:47 PM PDT 24 |
| Peak memory | 198324 kb |
| Host | smart-92fe4337-916a-4b1a-b6c4-70e089e52048 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745477193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra ndom_long_reg_writes_reg_reads.2745477193 |
| Directory | /workspace/45.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/45.gpio_smoke.2865778634 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 85758300 ps |
| CPU time | 1.51 seconds |
| Started | Jul 18 05:42:26 PM PDT 24 |
| Finished | Jul 18 05:42:43 PM PDT 24 |
| Peak memory | 195652 kb |
| Host | smart-8c421b59-91c8-4a2e-86b9-56857fc82e55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865778634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2865778634 |
| Directory | /workspace/45.gpio_smoke/latest |
| Test location | /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1208975656 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 35686259 ps |
| CPU time | 1.21 seconds |
| Started | Jul 18 05:42:28 PM PDT 24 |
| Finished | Jul 18 05:42:45 PM PDT 24 |
| Peak memory | 196468 kb |
| Host | smart-a1a6440b-a4da-48e2-8d4b-172f5b7e9b14 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208975656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1208975656 |
| Directory | /workspace/45.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/45.gpio_stress_all.244549886 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 12564451832 ps |
| CPU time | 123.52 seconds |
| Started | Jul 18 05:42:33 PM PDT 24 |
| Finished | Jul 18 05:44:53 PM PDT 24 |
| Peak memory | 198116 kb |
| Host | smart-10bdd47f-abb5-474f-b9ac-db7b2a43c7bc |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244549886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g pio_stress_all.244549886 |
| Directory | /workspace/45.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.3381539055 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 250205011761 ps |
| CPU time | 1785.79 seconds |
| Started | Jul 18 05:42:27 PM PDT 24 |
| Finished | Jul 18 06:12:28 PM PDT 24 |
| Peak memory | 198492 kb |
| Host | smart-a2f2b089-3472-4833-8d62-6b3b31a9153f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3381539055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.3381539055 |
| Directory | /workspace/45.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.gpio_alert_test.3715383411 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 11257237 ps |
| CPU time | 0.62 seconds |
| Started | Jul 18 05:42:29 PM PDT 24 |
| Finished | Jul 18 05:42:45 PM PDT 24 |
| Peak memory | 194164 kb |
| Host | smart-38bfc4e9-1249-4742-b376-f2e210a8d35b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715383411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3715383411 |
| Directory | /workspace/46.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.641700809 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 45454524 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:42:32 PM PDT 24 |
| Finished | Jul 18 05:42:50 PM PDT 24 |
| Peak memory | 194876 kb |
| Host | smart-1dcfef7c-9fcb-43b1-813f-ab774bbb95f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=641700809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.641700809 |
| Directory | /workspace/46.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/46.gpio_filter_stress.1011406480 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 812138667 ps |
| CPU time | 27.7 seconds |
| Started | Jul 18 05:42:30 PM PDT 24 |
| Finished | Jul 18 05:43:13 PM PDT 24 |
| Peak memory | 196960 kb |
| Host | smart-73e6b8c1-1e6a-4b20-9f27-f0e9671b3d64 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011406480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre ss.1011406480 |
| Directory | /workspace/46.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/46.gpio_full_random.128352245 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 164323878 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:42:32 PM PDT 24 |
| Finished | Jul 18 05:42:49 PM PDT 24 |
| Peak memory | 197312 kb |
| Host | smart-a890d54f-7b7b-4662-90f7-8c80d490f194 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128352245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.128352245 |
| Directory | /workspace/46.gpio_full_random/latest |
| Test location | /workspace/coverage/default/46.gpio_intr_rand_pgm.2830077304 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 815981823 ps |
| CPU time | 1.26 seconds |
| Started | Jul 18 05:42:30 PM PDT 24 |
| Finished | Jul 18 05:42:47 PM PDT 24 |
| Peak memory | 195968 kb |
| Host | smart-4e4612a7-35b2-45d1-9ea9-8702407ac223 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830077304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2830077304 |
| Directory | /workspace/46.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1207005709 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 91468606 ps |
| CPU time | 3.72 seconds |
| Started | Jul 18 05:42:29 PM PDT 24 |
| Finished | Jul 18 05:42:48 PM PDT 24 |
| Peak memory | 198168 kb |
| Host | smart-b9198390-5087-4868-9642-14fdd90cc05b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207005709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1207005709 |
| Directory | /workspace/46.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/46.gpio_rand_intr_trigger.337537619 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 154693770 ps |
| CPU time | 1.38 seconds |
| Started | Jul 18 05:42:32 PM PDT 24 |
| Finished | Jul 18 05:42:51 PM PDT 24 |
| Peak memory | 196880 kb |
| Host | smart-f9657fed-7e80-4744-88b1-624ddd938da3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337537619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger. 337537619 |
| Directory | /workspace/46.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/46.gpio_random_dout_din.3414473100 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 45111080 ps |
| CPU time | 0.97 seconds |
| Started | Jul 18 05:42:26 PM PDT 24 |
| Finished | Jul 18 05:42:41 PM PDT 24 |
| Peak memory | 196064 kb |
| Host | smart-9e8ec9c6-7231-4735-b777-f327ca489cb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3414473100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3414473100 |
| Directory | /workspace/46.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2742228337 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 47249065 ps |
| CPU time | 0.77 seconds |
| Started | Jul 18 05:42:32 PM PDT 24 |
| Finished | Jul 18 05:42:50 PM PDT 24 |
| Peak memory | 195572 kb |
| Host | smart-bb63f9f9-6894-4fbe-9c7f-5e10a000ee64 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742228337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu p_pulldown.2742228337 |
| Directory | /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2213825059 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 581183311 ps |
| CPU time | 5.21 seconds |
| Started | Jul 18 05:42:29 PM PDT 24 |
| Finished | Jul 18 05:42:49 PM PDT 24 |
| Peak memory | 198164 kb |
| Host | smart-fdda2f3d-ecb4-4b5d-bc57-2a2784fd3297 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213825059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra ndom_long_reg_writes_reg_reads.2213825059 |
| Directory | /workspace/46.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/46.gpio_smoke.3140656986 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 281206901 ps |
| CPU time | 1.33 seconds |
| Started | Jul 18 05:42:26 PM PDT 24 |
| Finished | Jul 18 05:42:43 PM PDT 24 |
| Peak memory | 196872 kb |
| Host | smart-818c8169-3d84-4cff-916b-3170d1e5c017 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140656986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3140656986 |
| Directory | /workspace/46.gpio_smoke/latest |
| Test location | /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1973655940 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 81173026 ps |
| CPU time | 1.28 seconds |
| Started | Jul 18 05:42:30 PM PDT 24 |
| Finished | Jul 18 05:42:47 PM PDT 24 |
| Peak memory | 198004 kb |
| Host | smart-46f9f0ee-5129-427f-8bdc-3ccda40aa794 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973655940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1973655940 |
| Directory | /workspace/46.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/46.gpio_stress_all.772412931 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 7126274177 ps |
| CPU time | 92.19 seconds |
| Started | Jul 18 05:42:32 PM PDT 24 |
| Finished | Jul 18 05:44:21 PM PDT 24 |
| Peak memory | 198288 kb |
| Host | smart-2a013941-de02-40c4-9f34-78b331fba0d8 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772412931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g pio_stress_all.772412931 |
| Directory | /workspace/46.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/47.gpio_alert_test.4030681673 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 105002735 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:42:45 PM PDT 24 |
| Finished | Jul 18 05:43:00 PM PDT 24 |
| Peak memory | 194176 kb |
| Host | smart-5a506153-22f3-40e4-8b80-a2a5565e125c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030681673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.4030681673 |
| Directory | /workspace/47.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1178426355 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 25902737 ps |
| CPU time | 0.69 seconds |
| Started | Jul 18 05:42:21 PM PDT 24 |
| Finished | Jul 18 05:42:35 PM PDT 24 |
| Peak memory | 194164 kb |
| Host | smart-a7f40dce-4143-42fe-8c21-1272dedb9c7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178426355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1178426355 |
| Directory | /workspace/47.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/47.gpio_filter_stress.559513888 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 3171456052 ps |
| CPU time | 24.51 seconds |
| Started | Jul 18 05:42:38 PM PDT 24 |
| Finished | Jul 18 05:43:19 PM PDT 24 |
| Peak memory | 197016 kb |
| Host | smart-106f4861-06f7-4418-8cfa-70eed1d87d68 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559513888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres s.559513888 |
| Directory | /workspace/47.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/47.gpio_full_random.2222133895 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 238470223 ps |
| CPU time | 0.88 seconds |
| Started | Jul 18 05:42:36 PM PDT 24 |
| Finished | Jul 18 05:42:53 PM PDT 24 |
| Peak memory | 197372 kb |
| Host | smart-41d28919-6188-4e9b-ba9d-d2659d3a544d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222133895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2222133895 |
| Directory | /workspace/47.gpio_full_random/latest |
| Test location | /workspace/coverage/default/47.gpio_intr_rand_pgm.3937863362 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 49453152 ps |
| CPU time | 0.7 seconds |
| Started | Jul 18 05:42:29 PM PDT 24 |
| Finished | Jul 18 05:42:46 PM PDT 24 |
| Peak memory | 194692 kb |
| Host | smart-2d106605-ccf9-4b70-b6bd-acc2297a6d6d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937863362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3937863362 |
| Directory | /workspace/47.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3579616427 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 72200026 ps |
| CPU time | 1.64 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:41 PM PDT 24 |
| Peak memory | 197000 kb |
| Host | smart-0b3ad68d-4d43-49e6-a8de-e2774406dc23 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579616427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3579616427 |
| Directory | /workspace/47.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/47.gpio_rand_intr_trigger.3562998642 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 97203475 ps |
| CPU time | 1.02 seconds |
| Started | Jul 18 05:42:25 PM PDT 24 |
| Finished | Jul 18 05:42:40 PM PDT 24 |
| Peak memory | 196460 kb |
| Host | smart-4cbbee6d-f913-429f-9709-7d1ea5f21ac2 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562998642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger .3562998642 |
| Directory | /workspace/47.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/47.gpio_random_dout_din.3604356869 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 44944917 ps |
| CPU time | 1.15 seconds |
| Started | Jul 18 05:42:30 PM PDT 24 |
| Finished | Jul 18 05:42:47 PM PDT 24 |
| Peak memory | 196224 kb |
| Host | smart-48cc290c-de17-4a72-9ba4-7d552ef25bb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3604356869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3604356869 |
| Directory | /workspace/47.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1772391372 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 198882560 ps |
| CPU time | 1.05 seconds |
| Started | Jul 18 05:42:30 PM PDT 24 |
| Finished | Jul 18 05:42:47 PM PDT 24 |
| Peak memory | 195136 kb |
| Host | smart-9ed21493-7ffa-493b-b92f-ed0e5ff062ae |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772391372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu p_pulldown.1772391372 |
| Directory | /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2189936763 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 332129707 ps |
| CPU time | 4.83 seconds |
| Started | Jul 18 05:42:43 PM PDT 24 |
| Finished | Jul 18 05:43:04 PM PDT 24 |
| Peak memory | 198084 kb |
| Host | smart-6a23a711-f090-4615-890b-5cb83b3194d6 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189936763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra ndom_long_reg_writes_reg_reads.2189936763 |
| Directory | /workspace/47.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/47.gpio_smoke.3714745670 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 420714020 ps |
| CPU time | 1.46 seconds |
| Started | Jul 18 05:42:33 PM PDT 24 |
| Finished | Jul 18 05:42:51 PM PDT 24 |
| Peak memory | 195824 kb |
| Host | smart-0c45b109-82d4-494e-a18a-f18d60fdf9e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714745670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3714745670 |
| Directory | /workspace/47.gpio_smoke/latest |
| Test location | /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3202808200 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 81044258 ps |
| CPU time | 0.71 seconds |
| Started | Jul 18 05:42:30 PM PDT 24 |
| Finished | Jul 18 05:42:46 PM PDT 24 |
| Peak memory | 193264 kb |
| Host | smart-19df60d9-af4b-4059-b9f9-6b7a002b39b9 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202808200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3202808200 |
| Directory | /workspace/47.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/47.gpio_stress_all.395947162 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 4419532570 ps |
| CPU time | 62.05 seconds |
| Started | Jul 18 05:42:40 PM PDT 24 |
| Finished | Jul 18 05:43:58 PM PDT 24 |
| Peak memory | 198320 kb |
| Host | smart-f6ec9888-8c1d-44c7-acfe-a4e16757c0f4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395947162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g pio_stress_all.395947162 |
| Directory | /workspace/47.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/48.gpio_alert_test.470597435 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 22617812 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:42:39 PM PDT 24 |
| Finished | Jul 18 05:42:55 PM PDT 24 |
| Peak memory | 194232 kb |
| Host | smart-ac41c62b-fc24-4109-af08-f6cdd493a6d4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470597435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.470597435 |
| Directory | /workspace/48.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1491953816 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 45426541 ps |
| CPU time | 0.92 seconds |
| Started | Jul 18 05:42:43 PM PDT 24 |
| Finished | Jul 18 05:43:00 PM PDT 24 |
| Peak memory | 196888 kb |
| Host | smart-e304dcf5-fd8d-489b-a984-914b32c43828 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1491953816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1491953816 |
| Directory | /workspace/48.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/48.gpio_filter_stress.4125428654 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2151381620 ps |
| CPU time | 21.89 seconds |
| Started | Jul 18 05:42:38 PM PDT 24 |
| Finished | Jul 18 05:43:16 PM PDT 24 |
| Peak memory | 197292 kb |
| Host | smart-e79ac4c9-631d-465a-bd2c-1f221559ccd4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125428654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre ss.4125428654 |
| Directory | /workspace/48.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/48.gpio_full_random.2559873236 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 353401501 ps |
| CPU time | 0.97 seconds |
| Started | Jul 18 05:42:53 PM PDT 24 |
| Finished | Jul 18 05:43:09 PM PDT 24 |
| Peak memory | 198040 kb |
| Host | smart-9d21c501-a840-4b15-b6a6-fc2c469ac450 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559873236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2559873236 |
| Directory | /workspace/48.gpio_full_random/latest |
| Test location | /workspace/coverage/default/48.gpio_intr_rand_pgm.2242210046 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 39283230 ps |
| CPU time | 1 seconds |
| Started | Jul 18 05:42:40 PM PDT 24 |
| Finished | Jul 18 05:42:57 PM PDT 24 |
| Peak memory | 196284 kb |
| Host | smart-8f646e27-362c-4b12-8b51-eed6b46228a3 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242210046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2242210046 |
| Directory | /workspace/48.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2432434161 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 857064407 ps |
| CPU time | 3.29 seconds |
| Started | Jul 18 05:42:42 PM PDT 24 |
| Finished | Jul 18 05:43:00 PM PDT 24 |
| Peak memory | 198296 kb |
| Host | smart-6f702263-81d6-4c67-a00a-35c4db3912cb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432434161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2432434161 |
| Directory | /workspace/48.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/48.gpio_rand_intr_trigger.2620507014 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 550434837 ps |
| CPU time | 3.38 seconds |
| Started | Jul 18 05:42:41 PM PDT 24 |
| Finished | Jul 18 05:42:59 PM PDT 24 |
| Peak memory | 197256 kb |
| Host | smart-f8267eeb-c98a-4010-bacb-76fb96880762 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620507014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger .2620507014 |
| Directory | /workspace/48.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/48.gpio_random_dout_din.943369030 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 148229057 ps |
| CPU time | 0.83 seconds |
| Started | Jul 18 05:42:53 PM PDT 24 |
| Finished | Jul 18 05:43:09 PM PDT 24 |
| Peak memory | 196840 kb |
| Host | smart-ca055cf1-72ab-4bb2-b4ae-3c4805f2cbd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=943369030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.943369030 |
| Directory | /workspace/48.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1425119897 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 47997616 ps |
| CPU time | 1 seconds |
| Started | Jul 18 05:42:47 PM PDT 24 |
| Finished | Jul 18 05:43:04 PM PDT 24 |
| Peak memory | 196044 kb |
| Host | smart-9b0ab5c1-b3c6-4bc8-9123-ac997263eee9 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425119897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu p_pulldown.1425119897 |
| Directory | /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1026374714 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 68544308 ps |
| CPU time | 2.87 seconds |
| Started | Jul 18 05:42:38 PM PDT 24 |
| Finished | Jul 18 05:42:57 PM PDT 24 |
| Peak memory | 198124 kb |
| Host | smart-969ec231-d147-44e5-b27d-694f4ba39b1c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026374714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra ndom_long_reg_writes_reg_reads.1026374714 |
| Directory | /workspace/48.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/48.gpio_smoke.1316846575 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 65555365 ps |
| CPU time | 1.16 seconds |
| Started | Jul 18 05:42:52 PM PDT 24 |
| Finished | Jul 18 05:43:08 PM PDT 24 |
| Peak memory | 196700 kb |
| Host | smart-dc708bd5-d7da-48a7-bf9c-f1cdf89bddae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1316846575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1316846575 |
| Directory | /workspace/48.gpio_smoke/latest |
| Test location | /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1587180759 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 75381630 ps |
| CPU time | 1.14 seconds |
| Started | Jul 18 05:42:45 PM PDT 24 |
| Finished | Jul 18 05:43:01 PM PDT 24 |
| Peak memory | 196084 kb |
| Host | smart-63192289-6e79-4f71-bd5a-5d7f7e329bf8 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587180759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1587180759 |
| Directory | /workspace/48.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/48.gpio_stress_all.3018228510 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 38416658119 ps |
| CPU time | 139.65 seconds |
| Started | Jul 18 05:42:39 PM PDT 24 |
| Finished | Jul 18 05:45:14 PM PDT 24 |
| Peak memory | 198348 kb |
| Host | smart-c8ff6316-a065-470a-8eea-ee73a813ecc4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018228510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. gpio_stress_all.3018228510 |
| Directory | /workspace/48.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2008387377 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 11303425941 ps |
| CPU time | 351.44 seconds |
| Started | Jul 18 05:42:43 PM PDT 24 |
| Finished | Jul 18 05:48:50 PM PDT 24 |
| Peak memory | 198516 kb |
| Host | smart-f6d35941-28dc-4c33-9ebd-f0bcd6c7315c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2008387377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2008387377 |
| Directory | /workspace/48.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.gpio_alert_test.3529427162 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 13421786 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:42:42 PM PDT 24 |
| Finished | Jul 18 05:42:59 PM PDT 24 |
| Peak memory | 195144 kb |
| Host | smart-1b8dede0-1abf-4c2c-90cd-abf367570309 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529427162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3529427162 |
| Directory | /workspace/49.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1897032916 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 441223389 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:42:41 PM PDT 24 |
| Finished | Jul 18 05:42:57 PM PDT 24 |
| Peak memory | 196736 kb |
| Host | smart-da820f0c-5bd9-4b8b-aa19-8df3b3ec8aba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1897032916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1897032916 |
| Directory | /workspace/49.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/49.gpio_filter_stress.1760393725 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1091527860 ps |
| CPU time | 15.86 seconds |
| Started | Jul 18 05:42:52 PM PDT 24 |
| Finished | Jul 18 05:43:23 PM PDT 24 |
| Peak memory | 197188 kb |
| Host | smart-cd64d0a6-151d-47c5-930b-0f1b1a664e6e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760393725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre ss.1760393725 |
| Directory | /workspace/49.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/49.gpio_full_random.3988821878 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 104789151 ps |
| CPU time | 0.82 seconds |
| Started | Jul 18 05:42:41 PM PDT 24 |
| Finished | Jul 18 05:42:58 PM PDT 24 |
| Peak memory | 196048 kb |
| Host | smart-ff23b548-e060-4fe6-836d-32564db9af51 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988821878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3988821878 |
| Directory | /workspace/49.gpio_full_random/latest |
| Test location | /workspace/coverage/default/49.gpio_intr_rand_pgm.3403617985 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 84591188 ps |
| CPU time | 1.32 seconds |
| Started | Jul 18 05:42:43 PM PDT 24 |
| Finished | Jul 18 05:43:00 PM PDT 24 |
| Peak memory | 198264 kb |
| Host | smart-0adc4305-e153-40cc-8ae6-3371816df43c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403617985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3403617985 |
| Directory | /workspace/49.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1657453228 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 92355861 ps |
| CPU time | 4.02 seconds |
| Started | Jul 18 05:42:45 PM PDT 24 |
| Finished | Jul 18 05:43:04 PM PDT 24 |
| Peak memory | 198260 kb |
| Host | smart-5d276444-9467-4ba1-b278-da39437c6a3f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657453228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1657453228 |
| Directory | /workspace/49.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/49.gpio_rand_intr_trigger.1190946468 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 83794424 ps |
| CPU time | 1.61 seconds |
| Started | Jul 18 05:42:49 PM PDT 24 |
| Finished | Jul 18 05:43:05 PM PDT 24 |
| Peak memory | 196512 kb |
| Host | smart-aa65338b-4592-4a6b-9c3f-5dd68a21c4fd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190946468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger .1190946468 |
| Directory | /workspace/49.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/49.gpio_random_dout_din.3414586604 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 376393994 ps |
| CPU time | 1.2 seconds |
| Started | Jul 18 05:42:47 PM PDT 24 |
| Finished | Jul 18 05:43:04 PM PDT 24 |
| Peak memory | 196728 kb |
| Host | smart-f8c4502a-7643-4977-84ad-7eac612c8683 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3414586604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3414586604 |
| Directory | /workspace/49.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.4155978512 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 56784951 ps |
| CPU time | 0.75 seconds |
| Started | Jul 18 05:42:53 PM PDT 24 |
| Finished | Jul 18 05:43:09 PM PDT 24 |
| Peak memory | 195624 kb |
| Host | smart-e6cc3dc9-218f-4f44-a8fd-dca5e183fb55 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155978512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu p_pulldown.4155978512 |
| Directory | /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3601600563 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 437523371 ps |
| CPU time | 4.46 seconds |
| Started | Jul 18 05:42:41 PM PDT 24 |
| Finished | Jul 18 05:43:01 PM PDT 24 |
| Peak memory | 198216 kb |
| Host | smart-06eb9a19-7f24-4c3c-a0a0-1738bdd6b516 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601600563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra ndom_long_reg_writes_reg_reads.3601600563 |
| Directory | /workspace/49.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/49.gpio_smoke.1357816884 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 38111476 ps |
| CPU time | 1.19 seconds |
| Started | Jul 18 05:42:41 PM PDT 24 |
| Finished | Jul 18 05:42:57 PM PDT 24 |
| Peak memory | 195896 kb |
| Host | smart-aafd45f8-3986-4687-b620-304905faf689 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1357816884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1357816884 |
| Directory | /workspace/49.gpio_smoke/latest |
| Test location | /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.4201780806 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 78986219 ps |
| CPU time | 1.31 seconds |
| Started | Jul 18 05:42:50 PM PDT 24 |
| Finished | Jul 18 05:43:06 PM PDT 24 |
| Peak memory | 197272 kb |
| Host | smart-072a3371-ff1b-44d2-b8c8-af38d724b31c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201780806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.4201780806 |
| Directory | /workspace/49.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/49.gpio_stress_all.3938222965 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 13991742630 ps |
| CPU time | 161.42 seconds |
| Started | Jul 18 05:42:37 PM PDT 24 |
| Finished | Jul 18 05:45:35 PM PDT 24 |
| Peak memory | 198240 kb |
| Host | smart-64b3b55c-28de-49f9-a520-24a49b88524e |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938222965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. gpio_stress_all.3938222965 |
| Directory | /workspace/49.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/5.gpio_alert_test.3823929798 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 14189390 ps |
| CPU time | 0.53 seconds |
| Started | Jul 18 05:40:49 PM PDT 24 |
| Finished | Jul 18 05:40:55 PM PDT 24 |
| Peak memory | 194156 kb |
| Host | smart-44bd93d5-48f7-4b6e-8816-ca1e7e990af4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823929798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3823929798 |
| Directory | /workspace/5.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1572813116 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 32894769 ps |
| CPU time | 0.65 seconds |
| Started | Jul 18 05:40:52 PM PDT 24 |
| Finished | Jul 18 05:40:59 PM PDT 24 |
| Peak memory | 194200 kb |
| Host | smart-69e7d4a2-f885-485b-8c63-20c66d8b125d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1572813116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1572813116 |
| Directory | /workspace/5.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/5.gpio_filter_stress.512490568 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 147900099 ps |
| CPU time | 5.16 seconds |
| Started | Jul 18 05:40:52 PM PDT 24 |
| Finished | Jul 18 05:41:03 PM PDT 24 |
| Peak memory | 197324 kb |
| Host | smart-8ade596d-ddae-453c-93c1-b00c735bde1f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512490568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter _stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress .512490568 |
| Directory | /workspace/5.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/5.gpio_full_random.3214729830 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 229207952 ps |
| CPU time | 0.73 seconds |
| Started | Jul 18 05:40:51 PM PDT 24 |
| Finished | Jul 18 05:40:57 PM PDT 24 |
| Peak memory | 194448 kb |
| Host | smart-aa0bb3d7-445a-47c6-b67b-627acedc3c75 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214729830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3214729830 |
| Directory | /workspace/5.gpio_full_random/latest |
| Test location | /workspace/coverage/default/5.gpio_intr_rand_pgm.2569299323 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 149641878 ps |
| CPU time | 1.21 seconds |
| Started | Jul 18 05:40:55 PM PDT 24 |
| Finished | Jul 18 05:41:02 PM PDT 24 |
| Peak memory | 196364 kb |
| Host | smart-a8b2230a-7f1f-4dae-b086-a6ac02e59c67 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569299323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2569299323 |
| Directory | /workspace/5.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3080777865 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 38926203 ps |
| CPU time | 1.56 seconds |
| Started | Jul 18 05:40:53 PM PDT 24 |
| Finished | Jul 18 05:41:01 PM PDT 24 |
| Peak memory | 196876 kb |
| Host | smart-674dbb1d-d1d8-4dc0-adee-55ebecb9ff17 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080777865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3080777865 |
| Directory | /workspace/5.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/5.gpio_rand_intr_trigger.860020099 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 241489883 ps |
| CPU time | 1.6 seconds |
| Started | Jul 18 05:40:54 PM PDT 24 |
| Finished | Jul 18 05:41:02 PM PDT 24 |
| Peak memory | 196064 kb |
| Host | smart-0db6b4fd-75fc-4da4-910b-2dbbc0e99d19 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860020099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.860020099 |
| Directory | /workspace/5.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/5.gpio_random_dout_din.1983166789 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 32311308 ps |
| CPU time | 1.26 seconds |
| Started | Jul 18 05:40:49 PM PDT 24 |
| Finished | Jul 18 05:40:55 PM PDT 24 |
| Peak memory | 196840 kb |
| Host | smart-c9e0445d-0574-4c3e-8ea8-0fee88745700 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1983166789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1983166789 |
| Directory | /workspace/5.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1309134789 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 14605238 ps |
| CPU time | 0.67 seconds |
| Started | Jul 18 05:40:51 PM PDT 24 |
| Finished | Jul 18 05:40:56 PM PDT 24 |
| Peak memory | 194508 kb |
| Host | smart-9321d8ea-989b-4008-8781-d465190dfbb7 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309134789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup _pulldown.1309134789 |
| Directory | /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.916436511 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 120301820 ps |
| CPU time | 2.25 seconds |
| Started | Jul 18 05:40:51 PM PDT 24 |
| Finished | Jul 18 05:40:58 PM PDT 24 |
| Peak memory | 197872 kb |
| Host | smart-1e6c2399-3cb6-4df3-bb0c-23ea29402d38 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916436511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand om_long_reg_writes_reg_reads.916436511 |
| Directory | /workspace/5.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/5.gpio_smoke.1083608609 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 118500309 ps |
| CPU time | 1.06 seconds |
| Started | Jul 18 05:40:53 PM PDT 24 |
| Finished | Jul 18 05:41:00 PM PDT 24 |
| Peak memory | 196792 kb |
| Host | smart-0798fe8d-5297-4823-8e3a-ebdea190c795 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083608609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1083608609 |
| Directory | /workspace/5.gpio_smoke/latest |
| Test location | /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3443455230 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 31919881 ps |
| CPU time | 1.05 seconds |
| Started | Jul 18 05:40:54 PM PDT 24 |
| Finished | Jul 18 05:41:01 PM PDT 24 |
| Peak memory | 196568 kb |
| Host | smart-8282f9ab-387e-4767-87a7-8d02626d247c |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443455230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3443455230 |
| Directory | /workspace/5.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/5.gpio_stress_all.3822894778 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 69575072032 ps |
| CPU time | 107.17 seconds |
| Started | Jul 18 05:40:52 PM PDT 24 |
| Finished | Jul 18 05:42:46 PM PDT 24 |
| Peak memory | 198260 kb |
| Host | smart-946ed9ce-5bd9-4057-8566-053a2a8b6d24 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822894778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g pio_stress_all.3822894778 |
| Directory | /workspace/5.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.4139086944 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 5723337511 ps |
| CPU time | 193.81 seconds |
| Started | Jul 18 05:40:49 PM PDT 24 |
| Finished | Jul 18 05:44:08 PM PDT 24 |
| Peak memory | 198308 kb |
| Host | smart-e6337145-3ab3-4181-9c28-dfeeb3dd58ab |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4139086944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.4139086944 |
| Directory | /workspace/5.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.gpio_alert_test.3514127206 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 11225949 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:17 PM PDT 24 |
| Peak memory | 194208 kb |
| Host | smart-c07d5135-592b-4b61-b3ae-dd54b21f2eb1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514127206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3514127206 |
| Directory | /workspace/6.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1609284130 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 77146414 ps |
| CPU time | 0.75 seconds |
| Started | Jul 18 05:41:09 PM PDT 24 |
| Finished | Jul 18 05:41:16 PM PDT 24 |
| Peak memory | 194992 kb |
| Host | smart-d888abbe-6046-4644-bf92-86c49a79c289 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1609284130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1609284130 |
| Directory | /workspace/6.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/6.gpio_filter_stress.3124443169 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1395365420 ps |
| CPU time | 18.68 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:31 PM PDT 24 |
| Peak memory | 196496 kb |
| Host | smart-81f3ff80-25e8-429a-88b3-3cea9380d9fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124443169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres s.3124443169 |
| Directory | /workspace/6.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/6.gpio_full_random.1747326680 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 62743607 ps |
| CPU time | 0.97 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:12 PM PDT 24 |
| Peak memory | 198032 kb |
| Host | smart-0eef2857-af57-4f99-84e4-50ce0a4daeb7 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747326680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1747326680 |
| Directory | /workspace/6.gpio_full_random/latest |
| Test location | /workspace/coverage/default/6.gpio_intr_rand_pgm.2091664436 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 14915360 ps |
| CPU time | 0.65 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:16 PM PDT 24 |
| Peak memory | 195160 kb |
| Host | smart-080da878-6f81-49b6-afc0-e4eb68bf7147 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091664436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2091664436 |
| Directory | /workspace/6.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1226793588 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 163729631 ps |
| CPU time | 1.81 seconds |
| Started | Jul 18 05:41:13 PM PDT 24 |
| Finished | Jul 18 05:41:23 PM PDT 24 |
| Peak memory | 197484 kb |
| Host | smart-482f7f0c-1793-4086-a891-52e2c73fe6ab |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226793588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1226793588 |
| Directory | /workspace/6.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/6.gpio_rand_intr_trigger.1735260608 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 53962969 ps |
| CPU time | 1.29 seconds |
| Started | Jul 18 05:42:15 PM PDT 24 |
| Finished | Jul 18 05:42:29 PM PDT 24 |
| Peak memory | 197008 kb |
| Host | smart-8b62437a-08c5-4e8b-928e-2218e0fd62fd |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735260608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger. 1735260608 |
| Directory | /workspace/6.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/6.gpio_random_dout_din.3985635400 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 23883525 ps |
| CPU time | 0.91 seconds |
| Started | Jul 18 05:41:15 PM PDT 24 |
| Finished | Jul 18 05:41:25 PM PDT 24 |
| Peak memory | 196268 kb |
| Host | smart-c768f655-1e2a-4efc-9553-e5503624b9b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3985635400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3985635400 |
| Directory | /workspace/6.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3762018243 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 23562423 ps |
| CPU time | 0.67 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:18 PM PDT 24 |
| Peak memory | 194472 kb |
| Host | smart-6191d7ad-dd48-4e64-9f1d-38aaf63d2bb9 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762018243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup _pulldown.3762018243 |
| Directory | /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1858152197 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 697587946 ps |
| CPU time | 2.84 seconds |
| Started | Jul 18 05:41:09 PM PDT 24 |
| Finished | Jul 18 05:41:17 PM PDT 24 |
| Peak memory | 198156 kb |
| Host | smart-29eb2940-8daa-40bb-9ccd-c8eb0f8dc4fb |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858152197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran dom_long_reg_writes_reg_reads.1858152197 |
| Directory | /workspace/6.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/6.gpio_smoke.1853905576 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 70898490 ps |
| CPU time | 1.11 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:20 PM PDT 24 |
| Peak memory | 195772 kb |
| Host | smart-07dbb041-2eba-4e8f-ae67-34ee57c8de9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853905576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1853905576 |
| Directory | /workspace/6.gpio_smoke/latest |
| Test location | /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.4109533504 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 59599128 ps |
| CPU time | 1.06 seconds |
| Started | Jul 18 05:41:07 PM PDT 24 |
| Finished | Jul 18 05:41:11 PM PDT 24 |
| Peak memory | 196080 kb |
| Host | smart-f06cd463-e2e3-4ed8-a5ca-b57475a9761f |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109533504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.4109533504 |
| Directory | /workspace/6.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/6.gpio_stress_all.327371041 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 3333139375 ps |
| CPU time | 41 seconds |
| Started | Jul 18 05:41:09 PM PDT 24 |
| Finished | Jul 18 05:41:55 PM PDT 24 |
| Peak memory | 198396 kb |
| Host | smart-da9ed8c4-5204-49ed-b651-ea2bf31d8829 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327371041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp io_stress_all.327371041 |
| Directory | /workspace/6.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3338436208 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 315230477369 ps |
| CPU time | 1587.23 seconds |
| Started | Jul 18 05:41:07 PM PDT 24 |
| Finished | Jul 18 06:07:37 PM PDT 24 |
| Peak memory | 198560 kb |
| Host | smart-a25cd9eb-2ccc-422c-8a29-2be912d74de5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3338436208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.3338436208 |
| Directory | /workspace/6.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.gpio_alert_test.3884152921 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 35088099 ps |
| CPU time | 0.62 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:20 PM PDT 24 |
| Peak memory | 194840 kb |
| Host | smart-6843ed05-eb94-496d-a6f2-d924617473b7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884152921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3884152921 |
| Directory | /workspace/7.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3961238754 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 53432591 ps |
| CPU time | 0.63 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:19 PM PDT 24 |
| Peak memory | 194212 kb |
| Host | smart-710cf2e5-430e-4cbf-809b-4351f37ced1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3961238754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3961238754 |
| Directory | /workspace/7.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/7.gpio_filter_stress.3836524130 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1356598208 ps |
| CPU time | 16.99 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:30 PM PDT 24 |
| Peak memory | 196612 kb |
| Host | smart-4d810464-5346-4dc2-9110-c925a90dd853 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836524130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres s.3836524130 |
| Directory | /workspace/7.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/7.gpio_full_random.2129678559 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 81490443 ps |
| CPU time | 1.08 seconds |
| Started | Jul 18 05:41:09 PM PDT 24 |
| Finished | Jul 18 05:41:15 PM PDT 24 |
| Peak memory | 196868 kb |
| Host | smart-41d0c6ef-6da4-42dc-b077-93d31e998e69 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129678559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2129678559 |
| Directory | /workspace/7.gpio_full_random/latest |
| Test location | /workspace/coverage/default/7.gpio_intr_rand_pgm.1213542941 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 55417827 ps |
| CPU time | 1.3 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:19 PM PDT 24 |
| Peak memory | 197244 kb |
| Host | smart-2eb226bc-b2d7-42ce-8639-2251fe3a4cf4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213542941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1213542941 |
| Directory | /workspace/7.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.4144659440 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 66465884 ps |
| CPU time | 2.66 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:15 PM PDT 24 |
| Peak memory | 196504 kb |
| Host | smart-51df6483-dd97-4541-bf76-f59c0848177f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144659440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.gpio_intr_with_filter_rand_intr_event.4144659440 |
| Directory | /workspace/7.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/7.gpio_rand_intr_trigger.2594639014 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 499782874 ps |
| CPU time | 3.48 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:21 PM PDT 24 |
| Peak memory | 197412 kb |
| Host | smart-a7c853d3-aaca-48ce-a5ed-17054f23e4f5 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594639014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger. 2594639014 |
| Directory | /workspace/7.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/7.gpio_random_dout_din.4030771229 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 53037634 ps |
| CPU time | 0.97 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:17 PM PDT 24 |
| Peak memory | 196076 kb |
| Host | smart-542aa924-0c0c-4651-8e5a-d0acf032f58a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4030771229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.4030771229 |
| Directory | /workspace/7.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3646696883 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 125406389 ps |
| CPU time | 1.25 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:17 PM PDT 24 |
| Peak memory | 197196 kb |
| Host | smart-89d1f9c3-e4aa-4f1b-9c89-20dadab46074 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646696883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup _pulldown.3646696883 |
| Directory | /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1257682573 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 581625064 ps |
| CPU time | 2.51 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:21 PM PDT 24 |
| Peak memory | 198188 kb |
| Host | smart-ba07b322-6312-49b9-8202-90082e5d8d87 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257682573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran dom_long_reg_writes_reg_reads.1257682573 |
| Directory | /workspace/7.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/7.gpio_smoke.2344000473 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 51920521 ps |
| CPU time | 1.13 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:18 PM PDT 24 |
| Peak memory | 196652 kb |
| Host | smart-b862bbc9-5126-4ec3-8391-063625499315 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2344000473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2344000473 |
| Directory | /workspace/7.gpio_smoke/latest |
| Test location | /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.532548973 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 34216698 ps |
| CPU time | 1.09 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:14 PM PDT 24 |
| Peak memory | 197128 kb |
| Host | smart-55c97aa5-b19a-4d8e-9f63-9f7875b53646 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532548973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.532548973 |
| Directory | /workspace/7.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/7.gpio_stress_all.3384184646 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 56288608862 ps |
| CPU time | 142.62 seconds |
| Started | Jul 18 05:41:07 PM PDT 24 |
| Finished | Jul 18 05:43:31 PM PDT 24 |
| Peak memory | 198392 kb |
| Host | smart-516ba799-91ac-4ad1-ad06-2f75d7862e8c |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384184646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g pio_stress_all.3384184646 |
| Directory | /workspace/7.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/8.gpio_alert_test.2122512055 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 56645489 ps |
| CPU time | 0.57 seconds |
| Started | Jul 18 05:41:09 PM PDT 24 |
| Finished | Jul 18 05:41:16 PM PDT 24 |
| Peak memory | 194780 kb |
| Host | smart-4eb2d9bd-89eb-4a5e-ae12-c02fc776cc68 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122512055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2122512055 |
| Directory | /workspace/8.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1442198341 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 150505389 ps |
| CPU time | 0.98 seconds |
| Started | Jul 18 05:41:06 PM PDT 24 |
| Finished | Jul 18 05:41:09 PM PDT 24 |
| Peak memory | 196636 kb |
| Host | smart-73cb04e5-3a8c-4f4e-aa44-11f5eaae97c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1442198341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1442198341 |
| Directory | /workspace/8.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/8.gpio_filter_stress.66800170 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 6820311415 ps |
| CPU time | 17.74 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:37 PM PDT 24 |
| Peak memory | 197568 kb |
| Host | smart-2a15b1e0-1c2a-45d3-aa8a-9634bae34802 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66800170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_ stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress.66800170 |
| Directory | /workspace/8.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/8.gpio_full_random.2531157331 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 71964435 ps |
| CPU time | 0.97 seconds |
| Started | Jul 18 05:41:09 PM PDT 24 |
| Finished | Jul 18 05:41:16 PM PDT 24 |
| Peak memory | 197944 kb |
| Host | smart-f82b348b-9053-4dd2-833a-f69aac24e191 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531157331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2531157331 |
| Directory | /workspace/8.gpio_full_random/latest |
| Test location | /workspace/coverage/default/8.gpio_intr_rand_pgm.1219036816 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 55817270 ps |
| CPU time | 1.12 seconds |
| Started | Jul 18 05:41:13 PM PDT 24 |
| Finished | Jul 18 05:41:22 PM PDT 24 |
| Peak memory | 196400 kb |
| Host | smart-1b2fc408-bd5a-43d5-b4d9-4fe31a772b44 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219036816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1219036816 |
| Directory | /workspace/8.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.330459937 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 262147799 ps |
| CPU time | 2.89 seconds |
| Started | Jul 18 05:41:06 PM PDT 24 |
| Finished | Jul 18 05:41:10 PM PDT 24 |
| Peak memory | 198260 kb |
| Host | smart-89af0bcb-1c1a-4af0-8a10-ee2ba883678c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330459937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_ SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 8.gpio_intr_with_filter_rand_intr_event.330459937 |
| Directory | /workspace/8.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/8.gpio_rand_intr_trigger.3653087330 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 701987941 ps |
| CPU time | 1.48 seconds |
| Started | Jul 18 05:41:12 PM PDT 24 |
| Finished | Jul 18 05:41:21 PM PDT 24 |
| Peak memory | 195996 kb |
| Host | smart-62f546df-6ae7-421a-95de-f237a863ae43 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653087330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger. 3653087330 |
| Directory | /workspace/8.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/8.gpio_random_dout_din.1770766352 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 295540168 ps |
| CPU time | 1.15 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:17 PM PDT 24 |
| Peak memory | 196148 kb |
| Host | smart-3b20834c-442b-47b2-b014-a415fb1a2693 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770766352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1770766352 |
| Directory | /workspace/8.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3543366631 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 73297079 ps |
| CPU time | 0.7 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:19 PM PDT 24 |
| Peak memory | 194332 kb |
| Host | smart-27934835-90a7-4bbf-90f2-0033c7ee2e8b |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543366631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup _pulldown.3543366631 |
| Directory | /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.209827639 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 152504830 ps |
| CPU time | 1.89 seconds |
| Started | Jul 18 05:41:07 PM PDT 24 |
| Finished | Jul 18 05:41:12 PM PDT 24 |
| Peak memory | 198176 kb |
| Host | smart-fd1c6b6e-a6a8-43e1-ad6c-1585b18f5cae |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209827639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_ writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand om_long_reg_writes_reg_reads.209827639 |
| Directory | /workspace/8.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/8.gpio_smoke.1920270815 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 241481610 ps |
| CPU time | 1.25 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:17 PM PDT 24 |
| Peak memory | 195948 kb |
| Host | smart-df352db9-42b6-4576-b0eb-7c7cecbe7d82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1920270815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1920270815 |
| Directory | /workspace/8.gpio_smoke/latest |
| Test location | /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3188351222 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 46194571 ps |
| CPU time | 1 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:20 PM PDT 24 |
| Peak memory | 196764 kb |
| Host | smart-1c551399-a6c9-438a-988b-5b9330a1bcea |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188351222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3188351222 |
| Directory | /workspace/8.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/8.gpio_stress_all.4172886099 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 10896654361 ps |
| CPU time | 69.23 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:42:26 PM PDT 24 |
| Peak memory | 198292 kb |
| Host | smart-8638cc78-0c6b-46d2-9aad-be8ed6771793 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172886099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g pio_stress_all.4172886099 |
| Directory | /workspace/8.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/9.gpio_alert_test.2184474432 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 26708754 ps |
| CPU time | 0.59 seconds |
| Started | Jul 18 05:41:06 PM PDT 24 |
| Finished | Jul 18 05:41:08 PM PDT 24 |
| Peak memory | 194164 kb |
| Host | smart-d3a04294-9c1c-43dc-9152-4ed394693f38 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184474432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2184474432 |
| Directory | /workspace/9.gpio_alert_test/latest |
| Test location | /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.4099808804 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 123307862 ps |
| CPU time | 0.74 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:12 PM PDT 24 |
| Peak memory | 195432 kb |
| Host | smart-f64fbf48-a3e8-4924-b394-75aa0f345141 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4099808804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.4099808804 |
| Directory | /workspace/9.gpio_dout_din_regs_random_rw/latest |
| Test location | /workspace/coverage/default/9.gpio_filter_stress.2009133411 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 986057789 ps |
| CPU time | 13.14 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:32 PM PDT 24 |
| Peak memory | 198240 kb |
| Host | smart-b842d4a3-69d5-4cd8-ab93-9ed83404c29e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009133411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres s.2009133411 |
| Directory | /workspace/9.gpio_filter_stress/latest |
| Test location | /workspace/coverage/default/9.gpio_full_random.538029344 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 256993036 ps |
| CPU time | 0.96 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:20 PM PDT 24 |
| Peak memory | 197368 kb |
| Host | smart-337cf155-96bb-4910-9140-1577c6e0c088 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538029344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.538029344 |
| Directory | /workspace/9.gpio_full_random/latest |
| Test location | /workspace/coverage/default/9.gpio_intr_rand_pgm.1965713732 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 75799765 ps |
| CPU time | 1.12 seconds |
| Started | Jul 18 05:41:11 PM PDT 24 |
| Finished | Jul 18 05:41:19 PM PDT 24 |
| Peak memory | 196416 kb |
| Host | smart-d1dc24bd-886f-484c-8dad-fc7d84a02d7f |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965713732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1965713732 |
| Directory | /workspace/9.gpio_intr_rand_pgm/latest |
| Test location | /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1285927078 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 60686401 ps |
| CPU time | 1.46 seconds |
| Started | Jul 18 05:41:09 PM PDT 24 |
| Finished | Jul 18 05:41:16 PM PDT 24 |
| Peak memory | 198216 kb |
| Host | smart-24f49eb0-b2cd-4f61-b1e0-c9e4f796fc47 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285927078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST _SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1285927078 |
| Directory | /workspace/9.gpio_intr_with_filter_rand_intr_event/latest |
| Test location | /workspace/coverage/default/9.gpio_rand_intr_trigger.4199068307 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 140159156 ps |
| CPU time | 2.78 seconds |
| Started | Jul 18 05:42:13 PM PDT 24 |
| Finished | Jul 18 05:42:29 PM PDT 24 |
| Peak memory | 198264 kb |
| Host | smart-2d2bb8d8-68c4-41b0-8130-add2d0282de0 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199068307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger. 4199068307 |
| Directory | /workspace/9.gpio_rand_intr_trigger/latest |
| Test location | /workspace/coverage/default/9.gpio_random_dout_din.1715234361 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 314662385 ps |
| CPU time | 0.83 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:18 PM PDT 24 |
| Peak memory | 196732 kb |
| Host | smart-4d16a2de-e47b-47ab-a3ca-49d3dfc0d4be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1715234361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1715234361 |
| Directory | /workspace/9.gpio_random_dout_din/latest |
| Test location | /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3798845681 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 59468230 ps |
| CPU time | 1.1 seconds |
| Started | Jul 18 05:41:08 PM PDT 24 |
| Finished | Jul 18 05:41:14 PM PDT 24 |
| Peak memory | 196140 kb |
| Host | smart-74c9b5dc-def3-466b-957e-eafed2365cf6 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798845681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup _pulldown.3798845681 |
| Directory | /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2329959657 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 337297376 ps |
| CPU time | 3.91 seconds |
| Started | Jul 18 05:41:15 PM PDT 24 |
| Finished | Jul 18 05:41:28 PM PDT 24 |
| Peak memory | 198184 kb |
| Host | smart-1fbf2541-c564-44dd-9186-fa7dc97e295d |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329959657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg _writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran dom_long_reg_writes_reg_reads.2329959657 |
| Directory | /workspace/9.gpio_random_long_reg_writes_reg_reads/latest |
| Test location | /workspace/coverage/default/9.gpio_smoke.3981650654 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 150784051 ps |
| CPU time | 1.47 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:17 PM PDT 24 |
| Peak memory | 197168 kb |
| Host | smart-f79455cf-a8ed-4be0-a2c1-a92ec9a3ed53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3981650654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3981650654 |
| Directory | /workspace/9.gpio_smoke/latest |
| Test location | /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1570888771 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 84690987 ps |
| CPU time | 1.52 seconds |
| Started | Jul 18 05:41:10 PM PDT 24 |
| Finished | Jul 18 05:41:17 PM PDT 24 |
| Peak memory | 196492 kb |
| Host | smart-eeb20dec-ee3b-4d18-abd0-4013fa5d3f57 |
| User | root |
| Command | /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570888771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1570888771 |
| Directory | /workspace/9.gpio_smoke_no_pullup_pulldown/latest |
| Test location | /workspace/coverage/default/9.gpio_stress_all.1609176555 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 22878936052 ps |
| CPU time | 176.62 seconds |
| Started | Jul 18 05:41:09 PM PDT 24 |
| Finished | Jul 18 05:44:12 PM PDT 24 |
| Peak memory | 198272 kb |
| Host | smart-c4f3a86f-6e5a-490c-ab8b-d410a98170d9 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609176555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_ TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g pio_stress_all.1609176555 |
| Directory | /workspace/9.gpio_stress_all/latest |
| Test location | /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2335385601 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 19644591352 ps |
| CPU time | 568.63 seconds |
| Started | Jul 18 05:41:06 PM PDT 24 |
| Finished | Jul 18 05:50:36 PM PDT 24 |
| Peak memory | 198456 kb |
| Host | smart-d20504aa-a80d-4290-95b9-b9d2752a91b4 |
| User | root |
| Command | /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2335385601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.2335385601 |
| Directory | /workspace/9.gpio_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2550664373 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 40955223 ps |
| CPU time | 0.94 seconds |
| Started | Jul 18 05:40:27 PM PDT 24 |
| Finished | Jul 18 05:40:34 PM PDT 24 |
| Peak memory | 198404 kb |
| Host | smart-ee73e0d5-0f3e-4777-ad17-eff265aa01da |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2550664373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2550664373 |
| Directory | /workspace/0.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.404806343 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 677046553 ps |
| CPU time | 1.41 seconds |
| Started | Jul 18 05:40:17 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 192200 kb |
| Host | smart-0ab44a05-c173-42db-9989-22f84f1a1940 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404806343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e n_cdc_prim.404806343 |
| Directory | /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4154800299 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 86321243 ps |
| CPU time | 1.14 seconds |
| Started | Jul 18 05:40:16 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 192180 kb |
| Host | smart-b416bd73-2f79-4db4-a874-1617f90296d4 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4154800299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.4154800299 |
| Directory | /workspace/1.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2149121292 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 210485923 ps |
| CPU time | 0.78 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:25 PM PDT 24 |
| Peak memory | 192008 kb |
| Host | smart-87f0234c-cffe-43dc-b354-5a159383b132 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149121292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.2149121292 |
| Directory | /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2443084253 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 47051964 ps |
| CPU time | 0.93 seconds |
| Started | Jul 18 05:40:26 PM PDT 24 |
| Finished | Jul 18 05:40:34 PM PDT 24 |
| Peak memory | 192132 kb |
| Host | smart-7ed715d2-561b-4a00-9b7e-d86caa861d0f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2443084253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2443084253 |
| Directory | /workspace/10.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.865017286 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 279993812 ps |
| CPU time | 1.05 seconds |
| Started | Jul 18 05:40:17 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 192164 kb |
| Host | smart-a6368158-229c-4582-8d80-dd5a0de2e32e |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865017286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.865017286 |
| Directory | /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.238354402 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 182874006 ps |
| CPU time | 1.31 seconds |
| Started | Jul 18 05:40:28 PM PDT 24 |
| Finished | Jul 18 05:40:36 PM PDT 24 |
| Peak memory | 192136 kb |
| Host | smart-0a43b603-a036-41cd-82df-ca3a371d9750 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=238354402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.238354402 |
| Directory | /workspace/11.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2098888629 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 77496945 ps |
| CPU time | 0.99 seconds |
| Started | Jul 18 05:40:19 PM PDT 24 |
| Finished | Jul 18 05:40:30 PM PDT 24 |
| Peak memory | 191992 kb |
| Host | smart-d25ddfe7-9027-4720-8aef-0cb8d52f48a6 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098888629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2098888629 |
| Directory | /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2396837059 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 35801443 ps |
| CPU time | 1.07 seconds |
| Started | Jul 18 05:40:16 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 192096 kb |
| Host | smart-818e5311-0ad6-4c89-8b8e-42a3c98c0d95 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2396837059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2396837059 |
| Directory | /workspace/12.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1008602360 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 48535610 ps |
| CPU time | 1.04 seconds |
| Started | Jul 18 05:40:20 PM PDT 24 |
| Finished | Jul 18 05:40:30 PM PDT 24 |
| Peak memory | 197812 kb |
| Host | smart-8ba9b787-96d2-4fe3-8f86-7e0cadf6fa72 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008602360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1008602360 |
| Directory | /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2813167943 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 132076783 ps |
| CPU time | 0.85 seconds |
| Started | Jul 18 05:40:19 PM PDT 24 |
| Finished | Jul 18 05:40:29 PM PDT 24 |
| Peak memory | 196760 kb |
| Host | smart-e907acaf-a28b-4c1e-b1a8-47f1f4975f6d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2813167943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2813167943 |
| Directory | /workspace/13.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4176568304 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 347662636 ps |
| CPU time | 1.36 seconds |
| Started | Jul 18 05:40:17 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 192192 kb |
| Host | smart-2d9c57a9-9f97-424f-beeb-d8967345464c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176568304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown _en_cdc_prim.4176568304 |
| Directory | /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1288921522 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 34334992 ps |
| CPU time | 0.86 seconds |
| Started | Jul 18 05:40:19 PM PDT 24 |
| Finished | Jul 18 05:40:30 PM PDT 24 |
| Peak memory | 196404 kb |
| Host | smart-45194d2c-de59-4f37-b897-0e1e2aec627b |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1288921522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1288921522 |
| Directory | /workspace/14.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.512979252 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 223017841 ps |
| CPU time | 1.4 seconds |
| Started | Jul 18 05:40:19 PM PDT 24 |
| Finished | Jul 18 05:40:30 PM PDT 24 |
| Peak memory | 198484 kb |
| Host | smart-57f6a926-1f9b-469e-bc1f-68ddd7a28641 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512979252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.512979252 |
| Directory | /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2156578572 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 41406327 ps |
| CPU time | 1.16 seconds |
| Started | Jul 18 05:40:20 PM PDT 24 |
| Finished | Jul 18 05:40:30 PM PDT 24 |
| Peak memory | 192140 kb |
| Host | smart-2c068bc8-868e-45c2-aae6-85156987b734 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2156578572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2156578572 |
| Directory | /workspace/15.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4085613591 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 38872674 ps |
| CPU time | 1.05 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:24 PM PDT 24 |
| Peak memory | 192160 kb |
| Host | smart-775c8902-7370-46e5-ac84-29a05fcd4fb2 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085613591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown _en_cdc_prim.4085613591 |
| Directory | /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3229086727 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 45993688 ps |
| CPU time | 1.34 seconds |
| Started | Jul 18 05:40:20 PM PDT 24 |
| Finished | Jul 18 05:40:31 PM PDT 24 |
| Peak memory | 192140 kb |
| Host | smart-43ff9f52-f197-41da-9473-c88fd69acbaf |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3229086727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3229086727 |
| Directory | /workspace/16.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.904006568 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 67837170 ps |
| CPU time | 1.24 seconds |
| Started | Jul 18 05:40:20 PM PDT 24 |
| Finished | Jul 18 05:40:30 PM PDT 24 |
| Peak memory | 192112 kb |
| Host | smart-253066d2-8227-4071-be19-f494fbe62175 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904006568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.904006568 |
| Directory | /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3514240142 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 22220920 ps |
| CPU time | 0.83 seconds |
| Started | Jul 18 05:40:20 PM PDT 24 |
| Finished | Jul 18 05:40:30 PM PDT 24 |
| Peak memory | 191900 kb |
| Host | smart-155669ca-866d-4d08-a98a-4a00a024ba6c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3514240142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3514240142 |
| Directory | /workspace/17.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2905352567 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 96027522 ps |
| CPU time | 1.33 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:25 PM PDT 24 |
| Peak memory | 192120 kb |
| Host | smart-32a16910-f3e2-41d9-ab5e-c3330ba0fec0 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905352567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2905352567 |
| Directory | /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.4007077148 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 32048934 ps |
| CPU time | 0.73 seconds |
| Started | Jul 18 05:40:19 PM PDT 24 |
| Finished | Jul 18 05:40:30 PM PDT 24 |
| Peak memory | 191924 kb |
| Host | smart-00c31b4d-5cc9-4de4-b015-e33f9c8b8109 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4007077148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.4007077148 |
| Directory | /workspace/18.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4061083053 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 46385550 ps |
| CPU time | 0.87 seconds |
| Started | Jul 18 05:40:13 PM PDT 24 |
| Finished | Jul 18 05:40:23 PM PDT 24 |
| Peak memory | 197720 kb |
| Host | smart-93ace8eb-2a6a-403c-8172-f7b385656726 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061083053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown _en_cdc_prim.4061083053 |
| Directory | /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1447119233 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 76730072 ps |
| CPU time | 1.25 seconds |
| Started | Jul 18 05:40:33 PM PDT 24 |
| Finished | Jul 18 05:40:43 PM PDT 24 |
| Peak memory | 192196 kb |
| Host | smart-f82af3c7-e45c-4046-98fe-8a741c37de81 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1447119233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1447119233 |
| Directory | /workspace/19.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3931768469 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 142477342 ps |
| CPU time | 0.97 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:39 PM PDT 24 |
| Peak memory | 192460 kb |
| Host | smart-4645c92c-d03d-433b-88c2-567a92d2f8be |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931768469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3931768469 |
| Directory | /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2885901305 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 44483440 ps |
| CPU time | 1.25 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:25 PM PDT 24 |
| Peak memory | 198596 kb |
| Host | smart-418f48c0-8d57-4f98-9354-b9b76aae92bc |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2885901305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2885901305 |
| Directory | /workspace/2.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.884099063 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 61341770 ps |
| CPU time | 0.78 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:25 PM PDT 24 |
| Peak memory | 192016 kb |
| Host | smart-979d375d-533e-4c59-b9b2-689709c3a333 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884099063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e n_cdc_prim.884099063 |
| Directory | /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.525454268 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 254660080 ps |
| CPU time | 1.1 seconds |
| Started | Jul 18 05:40:34 PM PDT 24 |
| Finished | Jul 18 05:40:43 PM PDT 24 |
| Peak memory | 198072 kb |
| Host | smart-5a066c69-f34f-4a28-9a23-336bab3e9d74 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=525454268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.525454268 |
| Directory | /workspace/20.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.544870160 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 41887457 ps |
| CPU time | 0.93 seconds |
| Started | Jul 18 05:40:32 PM PDT 24 |
| Finished | Jul 18 05:40:42 PM PDT 24 |
| Peak memory | 191920 kb |
| Host | smart-b28524e8-7413-4302-ad33-ca60d514167a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544870160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.544870160 |
| Directory | /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.446651654 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 121116864 ps |
| CPU time | 1.17 seconds |
| Started | Jul 18 05:40:29 PM PDT 24 |
| Finished | Jul 18 05:40:37 PM PDT 24 |
| Peak memory | 192184 kb |
| Host | smart-6f06dfac-f2fa-494f-9adb-a6e9b96c3ade |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=446651654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.446651654 |
| Directory | /workspace/21.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.796419896 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 183156141 ps |
| CPU time | 1.04 seconds |
| Started | Jul 18 05:40:31 PM PDT 24 |
| Finished | Jul 18 05:40:41 PM PDT 24 |
| Peak memory | 197812 kb |
| Host | smart-e6d1a17e-4893-4e64-98fe-005c87095a08 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796419896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.796419896 |
| Directory | /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2106761391 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 94486864 ps |
| CPU time | 1.4 seconds |
| Started | Jul 18 05:40:28 PM PDT 24 |
| Finished | Jul 18 05:40:36 PM PDT 24 |
| Peak memory | 192164 kb |
| Host | smart-8282eb26-e04e-422c-bfde-a4cd75008f73 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2106761391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2106761391 |
| Directory | /workspace/22.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2402347216 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 316776462 ps |
| CPU time | 1.42 seconds |
| Started | Jul 18 05:40:34 PM PDT 24 |
| Finished | Jul 18 05:40:43 PM PDT 24 |
| Peak memory | 192180 kb |
| Host | smart-7b558d0f-685e-4b1e-a0b7-b73b34561267 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402347216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2402347216 |
| Directory | /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.602608641 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 500567947 ps |
| CPU time | 1.23 seconds |
| Started | Jul 18 05:40:33 PM PDT 24 |
| Finished | Jul 18 05:40:43 PM PDT 24 |
| Peak memory | 192156 kb |
| Host | smart-7ab176c0-c169-4641-bc19-e10beac7d7c1 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=602608641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.602608641 |
| Directory | /workspace/23.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3632057979 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 137504848 ps |
| CPU time | 1.18 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:39 PM PDT 24 |
| Peak memory | 192120 kb |
| Host | smart-8c89fbd9-5405-49fd-a36f-7103ba9b0d06 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632057979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3632057979 |
| Directory | /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.907325980 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 110999227 ps |
| CPU time | 0.91 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:39 PM PDT 24 |
| Peak memory | 197464 kb |
| Host | smart-7b07a91f-882b-4518-b5c6-cf9ed941edf2 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=907325980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.907325980 |
| Directory | /workspace/24.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3767603466 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 48685737 ps |
| CPU time | 1.34 seconds |
| Started | Jul 18 05:40:33 PM PDT 24 |
| Finished | Jul 18 05:40:43 PM PDT 24 |
| Peak memory | 192140 kb |
| Host | smart-b716c0a9-6c36-41dd-b9e8-022faa13507a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767603466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3767603466 |
| Directory | /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.285027149 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 210077630 ps |
| CPU time | 1 seconds |
| Started | Jul 18 05:40:29 PM PDT 24 |
| Finished | Jul 18 05:40:36 PM PDT 24 |
| Peak memory | 191972 kb |
| Host | smart-ff859e5f-89bf-4a6e-82eb-561b74e6e799 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=285027149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.285027149 |
| Directory | /workspace/25.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.621280804 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 48883020 ps |
| CPU time | 1.04 seconds |
| Started | Jul 18 05:40:32 PM PDT 24 |
| Finished | Jul 18 05:40:42 PM PDT 24 |
| Peak memory | 192184 kb |
| Host | smart-de11b115-ee1a-4172-bfdd-8e7d20b68efc |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621280804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.621280804 |
| Directory | /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3503654885 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 71317143 ps |
| CPU time | 1.33 seconds |
| Started | Jul 18 05:40:29 PM PDT 24 |
| Finished | Jul 18 05:40:37 PM PDT 24 |
| Peak memory | 192180 kb |
| Host | smart-ab7879ab-78d6-48e4-a4c0-9ae6687a5566 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3503654885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3503654885 |
| Directory | /workspace/26.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1758740339 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 96180213 ps |
| CPU time | 0.9 seconds |
| Started | Jul 18 05:40:35 PM PDT 24 |
| Finished | Jul 18 05:40:43 PM PDT 24 |
| Peak memory | 196772 kb |
| Host | smart-053b98c0-3c0b-41a8-ba9f-56ece7dd0284 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758740339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1758740339 |
| Directory | /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.441217706 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 58424131 ps |
| CPU time | 1.07 seconds |
| Started | Jul 18 05:40:32 PM PDT 24 |
| Finished | Jul 18 05:40:41 PM PDT 24 |
| Peak memory | 191984 kb |
| Host | smart-1578276d-6536-4f8b-98a7-d0155e1ae5f1 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=441217706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.441217706 |
| Directory | /workspace/27.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2818258733 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 139927921 ps |
| CPU time | 1.31 seconds |
| Started | Jul 18 05:40:34 PM PDT 24 |
| Finished | Jul 18 05:40:44 PM PDT 24 |
| Peak memory | 192140 kb |
| Host | smart-a72788b5-5b27-4857-93b7-e3d9e5702e44 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818258733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2818258733 |
| Directory | /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.996340710 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 76487785 ps |
| CPU time | 0.97 seconds |
| Started | Jul 18 05:40:32 PM PDT 24 |
| Finished | Jul 18 05:40:41 PM PDT 24 |
| Peak memory | 197840 kb |
| Host | smart-4265e13f-3365-48b0-b58a-5da2e970219d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=996340710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.996340710 |
| Directory | /workspace/28.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.936284082 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 39672405 ps |
| CPU time | 1.08 seconds |
| Started | Jul 18 05:40:31 PM PDT 24 |
| Finished | Jul 18 05:40:40 PM PDT 24 |
| Peak memory | 197768 kb |
| Host | smart-2b861bf1-2327-4033-9a32-2beb12b22287 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936284082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.936284082 |
| Directory | /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4007478026 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 222514831 ps |
| CPU time | 1.25 seconds |
| Started | Jul 18 05:40:32 PM PDT 24 |
| Finished | Jul 18 05:40:42 PM PDT 24 |
| Peak memory | 198528 kb |
| Host | smart-82256c12-efaf-4bfa-8336-3d9deb64ca4f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4007478026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.4007478026 |
| Directory | /workspace/29.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3953874762 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 790992443 ps |
| CPU time | 1.3 seconds |
| Started | Jul 18 05:40:32 PM PDT 24 |
| Finished | Jul 18 05:40:42 PM PDT 24 |
| Peak memory | 192100 kb |
| Host | smart-6cbd4cbd-18f6-4211-9cf9-31979b54c30a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953874762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3953874762 |
| Directory | /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.357944971 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 97158278 ps |
| CPU time | 1.54 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:25 PM PDT 24 |
| Peak memory | 192184 kb |
| Host | smart-f4eb2db4-fa75-4042-bee0-e1d8883e9797 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=357944971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.357944971 |
| Directory | /workspace/3.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3539202031 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 88777229 ps |
| CPU time | 1.44 seconds |
| Started | Jul 18 05:40:12 PM PDT 24 |
| Finished | Jul 18 05:40:23 PM PDT 24 |
| Peak memory | 192132 kb |
| Host | smart-21beaa56-d2e0-4d16-b2d6-b81fc8ab3925 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539202031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.3539202031 |
| Directory | /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.4011406358 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 103005929 ps |
| CPU time | 1.54 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:39 PM PDT 24 |
| Peak memory | 192136 kb |
| Host | smart-c8458ba6-7a8d-4ca9-98b8-2678bf2b438d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4011406358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.4011406358 |
| Directory | /workspace/30.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1787487947 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 64504208 ps |
| CPU time | 1.04 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:39 PM PDT 24 |
| Peak memory | 198804 kb |
| Host | smart-3465f97d-ae54-4a4e-8070-92e4e64b21f9 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787487947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1787487947 |
| Directory | /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2205715208 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 144329268 ps |
| CPU time | 0.94 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:38 PM PDT 24 |
| Peak memory | 191960 kb |
| Host | smart-d12901da-c3bd-44ea-8e22-7361725d181e |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2205715208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2205715208 |
| Directory | /workspace/31.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1351291663 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 92826955 ps |
| CPU time | 0.99 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:38 PM PDT 24 |
| Peak memory | 192116 kb |
| Host | smart-bbd8b103-abbd-4e0b-bb59-fb66f575e7ce |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351291663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1351291663 |
| Directory | /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3951090057 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 93856822 ps |
| CPU time | 1 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:38 PM PDT 24 |
| Peak memory | 192140 kb |
| Host | smart-23a951ce-5f94-44ee-a8c7-d31136f41f5d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3951090057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3951090057 |
| Directory | /workspace/32.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.803417019 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 179866194 ps |
| CPU time | 1 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:39 PM PDT 24 |
| Peak memory | 191960 kb |
| Host | smart-3110f4be-d186-4da9-8fe6-6dce316dd059 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803417019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.803417019 |
| Directory | /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1144911943 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 122393322 ps |
| CPU time | 1.42 seconds |
| Started | Jul 18 05:40:34 PM PDT 24 |
| Finished | Jul 18 05:40:43 PM PDT 24 |
| Peak memory | 192192 kb |
| Host | smart-e03e0af7-fc16-4e9d-bf86-f8fcbe0269e7 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1144911943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1144911943 |
| Directory | /workspace/33.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3097476855 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 56548262 ps |
| CPU time | 1.16 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:39 PM PDT 24 |
| Peak memory | 192124 kb |
| Host | smart-2fa4ee6f-e032-4913-9335-503b3ec6318d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097476855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3097476855 |
| Directory | /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1961383554 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 214153657 ps |
| CPU time | 0.84 seconds |
| Started | Jul 18 05:40:28 PM PDT 24 |
| Finished | Jul 18 05:40:36 PM PDT 24 |
| Peak memory | 191984 kb |
| Host | smart-5910c2aa-3043-482e-96a4-5ac391292efe |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1961383554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1961383554 |
| Directory | /workspace/34.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1659993593 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 185131927 ps |
| CPU time | 0.9 seconds |
| Started | Jul 18 05:41:55 PM PDT 24 |
| Finished | Jul 18 05:42:08 PM PDT 24 |
| Peak memory | 196780 kb |
| Host | smart-366d85e2-1096-4700-b66e-223884efb0fe |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659993593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1659993593 |
| Directory | /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1796356031 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 142649150 ps |
| CPU time | 0.72 seconds |
| Started | Jul 18 05:40:27 PM PDT 24 |
| Finished | Jul 18 05:40:34 PM PDT 24 |
| Peak memory | 191940 kb |
| Host | smart-f08526ab-33cb-42c7-9fd1-4c91783cf936 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1796356031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1796356031 |
| Directory | /workspace/35.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1736367054 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 97356200 ps |
| CPU time | 0.94 seconds |
| Started | Jul 18 05:40:31 PM PDT 24 |
| Finished | Jul 18 05:40:40 PM PDT 24 |
| Peak memory | 192012 kb |
| Host | smart-ad21872f-2182-4a11-9fe8-3edc1d0aaeb7 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736367054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1736367054 |
| Directory | /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3759826111 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 148424973 ps |
| CPU time | 1.39 seconds |
| Started | Jul 18 05:40:32 PM PDT 24 |
| Finished | Jul 18 05:40:41 PM PDT 24 |
| Peak memory | 192172 kb |
| Host | smart-2060eb31-dc66-4f71-a6e2-6640c09a4912 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3759826111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3759826111 |
| Directory | /workspace/36.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2328116304 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 136647370 ps |
| CPU time | 1.13 seconds |
| Started | Jul 18 05:40:33 PM PDT 24 |
| Finished | Jul 18 05:40:43 PM PDT 24 |
| Peak memory | 192160 kb |
| Host | smart-243fb20b-a89f-4daa-af14-9e3aa8025bce |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328116304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2328116304 |
| Directory | /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.566875886 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 50671477 ps |
| CPU time | 0.84 seconds |
| Started | Jul 18 05:40:29 PM PDT 24 |
| Finished | Jul 18 05:40:37 PM PDT 24 |
| Peak memory | 191960 kb |
| Host | smart-0cdbfa57-6f89-48c8-b1f9-59739da528c9 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=566875886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.566875886 |
| Directory | /workspace/37.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2732451449 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 201012368 ps |
| CPU time | 1.29 seconds |
| Started | Jul 18 05:40:34 PM PDT 24 |
| Finished | Jul 18 05:40:43 PM PDT 24 |
| Peak memory | 192180 kb |
| Host | smart-fbdb6906-309e-4b34-99b3-0ebb33b3776e |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732451449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2732451449 |
| Directory | /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2130624407 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 272649053 ps |
| CPU time | 0.9 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:39 PM PDT 24 |
| Peak memory | 192004 kb |
| Host | smart-23c56130-9a36-4a96-bbeb-19370c864e0f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2130624407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2130624407 |
| Directory | /workspace/38.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2973699251 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 287163313 ps |
| CPU time | 1.32 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:39 PM PDT 24 |
| Peak memory | 192144 kb |
| Host | smart-81ad69bc-c8c7-4b76-9845-bcc031a29795 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973699251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2973699251 |
| Directory | /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1074506532 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 261541114 ps |
| CPU time | 1.24 seconds |
| Started | Jul 18 05:40:31 PM PDT 24 |
| Finished | Jul 18 05:40:40 PM PDT 24 |
| Peak memory | 192192 kb |
| Host | smart-9c13ba21-b44a-4135-a138-1559c35faac0 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1074506532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1074506532 |
| Directory | /workspace/39.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3287068051 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 231668433 ps |
| CPU time | 1.05 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:39 PM PDT 24 |
| Peak memory | 197776 kb |
| Host | smart-28bd549c-2a94-468b-b19d-67d2e6611eda |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287068051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3287068051 |
| Directory | /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1191826687 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 176379892 ps |
| CPU time | 0.98 seconds |
| Started | Jul 18 05:40:13 PM PDT 24 |
| Finished | Jul 18 05:40:24 PM PDT 24 |
| Peak memory | 192136 kb |
| Host | smart-430e00bf-56d6-4e7f-8c7a-dd4c946caf9a |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1191826687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1191826687 |
| Directory | /workspace/4.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1305096599 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 30403509 ps |
| CPU time | 0.78 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:26 PM PDT 24 |
| Peak memory | 192008 kb |
| Host | smart-e0af4b73-b412-41b0-b4fa-371e5cad528c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305096599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.1305096599 |
| Directory | /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4258491335 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 141945021 ps |
| CPU time | 1.03 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:38 PM PDT 24 |
| Peak memory | 192144 kb |
| Host | smart-7d11e077-5276-484e-8498-c7c7ca2d1b95 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4258491335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.4258491335 |
| Directory | /workspace/40.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1018751141 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 79624058 ps |
| CPU time | 1.07 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:39 PM PDT 24 |
| Peak memory | 192148 kb |
| Host | smart-d6d625cc-2408-461b-882c-9d928005c544 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018751141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1018751141 |
| Directory | /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1181398874 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 58245176 ps |
| CPU time | 1.2 seconds |
| Started | Jul 18 05:40:35 PM PDT 24 |
| Finished | Jul 18 05:40:44 PM PDT 24 |
| Peak memory | 192164 kb |
| Host | smart-88e4d1ec-8288-467b-a4a4-e487ba58145c |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1181398874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1181398874 |
| Directory | /workspace/41.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.519521651 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 55380419 ps |
| CPU time | 1.19 seconds |
| Started | Jul 18 05:40:32 PM PDT 24 |
| Finished | Jul 18 05:40:42 PM PDT 24 |
| Peak memory | 192132 kb |
| Host | smart-88779d4e-56a7-4ce3-b6c6-301787260d5b |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519521651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.519521651 |
| Directory | /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4024789341 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 208641389 ps |
| CPU time | 1.01 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:38 PM PDT 24 |
| Peak memory | 197772 kb |
| Host | smart-eec15d08-2dd3-47d8-bf14-75dfb33ff4ef |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4024789341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.4024789341 |
| Directory | /workspace/42.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2347846361 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 111333143 ps |
| CPU time | 0.83 seconds |
| Started | Jul 18 05:40:31 PM PDT 24 |
| Finished | Jul 18 05:40:40 PM PDT 24 |
| Peak memory | 191924 kb |
| Host | smart-004f0eee-e536-4723-a09e-ec69909f8c1d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347846361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2347846361 |
| Directory | /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2910046788 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 308013036 ps |
| CPU time | 1.38 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:38 PM PDT 24 |
| Peak memory | 198212 kb |
| Host | smart-9299baf6-8562-40ae-bd71-230883dca38f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2910046788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2910046788 |
| Directory | /workspace/43.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4255990974 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 298105574 ps |
| CPU time | 1.21 seconds |
| Started | Jul 18 05:40:31 PM PDT 24 |
| Finished | Jul 18 05:40:40 PM PDT 24 |
| Peak memory | 192168 kb |
| Host | smart-c6e10caa-6f9c-4285-ab9d-389da8c67b23 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255990974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown _en_cdc_prim.4255990974 |
| Directory | /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3381860349 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 88650190 ps |
| CPU time | 0.97 seconds |
| Started | Jul 18 05:40:27 PM PDT 24 |
| Finished | Jul 18 05:40:35 PM PDT 24 |
| Peak memory | 192124 kb |
| Host | smart-f312fa6d-569f-445c-929d-f9fd8565fd17 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3381860349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3381860349 |
| Directory | /workspace/44.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1603818806 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 43266899 ps |
| CPU time | 1.02 seconds |
| Started | Jul 18 05:40:35 PM PDT 24 |
| Finished | Jul 18 05:40:43 PM PDT 24 |
| Peak memory | 197812 kb |
| Host | smart-c850ebd2-a54a-4186-aa74-59f18450e0e7 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603818806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown _en_cdc_prim.1603818806 |
| Directory | /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2527422164 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 60935554 ps |
| CPU time | 1.01 seconds |
| Started | Jul 18 05:40:30 PM PDT 24 |
| Finished | Jul 18 05:40:38 PM PDT 24 |
| Peak memory | 192140 kb |
| Host | smart-50711303-b5ec-47f4-aee9-2381528d2241 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2527422164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2527422164 |
| Directory | /workspace/45.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4269225798 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 115833990 ps |
| CPU time | 1.17 seconds |
| Started | Jul 18 05:40:35 PM PDT 24 |
| Finished | Jul 18 05:40:44 PM PDT 24 |
| Peak memory | 198492 kb |
| Host | smart-00fefd03-2db6-496e-8b59-3071159c4684 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269225798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown _en_cdc_prim.4269225798 |
| Directory | /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.423409581 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 64401737 ps |
| CPU time | 1.21 seconds |
| Started | Jul 18 05:40:28 PM PDT 24 |
| Finished | Jul 18 05:40:36 PM PDT 24 |
| Peak memory | 198568 kb |
| Host | smart-b7996a9a-e6c4-41f5-a0ae-1bcec677c695 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=423409581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.423409581 |
| Directory | /workspace/46.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2613438879 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 66049003 ps |
| CPU time | 1.19 seconds |
| Started | Jul 18 05:40:28 PM PDT 24 |
| Finished | Jul 18 05:40:36 PM PDT 24 |
| Peak memory | 192364 kb |
| Host | smart-5e76f95b-31be-450e-8995-2fac03141ec4 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613438879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown _en_cdc_prim.2613438879 |
| Directory | /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1544291622 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 191278251 ps |
| CPU time | 1.53 seconds |
| Started | Jul 18 05:40:35 PM PDT 24 |
| Finished | Jul 18 05:40:44 PM PDT 24 |
| Peak memory | 198580 kb |
| Host | smart-5f760b8f-f3c6-442e-ad3b-024c72bce242 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1544291622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1544291622 |
| Directory | /workspace/47.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.833492614 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 32059927 ps |
| CPU time | 1.02 seconds |
| Started | Jul 18 05:40:35 PM PDT 24 |
| Finished | Jul 18 05:40:43 PM PDT 24 |
| Peak memory | 192112 kb |
| Host | smart-4aded510-2bbf-49e8-9310-9134d8daa6ee |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833492614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.833492614 |
| Directory | /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.568622638 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 110316725 ps |
| CPU time | 0.98 seconds |
| Started | Jul 18 05:40:34 PM PDT 24 |
| Finished | Jul 18 05:40:43 PM PDT 24 |
| Peak memory | 197852 kb |
| Host | smart-b1f0f592-aae3-4d41-9c3b-2a49811158c6 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=568622638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.568622638 |
| Directory | /workspace/48.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3697701583 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 67999608 ps |
| CPU time | 0.99 seconds |
| Started | Jul 18 05:40:32 PM PDT 24 |
| Finished | Jul 18 05:40:42 PM PDT 24 |
| Peak memory | 192144 kb |
| Host | smart-1d3d50e3-de7d-44eb-8a90-78951f6e9f43 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697701583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown _en_cdc_prim.3697701583 |
| Directory | /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3789499732 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 107337015 ps |
| CPU time | 1.04 seconds |
| Started | Jul 18 05:40:34 PM PDT 24 |
| Finished | Jul 18 05:40:43 PM PDT 24 |
| Peak memory | 192176 kb |
| Host | smart-814913d9-5c24-4e92-bd3d-67a47e169e21 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3789499732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3789499732 |
| Directory | /workspace/49.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4165803931 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 282518077 ps |
| CPU time | 1.38 seconds |
| Started | Jul 18 05:40:33 PM PDT 24 |
| Finished | Jul 18 05:40:43 PM PDT 24 |
| Peak memory | 192144 kb |
| Host | smart-5f473aba-11f8-4293-b6a7-2e25f1dab1ec |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165803931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown _en_cdc_prim.4165803931 |
| Directory | /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1711081234 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 219276535 ps |
| CPU time | 1.01 seconds |
| Started | Jul 18 05:40:15 PM PDT 24 |
| Finished | Jul 18 05:40:25 PM PDT 24 |
| Peak memory | 192180 kb |
| Host | smart-13e47d8a-549d-4a4f-a4f0-77e1bdd98175 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1711081234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1711081234 |
| Directory | /workspace/5.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3043184196 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 52916054 ps |
| CPU time | 1.38 seconds |
| Started | Jul 18 05:40:13 PM PDT 24 |
| Finished | Jul 18 05:40:24 PM PDT 24 |
| Peak memory | 192196 kb |
| Host | smart-58cf1fa3-f73c-45de-b3d3-b4665ff05d47 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043184196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.3043184196 |
| Directory | /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2860242612 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 381264611 ps |
| CPU time | 1.08 seconds |
| Started | Jul 18 05:40:14 PM PDT 24 |
| Finished | Jul 18 05:40:24 PM PDT 24 |
| Peak memory | 197728 kb |
| Host | smart-ef4b0a1c-c054-46e5-a561-10452832c2eb |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2860242612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2860242612 |
| Directory | /workspace/6.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3005540871 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 369904042 ps |
| CPU time | 1.51 seconds |
| Started | Jul 18 05:40:13 PM PDT 24 |
| Finished | Jul 18 05:40:24 PM PDT 24 |
| Peak memory | 192112 kb |
| Host | smart-e8cfe0eb-1eec-4a67-83cf-49985b616fe4 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005540871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.3005540871 |
| Directory | /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2439746336 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 26737706 ps |
| CPU time | 0.84 seconds |
| Started | Jul 18 05:40:17 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 196556 kb |
| Host | smart-7fdd5f5f-3581-4be2-9ef8-8ca04eba3b48 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2439746336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2439746336 |
| Directory | /workspace/7.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4092290532 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 56799855 ps |
| CPU time | 1.18 seconds |
| Started | Jul 18 05:40:27 PM PDT 24 |
| Finished | Jul 18 05:40:35 PM PDT 24 |
| Peak memory | 192168 kb |
| Host | smart-f105fa12-cd23-428f-86bf-91aba7f18801 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092290532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.4092290532 |
| Directory | /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.576880273 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 139771634 ps |
| CPU time | 1.29 seconds |
| Started | Jul 18 05:40:17 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 192156 kb |
| Host | smart-d166c8ff-f4ef-4e6f-8552-47ecfd3f95e3 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=576880273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.576880273 |
| Directory | /workspace/8.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1990232730 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 133086643 ps |
| CPU time | 1.15 seconds |
| Started | Jul 18 05:40:27 PM PDT 24 |
| Finished | Jul 18 05:40:35 PM PDT 24 |
| Peak memory | 198576 kb |
| Host | smart-1dc59ad1-ba5a-421c-b074-55d43ba1b83f |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990232730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.1990232730 |
| Directory | /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1836248085 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 70677205 ps |
| CPU time | 1.18 seconds |
| Started | Jul 18 05:40:18 PM PDT 24 |
| Finished | Jul 18 05:40:29 PM PDT 24 |
| Peak memory | 198548 kb |
| Host | smart-08bd39c1-7e40-44f7-8e8c-e9751ef2be8d |
| User | root |
| Command | /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1836248085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1836248085 |
| Directory | /workspace/9.gpio_smoke_en_cdc_prim/latest |
| Test location | /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3058706175 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 266190248 ps |
| CPU time | 1.42 seconds |
| Started | Jul 18 05:40:17 PM PDT 24 |
| Finished | Jul 18 05:40:28 PM PDT 24 |
| Peak memory | 192168 kb |
| Host | smart-6a1cf4de-7ace-44e7-926d-afaf0b218e86 |
| User | root |
| Command | /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058706175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_ en_cdc_prim.3058706175 |
| Directory | /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |