Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14064972	1			T32	107550		T33	341		T1	29
all_values[1]	14064972	1			T32	107550		T33	341		T1	29
all_values[2]	14064972	1			T32	107550		T33	341		T1	29
all_values[3]	14064972	1			T32	107550		T33	341		T1	29
all_values[4]	14064972	1			T32	107550		T33	341		T1	29
all_values[5]	14064972	1			T32	107550		T33	341		T1	29
all_values[6]	14064972	1			T32	107550		T33	341		T1	29
all_values[7]	14064972	1			T32	107550		T33	341		T1	29
all_values[8]	14064972	1			T32	107550		T33	341		T1	29
all_values[9]	14064972	1			T32	107550		T33	341		T1	29
all_values[10]	14064972	1			T32	107550		T33	341		T1	29
all_values[11]	14064972	1			T32	107550		T33	341		T1	29
all_values[12]	14064972	1			T32	107550		T33	341		T1	29
all_values[13]	14064972	1			T32	107550		T33	341		T1	29
all_values[14]	14064972	1			T32	107550		T33	341		T1	29
all_values[15]	14064972	1			T32	107550		T33	341		T1	29
all_values[16]	14064972	1			T32	107550		T33	341		T1	29
all_values[17]	14064972	1			T32	107550		T33	341		T1	29
all_values[18]	14064972	1			T32	107550		T33	341		T1	29
all_values[19]	14064972	1			T32	107550		T33	341		T1	29
all_values[20]	14064972	1			T32	107550		T33	341		T1	29
all_values[21]	14064972	1			T32	107550		T33	341		T1	29
all_values[22]	14064972	1			T32	107550		T33	341		T1	29
all_values[23]	14064972	1			T32	107550		T33	341		T1	29
all_values[24]	14064972	1			T32	107550		T33	341		T1	29
all_values[25]	14064972	1			T32	107550		T33	341		T1	29
all_values[26]	14064972	1			T32	107550		T33	341		T1	29
all_values[27]	14064972	1			T32	107550		T33	341		T1	29
all_values[28]	14064972	1			T32	107550		T33	341		T1	29
all_values[29]	14064972	1			T32	107550		T33	341		T1	29
all_values[30]	14064972	1			T32	107550		T33	341		T1	29
all_values[31]	14064972	1			T32	107550		T33	341		T1	29

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

261775084

1

T32

193685

T33

10912

T1

758

auto[1]

188304020

1

T32

150474

T1

170

T11

130988

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109664417

1

T32

730461

T33

10912

T1

707

auto[1]

340414687

1

T32

271113

T1

221

T11

233591

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2848708	1			T32	17658		T33	341		T1	14
all_values[0]	auto[0]	auto[1]	5339440	1			T32	41706		T1	5		T11	37543
all_values[0]	auto[1]	auto[0]	570582	1			T32	4660		T1	5		T11	3711
all_values[0]	auto[1]	auto[1]	5306242	1			T32	43526		T1	5		T11	36229
all_values[1]	auto[0]	auto[0]	2847540	1			T32	17326		T33	341		T1	14
all_values[1]	auto[0]	auto[1]	5333252	1			T32	39894		T1	5		T11	35809
all_values[1]	auto[1]	auto[0]	577129	1			T32	5856		T1	5		T11	4076
all_values[1]	auto[1]	auto[1]	5307051	1			T32	44474		T1	5		T11	37831
all_values[2]	auto[0]	auto[0]	2852048	1			T32	18165		T33	341		T1	17
all_values[2]	auto[0]	auto[1]	5349086	1			T32	44276		T1	6		T11	35581
all_values[2]	auto[1]	auto[0]	569632	1			T32	5039		T1	2		T11	4305
all_values[2]	auto[1]	auto[1]	5294206	1			T32	40070		T1	4		T11	37403
all_values[3]	auto[0]	auto[0]	2847003	1			T32	17894		T33	341		T1	14
all_values[3]	auto[0]	auto[1]	5314755	1			T32	43199		T1	5		T11	36419
all_values[3]	auto[1]	auto[0]	581763	1			T32	4358		T1	5		T11	4478
all_values[3]	auto[1]	auto[1]	5321451	1			T32	42099		T1	5		T11	36464
all_values[4]	auto[0]	auto[0]	2854237	1			T32	17410		T33	341		T1	21
all_values[4]	auto[0]	auto[1]	5316530	1			T32	41979		T1	2		T11	38288
all_values[4]	auto[1]	auto[0]	571984	1			T32	5195		T1	2		T11	3785
all_values[4]	auto[1]	auto[1]	5322221	1			T32	42966		T1	4		T11	35787
all_values[5]	auto[0]	auto[0]	2857924	1			T32	17612		T33	341		T1	21
all_values[5]	auto[0]	auto[1]	5326907	1			T32	43495		T1	2		T11	36457
all_values[5]	auto[1]	auto[0]	575263	1			T32	4902		T1	6		T11	4438
all_values[5]	auto[1]	auto[1]	5304878	1			T32	41541		T11	36844		T12	8761
all_values[6]	auto[0]	auto[0]	2853825	1			T32	18217		T33	341		T1	23
all_values[6]	auto[0]	auto[1]	5286464	1			T32	42184		T1	6		T11	36333
all_values[6]	auto[1]	auto[0]	573246	1			T32	4619		T11	4427		T12	982
all_values[6]	auto[1]	auto[1]	5351437	1			T32	42530		T11	36546		T12	9353
all_values[7]	auto[0]	auto[0]	2857816	1			T32	18048		T33	341		T1	16
all_values[7]	auto[0]	auto[1]	5317036	1			T32	42524		T1	13		T11	36162
all_values[7]	auto[1]	auto[0]	564847	1			T32	4355		T11	5138		T12	1185
all_values[7]	auto[1]	auto[1]	5325273	1			T32	42623		T11	35879		T12	9366
all_values[8]	auto[0]	auto[0]	2851499	1			T32	18310		T33	341		T1	16
all_values[8]	auto[0]	auto[1]	5339728	1			T32	44402		T1	7		T11	36727
all_values[8]	auto[1]	auto[0]	572328	1			T32	4562		T1	6		T11	4856
all_values[8]	auto[1]	auto[1]	5301417	1			T32	40276		T11	35708		T12	8802
all_values[9]	auto[0]	auto[0]	2852038	1			T32	18091		T33	341		T1	14
all_values[9]	auto[0]	auto[1]	5327513	1			T32	42275		T1	5		T11	36167
all_values[9]	auto[1]	auto[0]	575608	1			T32	4782		T1	6		T11	4868
all_values[9]	auto[1]	auto[1]	5309813	1			T32	42402		T1	4		T11	36161
all_values[10]	auto[0]	auto[0]	2859983	1			T32	17465		T33	341		T1	20
all_values[10]	auto[0]	auto[1]	5347839	1			T32	43275		T1	3		T11	35428
all_values[10]	auto[1]	auto[0]	574738	1			T32	4495		T1	2		T11	4172
all_values[10]	auto[1]	auto[1]	5282412	1			T32	42315		T1	4		T11	37897
all_values[11]	auto[0]	auto[0]	2855937	1			T32	18078		T33	341		T1	18
all_values[11]	auto[0]	auto[1]	5322452	1			T32	42456		T1	7		T11	37008
all_values[11]	auto[1]	auto[0]	573944	1			T32	5116		T1	3		T11	4132
all_values[11]	auto[1]	auto[1]	5312639	1			T32	41900		T1	1		T11	35770
all_values[12]	auto[0]	auto[0]	2852266	1			T32	17542		T33	341		T1	17
all_values[12]	auto[0]	auto[1]	5317531	1			T32	43015		T1	8		T11	35309
all_values[12]	auto[1]	auto[0]	571861	1			T32	4858		T1	2		T11	5035
all_values[12]	auto[1]	auto[1]	5323314	1			T32	42135		T1	2		T11	37185
all_values[13]	auto[0]	auto[0]	2850182	1			T32	18394		T33	341		T1	16
all_values[13]	auto[0]	auto[1]	5303435	1			T32	41653		T1	7		T11	36206
all_values[13]	auto[1]	auto[0]	562367	1			T32	4949		T1	6		T11	4624
all_values[13]	auto[1]	auto[1]	5348988	1			T32	42554		T11	36496		T12	9602
all_values[14]	auto[0]	auto[0]	2853134	1			T32	17639		T33	341		T1	21
all_values[14]	auto[0]	auto[1]	5314890	1			T32	43654		T1	2		T11	36766
all_values[14]	auto[1]	auto[0]	569792	1			T32	5204		T1	6		T11	4244
all_values[14]	auto[1]	auto[1]	5327156	1			T32	41053		T11	35839		T12	9824
all_values[15]	auto[0]	auto[0]	2850615	1			T32	17697		T33	341		T1	18
all_values[15]	auto[0]	auto[1]	5351031	1			T32	42426		T1	5		T11	36256
all_values[15]	auto[1]	auto[0]	571598	1			T32	4874		T1	6		T11	4213
all_values[15]	auto[1]	auto[1]	5291728	1			T32	42553		T11	37267		T12	9176
all_values[16]	auto[0]	auto[0]	2850971	1			T32	18311		T33	341		T1	18
all_values[16]	auto[0]	auto[1]	5332379	1			T32	42366		T1	7		T11	35302
all_values[16]	auto[1]	auto[0]	577340	1			T32	4955		T1	2		T11	4052
all_values[16]	auto[1]	auto[1]	5304282	1			T32	41918		T1	2		T11	37705
all_values[17]	auto[0]	auto[0]	2855964	1			T32	17484		T33	341		T1	19
all_values[17]	auto[0]	auto[1]	5323344	1			T32	43560		T11	36084		T12	10129
all_values[17]	auto[1]	auto[0]	579735	1			T32	5154		T1	8		T11	4643
all_values[17]	auto[1]	auto[1]	5305929	1			T32	41352		T1	2		T11	37251
all_values[18]	auto[0]	auto[0]	2846838	1			T32	18082		T33	341		T1	22
all_values[18]	auto[0]	auto[1]	5323051	1			T32	43338		T1	1		T11	36281
all_values[18]	auto[1]	auto[0]	572971	1			T32	5144		T1	6		T11	5285
all_values[18]	auto[1]	auto[1]	5322112	1			T32	40986		T11	36205		T12	9131
all_values[19]	auto[0]	auto[0]	2847490	1			T32	18238		T33	341		T1	19
all_values[19]	auto[0]	auto[1]	5286079	1			T32	44615		T1	4		T11	38146
all_values[19]	auto[1]	auto[0]	578396	1			T32	4504		T1	3		T11	4549
all_values[19]	auto[1]	auto[1]	5353007	1			T32	40193		T1	3		T11	34881
all_values[20]	auto[0]	auto[0]	2860494	1			T32	18972		T33	341		T1	20
all_values[20]	auto[0]	auto[1]	5310546	1			T32	43067		T1	5		T11	37004
all_values[20]	auto[1]	auto[0]	570927	1			T32	4600		T1	2		T11	4265
all_values[20]	auto[1]	auto[1]	5323005	1			T32	40911		T1	2		T11	36198
all_values[21]	auto[0]	auto[0]	2864963	1			T32	17992		T33	341		T1	16
all_values[21]	auto[0]	auto[1]	5324173	1			T32	41415		T1	3		T11	37134
all_values[21]	auto[1]	auto[0]	576267	1			T32	5003		T1	5		T11	4264
all_values[21]	auto[1]	auto[1]	5299569	1			T32	43140		T1	5		T11	36381
all_values[22]	auto[0]	auto[0]	2848515	1			T32	18303		T33	341		T1	20
all_values[22]	auto[0]	auto[1]	5338683	1			T32	42307		T1	9		T11	36458
all_values[22]	auto[1]	auto[0]	573412	1			T32	5100		T11	4712		T12	1315
all_values[22]	auto[1]	auto[1]	5304362	1			T32	41840		T11	36685		T12	9538
all_values[23]	auto[0]	auto[0]	2848948	1			T32	17707		T33	341		T1	14
all_values[23]	auto[0]	auto[1]	5347071	1			T32	43073		T1	9		T11	37342
all_values[23]	auto[1]	auto[0]	570678	1			T32	5049		T1	6		T11	4874
all_values[23]	auto[1]	auto[1]	5298275	1			T32	41721		T11	35568		T12	9027
all_values[24]	auto[0]	auto[0]	2852229	1			T32	17602		T33	341		T1	16
all_values[24]	auto[0]	auto[1]	5336370	1			T32	41411		T1	3		T11	37612
all_values[24]	auto[1]	auto[0]	566519	1			T32	5151		T1	6		T11	4245
all_values[24]	auto[1]	auto[1]	5309854	1			T32	43386		T1	4		T11	35880
all_values[25]	auto[0]	auto[0]	2846883	1			T32	17919		T33	341		T1	20
all_values[25]	auto[0]	auto[1]	5315648	1			T32	42323		T1	9		T11	36794
all_values[25]	auto[1]	auto[0]	576939	1			T32	4460		T11	5043		T12	1348
all_values[25]	auto[1]	auto[1]	5325502	1			T32	42848		T11	35538		T12	9042
all_values[26]	auto[0]	auto[0]	2856472	1			T32	17867		T33	341		T1	17
all_values[26]	auto[0]	auto[1]	5325472	1			T32	40829		T1	8		T11	35167
all_values[26]	auto[1]	auto[0]	575924	1			T32	4597		T1	4		T11	4921
all_values[26]	auto[1]	auto[1]	5307104	1			T32	44257		T11	37375		T12	9783
all_values[27]	auto[0]	auto[0]	2854563	1			T32	18059		T33	341		T1	27
all_values[27]	auto[0]	auto[1]	5364175	1			T32	42284		T1	2		T11	36965
all_values[27]	auto[1]	auto[0]	576810	1			T32	4458		T11	4356		T12	988
all_values[27]	auto[1]	auto[1]	5269424	1			T32	42749		T11	36398		T12	8937
all_values[28]	auto[0]	auto[0]	2860484	1			T32	17905		T33	341		T1	25
all_values[28]	auto[0]	auto[1]	5350035	1			T32	40889		T1	4		T11	38287
all_values[28]	auto[1]	auto[0]	580286	1			T32	5221		T11	4610		T12	1520
all_values[28]	auto[1]	auto[1]	5274167	1			T32	43535		T11	34394		T12	9420
all_values[29]	auto[0]	auto[0]	2853287	1			T32	18073		T33	341		T1	17
all_values[29]	auto[0]	auto[1]	5319797	1			T32	43964		T1	8		T11	36132
all_values[29]	auto[1]	auto[0]	587492	1			T32	5313		T1	2		T11	4543
all_values[29]	auto[1]	auto[1]	5304396	1			T32	40200		T1	2		T11	36682
all_values[30]	auto[0]	auto[0]	2853271	1			T32	17818		T33	341		T1	26
all_values[30]	auto[0]	auto[1]	5325645	1			T32	43324		T1	3		T11	36598
all_values[30]	auto[1]	auto[0]	579855	1			T32	5340		T11	4351		T12	1150
all_values[30]	auto[1]	auto[1]	5306201	1			T32	41068		T11	36613		T12	9405
all_values[31]	auto[0]	auto[0]	2853594	1			T32	17861		T33	341		T1	18
all_values[31]	auto[0]	auto[1]	5345006	1			T32	41937		T1	1		T11	35528
all_values[31]	auto[1]	auto[0]	564463	1			T32	4849		T1	7		T11	4050
all_values[31]	auto[1]	auto[1]	5301909	1			T32	42903		T1	3		T11	37557