Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2035924 |
1 |
|
|
T32 |
17655 |
|
T33 |
110 |
|
T1 |
15 |
| auto[1] |
1776293 |
1 |
|
|
T32 |
16077 |
|
T33 |
102 |
|
T1 |
9 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2400985 |
1 |
|
|
T32 |
21600 |
|
T33 |
89 |
|
T1 |
22 |
| auto[1] |
1411232 |
1 |
|
|
T32 |
12132 |
|
T33 |
123 |
|
T1 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1324117 |
1 |
|
|
T32 |
11643 |
|
T33 |
43 |
|
T1 |
15 |
| auto[0] |
auto[1] |
711807 |
1 |
|
|
T32 |
6012 |
|
T33 |
67 |
|
T11 |
5433 |
| auto[1] |
auto[0] |
1076868 |
1 |
|
|
T32 |
9957 |
|
T33 |
46 |
|
T1 |
7 |
| auto[1] |
auto[1] |
699425 |
1 |
|
|
T32 |
6120 |
|
T33 |
56 |
|
T1 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2036141 |
1 |
|
|
T32 |
17481 |
|
T33 |
102 |
|
T1 |
15 |
| auto[1] |
1776076 |
1 |
|
|
T32 |
16251 |
|
T33 |
110 |
|
T1 |
9 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2399464 |
1 |
|
|
T32 |
21801 |
|
T33 |
108 |
|
T1 |
20 |
| auto[1] |
1412753 |
1 |
|
|
T32 |
11931 |
|
T33 |
104 |
|
T1 |
4 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1324608 |
1 |
|
|
T32 |
11488 |
|
T33 |
49 |
|
T1 |
15 |
| auto[0] |
auto[1] |
711533 |
1 |
|
|
T32 |
5993 |
|
T33 |
53 |
|
T11 |
5749 |
| auto[1] |
auto[0] |
1074856 |
1 |
|
|
T32 |
10313 |
|
T33 |
59 |
|
T1 |
5 |
| auto[1] |
auto[1] |
701220 |
1 |
|
|
T32 |
5938 |
|
T33 |
51 |
|
T1 |
4 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2028532 |
1 |
|
|
T32 |
17948 |
|
T33 |
88 |
|
T1 |
15 |
| auto[1] |
1783685 |
1 |
|
|
T32 |
15784 |
|
T33 |
124 |
|
T1 |
9 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2402483 |
1 |
|
|
T32 |
21530 |
|
T33 |
102 |
|
T1 |
19 |
| auto[1] |
1409734 |
1 |
|
|
T32 |
12202 |
|
T33 |
110 |
|
T1 |
5 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1319830 |
1 |
|
|
T32 |
11698 |
|
T33 |
35 |
|
T1 |
12 |
| auto[0] |
auto[1] |
708702 |
1 |
|
|
T32 |
6250 |
|
T33 |
53 |
|
T1 |
3 |
| auto[1] |
auto[0] |
1082653 |
1 |
|
|
T32 |
9832 |
|
T33 |
67 |
|
T1 |
7 |
| auto[1] |
auto[1] |
701032 |
1 |
|
|
T32 |
5952 |
|
T33 |
57 |
|
T1 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2033566 |
1 |
|
|
T32 |
18040 |
|
T33 |
118 |
|
T1 |
11 |
| auto[1] |
1778651 |
1 |
|
|
T32 |
15692 |
|
T33 |
94 |
|
T1 |
13 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2402967 |
1 |
|
|
T32 |
21321 |
|
T33 |
121 |
|
T1 |
19 |
| auto[1] |
1409250 |
1 |
|
|
T32 |
12411 |
|
T33 |
91 |
|
T1 |
5 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1324188 |
1 |
|
|
T32 |
11731 |
|
T33 |
72 |
|
T1 |
8 |
| auto[0] |
auto[1] |
709378 |
1 |
|
|
T32 |
6309 |
|
T33 |
46 |
|
T1 |
3 |
| auto[1] |
auto[0] |
1078779 |
1 |
|
|
T32 |
9590 |
|
T33 |
49 |
|
T1 |
11 |
| auto[1] |
auto[1] |
699872 |
1 |
|
|
T32 |
6102 |
|
T33 |
45 |
|
T1 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2031226 |
1 |
|
|
T32 |
17491 |
|
T33 |
96 |
|
T1 |
20 |
| auto[1] |
1780991 |
1 |
|
|
T32 |
16241 |
|
T33 |
116 |
|
T1 |
4 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2401815 |
1 |
|
|
T32 |
21553 |
|
T33 |
100 |
|
T1 |
24 |
| auto[1] |
1410402 |
1 |
|
|
T32 |
12179 |
|
T33 |
112 |
|
T11 |
11018 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1322179 |
1 |
|
|
T32 |
11477 |
|
T33 |
46 |
|
T1 |
20 |
| auto[0] |
auto[1] |
709047 |
1 |
|
|
T32 |
6014 |
|
T33 |
50 |
|
T11 |
5587 |
| auto[1] |
auto[0] |
1079636 |
1 |
|
|
T32 |
10076 |
|
T33 |
54 |
|
T1 |
4 |
| auto[1] |
auto[1] |
701355 |
1 |
|
|
T32 |
6165 |
|
T33 |
62 |
|
T11 |
5431 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2035375 |
1 |
|
|
T32 |
18023 |
|
T33 |
114 |
|
T1 |
11 |
| auto[1] |
1776842 |
1 |
|
|
T32 |
15709 |
|
T33 |
98 |
|
T1 |
13 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2402885 |
1 |
|
|
T32 |
21481 |
|
T33 |
102 |
|
T1 |
22 |
| auto[1] |
1409332 |
1 |
|
|
T32 |
12251 |
|
T33 |
110 |
|
T1 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1325983 |
1 |
|
|
T32 |
11763 |
|
T33 |
52 |
|
T1 |
11 |
| auto[0] |
auto[1] |
709392 |
1 |
|
|
T32 |
6260 |
|
T33 |
62 |
|
T11 |
5686 |
| auto[1] |
auto[0] |
1076902 |
1 |
|
|
T32 |
9718 |
|
T33 |
50 |
|
T1 |
11 |
| auto[1] |
auto[1] |
699940 |
1 |
|
|
T32 |
5991 |
|
T33 |
48 |
|
T1 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2037822 |
1 |
|
|
T32 |
18103 |
|
T33 |
98 |
|
T1 |
11 |
| auto[1] |
1774395 |
1 |
|
|
T32 |
15629 |
|
T33 |
114 |
|
T1 |
13 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2405702 |
1 |
|
|
T32 |
21392 |
|
T33 |
112 |
|
T1 |
20 |
| auto[1] |
1406515 |
1 |
|
|
T32 |
12340 |
|
T33 |
100 |
|
T1 |
4 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1328926 |
1 |
|
|
T32 |
11832 |
|
T33 |
51 |
|
T1 |
11 |
| auto[0] |
auto[1] |
708896 |
1 |
|
|
T32 |
6271 |
|
T33 |
47 |
|
T11 |
5458 |
| auto[1] |
auto[0] |
1076776 |
1 |
|
|
T32 |
9560 |
|
T33 |
61 |
|
T1 |
9 |
| auto[1] |
auto[1] |
697619 |
1 |
|
|
T32 |
6069 |
|
T33 |
53 |
|
T1 |
4 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2026523 |
1 |
|
|
T32 |
17503 |
|
T33 |
96 |
|
T1 |
20 |
| auto[1] |
1785694 |
1 |
|
|
T32 |
16229 |
|
T33 |
116 |
|
T1 |
4 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2402399 |
1 |
|
|
T32 |
21621 |
|
T33 |
108 |
|
T1 |
24 |
| auto[1] |
1409818 |
1 |
|
|
T32 |
12111 |
|
T33 |
104 |
|
T11 |
11260 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1321154 |
1 |
|
|
T32 |
11463 |
|
T33 |
49 |
|
T1 |
20 |
| auto[0] |
auto[1] |
705369 |
1 |
|
|
T32 |
6040 |
|
T33 |
47 |
|
T11 |
5573 |
| auto[1] |
auto[0] |
1081245 |
1 |
|
|
T32 |
10158 |
|
T33 |
59 |
|
T1 |
4 |
| auto[1] |
auto[1] |
704449 |
1 |
|
|
T32 |
6071 |
|
T33 |
57 |
|
T11 |
5687 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2036781 |
1 |
|
|
T32 |
18036 |
|
T33 |
108 |
|
T1 |
19 |
| auto[1] |
1775436 |
1 |
|
|
T32 |
15696 |
|
T33 |
104 |
|
T1 |
5 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2410028 |
1 |
|
|
T32 |
21760 |
|
T33 |
99 |
|
T1 |
22 |
| auto[1] |
1402189 |
1 |
|
|
T32 |
11972 |
|
T33 |
113 |
|
T1 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1331407 |
1 |
|
|
T32 |
11947 |
|
T33 |
42 |
|
T1 |
19 |
| auto[0] |
auto[1] |
705374 |
1 |
|
|
T32 |
6089 |
|
T33 |
66 |
|
T11 |
5535 |
| auto[1] |
auto[0] |
1078621 |
1 |
|
|
T32 |
9813 |
|
T33 |
57 |
|
T1 |
3 |
| auto[1] |
auto[1] |
696815 |
1 |
|
|
T32 |
5883 |
|
T33 |
47 |
|
T1 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2034356 |
1 |
|
|
T32 |
17789 |
|
T33 |
116 |
|
T1 |
13 |
| auto[1] |
1777861 |
1 |
|
|
T32 |
15943 |
|
T33 |
96 |
|
T1 |
11 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2410808 |
1 |
|
|
T32 |
21763 |
|
T33 |
119 |
|
T1 |
21 |
| auto[1] |
1401409 |
1 |
|
|
T32 |
11969 |
|
T33 |
93 |
|
T1 |
3 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1329029 |
1 |
|
|
T32 |
11784 |
|
T33 |
66 |
|
T1 |
13 |
| auto[0] |
auto[1] |
705327 |
1 |
|
|
T32 |
6005 |
|
T33 |
50 |
|
T11 |
5787 |
| auto[1] |
auto[0] |
1081779 |
1 |
|
|
T32 |
9979 |
|
T33 |
53 |
|
T1 |
8 |
| auto[1] |
auto[1] |
696082 |
1 |
|
|
T32 |
5964 |
|
T33 |
43 |
|
T1 |
3 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2033622 |
1 |
|
|
T32 |
17408 |
|
T33 |
110 |
|
T1 |
19 |
| auto[1] |
1778595 |
1 |
|
|
T32 |
16324 |
|
T33 |
102 |
|
T1 |
5 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2408373 |
1 |
|
|
T32 |
21865 |
|
T33 |
89 |
|
T1 |
22 |
| auto[1] |
1403844 |
1 |
|
|
T32 |
11867 |
|
T33 |
123 |
|
T1 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1327718 |
1 |
|
|
T32 |
11535 |
|
T33 |
41 |
|
T1 |
19 |
| auto[0] |
auto[1] |
705904 |
1 |
|
|
T32 |
5873 |
|
T33 |
69 |
|
T11 |
5764 |
| auto[1] |
auto[0] |
1080655 |
1 |
|
|
T32 |
10330 |
|
T33 |
48 |
|
T1 |
3 |
| auto[1] |
auto[1] |
697940 |
1 |
|
|
T32 |
5994 |
|
T33 |
54 |
|
T1 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2039439 |
1 |
|
|
T32 |
18009 |
|
T33 |
106 |
|
T1 |
17 |
| auto[1] |
1772778 |
1 |
|
|
T32 |
15723 |
|
T33 |
106 |
|
T1 |
7 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2408670 |
1 |
|
|
T32 |
21691 |
|
T33 |
110 |
|
T1 |
22 |
| auto[1] |
1403547 |
1 |
|
|
T32 |
12041 |
|
T33 |
102 |
|
T1 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1331501 |
1 |
|
|
T32 |
11915 |
|
T33 |
59 |
|
T1 |
17 |
| auto[0] |
auto[1] |
707938 |
1 |
|
|
T32 |
6094 |
|
T33 |
47 |
|
T11 |
5650 |
| auto[1] |
auto[0] |
1077169 |
1 |
|
|
T32 |
9776 |
|
T33 |
51 |
|
T1 |
5 |
| auto[1] |
auto[1] |
695609 |
1 |
|
|
T32 |
5947 |
|
T33 |
55 |
|
T1 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2035428 |
1 |
|
|
T32 |
17904 |
|
T33 |
114 |
|
T1 |
15 |
| auto[1] |
1776789 |
1 |
|
|
T32 |
15828 |
|
T33 |
98 |
|
T1 |
9 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2403553 |
1 |
|
|
T32 |
21078 |
|
T33 |
99 |
|
T1 |
22 |
| auto[1] |
1408664 |
1 |
|
|
T32 |
12654 |
|
T33 |
113 |
|
T1 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1326774 |
1 |
|
|
T32 |
11406 |
|
T33 |
55 |
|
T1 |
15 |
| auto[0] |
auto[1] |
708654 |
1 |
|
|
T32 |
6498 |
|
T33 |
59 |
|
T11 |
5731 |
| auto[1] |
auto[0] |
1076779 |
1 |
|
|
T32 |
9672 |
|
T33 |
44 |
|
T1 |
7 |
| auto[1] |
auto[1] |
700010 |
1 |
|
|
T32 |
6156 |
|
T33 |
54 |
|
T1 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2033646 |
1 |
|
|
T32 |
17531 |
|
T33 |
108 |
|
T1 |
23 |
| auto[1] |
1778571 |
1 |
|
|
T32 |
16201 |
|
T33 |
104 |
|
T1 |
1 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2412332 |
1 |
|
|
T32 |
21757 |
|
T33 |
112 |
|
T1 |
24 |
| auto[1] |
1399885 |
1 |
|
|
T32 |
11975 |
|
T33 |
100 |
|
T11 |
11159 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1329494 |
1 |
|
|
T32 |
11540 |
|
T33 |
61 |
|
T1 |
23 |
| auto[0] |
auto[1] |
704152 |
1 |
|
|
T32 |
5991 |
|
T33 |
47 |
|
T11 |
5655 |
| auto[1] |
auto[0] |
1082838 |
1 |
|
|
T32 |
10217 |
|
T33 |
51 |
|
T1 |
1 |
| auto[1] |
auto[1] |
695733 |
1 |
|
|
T32 |
5984 |
|
T33 |
53 |
|
T11 |
5504 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2036307 |
1 |
|
|
T32 |
17923 |
|
T33 |
88 |
|
T1 |
22 |
| auto[1] |
1775910 |
1 |
|
|
T32 |
15809 |
|
T33 |
124 |
|
T1 |
2 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2407655 |
1 |
|
|
T32 |
21778 |
|
T33 |
115 |
|
T1 |
21 |
| auto[1] |
1404562 |
1 |
|
|
T32 |
11954 |
|
T33 |
97 |
|
T1 |
3 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1329879 |
1 |
|
|
T32 |
11811 |
|
T33 |
45 |
|
T1 |
19 |
| auto[0] |
auto[1] |
706428 |
1 |
|
|
T32 |
6112 |
|
T33 |
43 |
|
T1 |
3 |
| auto[1] |
auto[0] |
1077776 |
1 |
|
|
T32 |
9967 |
|
T33 |
70 |
|
T1 |
2 |
| auto[1] |
auto[1] |
698134 |
1 |
|
|
T32 |
5842 |
|
T33 |
54 |
|
T11 |
5367 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2035380 |
1 |
|
|
T32 |
17751 |
|
T33 |
120 |
|
T1 |
18 |
| auto[1] |
1776837 |
1 |
|
|
T32 |
15981 |
|
T33 |
92 |
|
T1 |
6 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2410206 |
1 |
|
|
T32 |
21629 |
|
T33 |
121 |
|
T1 |
22 |
| auto[1] |
1402011 |
1 |
|
|
T32 |
12103 |
|
T33 |
91 |
|
T1 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1328957 |
1 |
|
|
T32 |
11690 |
|
T33 |
70 |
|
T1 |
18 |
| auto[0] |
auto[1] |
706423 |
1 |
|
|
T32 |
6061 |
|
T33 |
50 |
|
T11 |
5725 |
| auto[1] |
auto[0] |
1081249 |
1 |
|
|
T32 |
9939 |
|
T33 |
51 |
|
T1 |
4 |
| auto[1] |
auto[1] |
695588 |
1 |
|
|
T32 |
6042 |
|
T33 |
41 |
|
T1 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2037378 |
1 |
|
|
T32 |
17471 |
|
T33 |
104 |
|
T1 |
21 |
| auto[1] |
1774839 |
1 |
|
|
T32 |
16261 |
|
T33 |
108 |
|
T1 |
3 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2412909 |
1 |
|
|
T32 |
21871 |
|
T33 |
106 |
|
T1 |
23 |
| auto[1] |
1399308 |
1 |
|
|
T32 |
11861 |
|
T33 |
106 |
|
T1 |
1 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1332122 |
1 |
|
|
T32 |
11553 |
|
T33 |
55 |
|
T1 |
20 |
| auto[0] |
auto[1] |
705256 |
1 |
|
|
T32 |
5918 |
|
T33 |
49 |
|
T1 |
1 |
| auto[1] |
auto[0] |
1080787 |
1 |
|
|
T32 |
10318 |
|
T33 |
51 |
|
T1 |
3 |
| auto[1] |
auto[1] |
694052 |
1 |
|
|
T32 |
5943 |
|
T33 |
57 |
|
T11 |
5590 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2036952 |
1 |
|
|
T32 |
18003 |
|
T33 |
116 |
|
T1 |
11 |
| auto[1] |
1775265 |
1 |
|
|
T32 |
15729 |
|
T33 |
96 |
|
T1 |
13 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2407125 |
1 |
|
|
T32 |
21627 |
|
T33 |
98 |
|
T1 |
22 |
| auto[1] |
1405092 |
1 |
|
|
T32 |
12105 |
|
T33 |
114 |
|
T1 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1330231 |
1 |
|
|
T32 |
11911 |
|
T33 |
55 |
|
T1 |
11 |
| auto[0] |
auto[1] |
706721 |
1 |
|
|
T32 |
6092 |
|
T33 |
61 |
|
T11 |
5844 |
| auto[1] |
auto[0] |
1076894 |
1 |
|
|
T32 |
9716 |
|
T33 |
43 |
|
T1 |
11 |
| auto[1] |
auto[1] |
698371 |
1 |
|
|
T32 |
6013 |
|
T33 |
53 |
|
T1 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2033229 |
1 |
|
|
T32 |
17596 |
|
T33 |
102 |
|
T1 |
24 |
| auto[1] |
1778988 |
1 |
|
|
T32 |
16136 |
|
T33 |
110 |
|
T11 |
14327 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2408122 |
1 |
|
|
T32 |
21798 |
|
T33 |
127 |
|
T1 |
24 |
| auto[1] |
1404095 |
1 |
|
|
T32 |
11934 |
|
T33 |
85 |
|
T11 |
10828 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1326534 |
1 |
|
|
T32 |
11786 |
|
T33 |
65 |
|
T1 |
24 |
| auto[0] |
auto[1] |
706695 |
1 |
|
|
T32 |
5810 |
|
T33 |
37 |
|
T11 |
5436 |
| auto[1] |
auto[0] |
1081588 |
1 |
|
|
T32 |
10012 |
|
T33 |
62 |
|
T11 |
8935 |
| auto[1] |
auto[1] |
697400 |
1 |
|
|
T32 |
6124 |
|
T33 |
48 |
|
T11 |
5392 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2032709 |
1 |
|
|
T32 |
17982 |
|
T33 |
94 |
|
T1 |
24 |
| auto[1] |
1779508 |
1 |
|
|
T32 |
15750 |
|
T33 |
118 |
|
T11 |
14084 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2405151 |
1 |
|
|
T32 |
21695 |
|
T33 |
118 |
|
T1 |
21 |
| auto[1] |
1407066 |
1 |
|
|
T32 |
12037 |
|
T33 |
94 |
|
T1 |
3 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1324461 |
1 |
|
|
T32 |
11889 |
|
T33 |
45 |
|
T1 |
21 |
| auto[0] |
auto[1] |
708248 |
1 |
|
|
T32 |
6093 |
|
T33 |
49 |
|
T1 |
3 |
| auto[1] |
auto[0] |
1080690 |
1 |
|
|
T32 |
9806 |
|
T33 |
73 |
|
T11 |
8482 |
| auto[1] |
auto[1] |
698818 |
1 |
|
|
T32 |
5944 |
|
T33 |
45 |
|
T11 |
5602 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2033037 |
1 |
|
|
T32 |
17613 |
|
T33 |
78 |
|
T1 |
11 |
| auto[1] |
1779180 |
1 |
|
|
T32 |
16119 |
|
T33 |
134 |
|
T1 |
13 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2410643 |
1 |
|
|
T32 |
21788 |
|
T33 |
121 |
|
T1 |
22 |
| auto[1] |
1401574 |
1 |
|
|
T32 |
11944 |
|
T33 |
91 |
|
T1 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1327652 |
1 |
|
|
T32 |
11757 |
|
T33 |
39 |
|
T1 |
11 |
| auto[0] |
auto[1] |
705385 |
1 |
|
|
T32 |
5856 |
|
T33 |
39 |
|
T11 |
5722 |
| auto[1] |
auto[0] |
1082991 |
1 |
|
|
T32 |
10031 |
|
T33 |
82 |
|
T1 |
11 |
| auto[1] |
auto[1] |
696189 |
1 |
|
|
T32 |
6088 |
|
T33 |
52 |
|
T1 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2037112 |
1 |
|
|
T32 |
17779 |
|
T33 |
90 |
|
T1 |
20 |
| auto[1] |
1775105 |
1 |
|
|
T32 |
15953 |
|
T33 |
122 |
|
T1 |
4 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2408955 |
1 |
|
|
T32 |
21755 |
|
T33 |
117 |
|
T1 |
23 |
| auto[1] |
1403262 |
1 |
|
|
T32 |
11977 |
|
T33 |
95 |
|
T1 |
1 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1330411 |
1 |
|
|
T32 |
11805 |
|
T33 |
42 |
|
T1 |
20 |
| auto[0] |
auto[1] |
706701 |
1 |
|
|
T32 |
5974 |
|
T33 |
48 |
|
T11 |
5514 |
| auto[1] |
auto[0] |
1078544 |
1 |
|
|
T32 |
9950 |
|
T33 |
75 |
|
T1 |
3 |
| auto[1] |
auto[1] |
696561 |
1 |
|
|
T32 |
6003 |
|
T33 |
47 |
|
T1 |
1 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2037465 |
1 |
|
|
T32 |
17770 |
|
T33 |
112 |
|
T1 |
19 |
| auto[1] |
1774752 |
1 |
|
|
T32 |
15962 |
|
T33 |
100 |
|
T1 |
5 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2408573 |
1 |
|
|
T32 |
21732 |
|
T33 |
108 |
|
T1 |
22 |
| auto[1] |
1403644 |
1 |
|
|
T32 |
12000 |
|
T33 |
104 |
|
T1 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1330808 |
1 |
|
|
T32 |
11759 |
|
T33 |
53 |
|
T1 |
19 |
| auto[0] |
auto[1] |
706657 |
1 |
|
|
T32 |
6011 |
|
T33 |
59 |
|
T11 |
5616 |
| auto[1] |
auto[0] |
1077765 |
1 |
|
|
T32 |
9973 |
|
T33 |
55 |
|
T1 |
3 |
| auto[1] |
auto[1] |
696987 |
1 |
|
|
T32 |
5989 |
|
T33 |
45 |
|
T1 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2037708 |
1 |
|
|
T32 |
17836 |
|
T33 |
98 |
|
T1 |
15 |
| auto[1] |
1774509 |
1 |
|
|
T32 |
15896 |
|
T33 |
114 |
|
T1 |
9 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2402388 |
1 |
|
|
T32 |
21751 |
|
T33 |
99 |
|
T1 |
22 |
| auto[1] |
1409829 |
1 |
|
|
T32 |
11981 |
|
T33 |
113 |
|
T1 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1325316 |
1 |
|
|
T32 |
11788 |
|
T33 |
48 |
|
T1 |
15 |
| auto[0] |
auto[1] |
712392 |
1 |
|
|
T32 |
6048 |
|
T33 |
50 |
|
T11 |
5838 |
| auto[1] |
auto[0] |
1077072 |
1 |
|
|
T32 |
9963 |
|
T33 |
51 |
|
T1 |
7 |
| auto[1] |
auto[1] |
697437 |
1 |
|
|
T32 |
5933 |
|
T33 |
63 |
|
T1 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2034619 |
1 |
|
|
T32 |
17825 |
|
T33 |
114 |
|
T1 |
15 |
| auto[1] |
1777598 |
1 |
|
|
T32 |
15907 |
|
T33 |
98 |
|
T1 |
9 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2409527 |
1 |
|
|
T32 |
21572 |
|
T33 |
112 |
|
T1 |
20 |
| auto[1] |
1402690 |
1 |
|
|
T32 |
12160 |
|
T33 |
100 |
|
T1 |
4 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1329096 |
1 |
|
|
T32 |
11748 |
|
T33 |
59 |
|
T1 |
13 |
| auto[0] |
auto[1] |
705523 |
1 |
|
|
T32 |
6077 |
|
T33 |
55 |
|
T1 |
2 |
| auto[1] |
auto[0] |
1080431 |
1 |
|
|
T32 |
9824 |
|
T33 |
53 |
|
T1 |
7 |
| auto[1] |
auto[1] |
697167 |
1 |
|
|
T32 |
6083 |
|
T33 |
45 |
|
T1 |
2 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2038035 |
1 |
|
|
T32 |
17414 |
|
T33 |
98 |
|
T1 |
22 |
| auto[1] |
1774182 |
1 |
|
|
T32 |
16318 |
|
T33 |
114 |
|
T1 |
2 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2405719 |
1 |
|
|
T32 |
21498 |
|
T33 |
110 |
|
T1 |
21 |
| auto[1] |
1406498 |
1 |
|
|
T32 |
12234 |
|
T33 |
102 |
|
T1 |
3 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1330111 |
1 |
|
|
T32 |
11377 |
|
T33 |
54 |
|
T1 |
19 |
| auto[0] |
auto[1] |
707924 |
1 |
|
|
T32 |
6037 |
|
T33 |
44 |
|
T1 |
3 |
| auto[1] |
auto[0] |
1075608 |
1 |
|
|
T32 |
10121 |
|
T33 |
56 |
|
T1 |
2 |
| auto[1] |
auto[1] |
698574 |
1 |
|
|
T32 |
6197 |
|
T33 |
58 |
|
T11 |
5371 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2035350 |
1 |
|
|
T32 |
17239 |
|
T33 |
102 |
|
T1 |
24 |
| auto[1] |
1776867 |
1 |
|
|
T32 |
16493 |
|
T33 |
110 |
|
T11 |
14282 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2401084 |
1 |
|
|
T32 |
21550 |
|
T33 |
96 |
|
T1 |
24 |
| auto[1] |
1411133 |
1 |
|
|
T32 |
12182 |
|
T33 |
116 |
|
T11 |
10970 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1324681 |
1 |
|
|
T32 |
11314 |
|
T33 |
38 |
|
T1 |
24 |
| auto[0] |
auto[1] |
710669 |
1 |
|
|
T32 |
5925 |
|
T33 |
64 |
|
T11 |
5463 |
| auto[1] |
auto[0] |
1076403 |
1 |
|
|
T32 |
10236 |
|
T33 |
58 |
|
T11 |
8775 |
| auto[1] |
auto[1] |
700464 |
1 |
|
|
T32 |
6257 |
|
T33 |
52 |
|
T11 |
5507 |