Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4175039	1			T32	36525		T33	1		T1	15
all_pins[1]	4175039	1			T32	36525		T33	1		T1	15
all_pins[2]	4175039	1			T32	36525		T33	1		T1	15
all_pins[3]	4175039	1			T32	36525		T33	1		T1	15
all_pins[4]	4175039	1			T32	36525		T33	1		T1	15
all_pins[5]	4175039	1			T32	36525		T33	1		T1	15
all_pins[6]	4175039	1			T32	36525		T33	1		T1	15
all_pins[7]	4175039	1			T32	36525		T33	1		T1	15
all_pins[8]	4175039	1			T32	36525		T33	1		T1	15
all_pins[9]	4175039	1			T32	36525		T33	1		T1	15
all_pins[10]	4175039	1			T32	36525		T33	1		T1	15
all_pins[11]	4175039	1			T32	36525		T33	1		T1	15
all_pins[12]	4175039	1			T32	36525		T33	1		T1	15
all_pins[13]	4175039	1			T32	36525		T33	1		T1	15
all_pins[14]	4175039	1			T32	36525		T33	1		T1	15
all_pins[15]	4175039	1			T32	36525		T33	1		T1	15
all_pins[16]	4175039	1			T32	36525		T33	1		T1	15
all_pins[17]	4175039	1			T32	36525		T33	1		T1	15
all_pins[18]	4175039	1			T32	36525		T33	1		T1	15
all_pins[19]	4175039	1			T32	36525		T33	1		T1	15
all_pins[20]	4175039	1			T32	36525		T33	1		T1	15
all_pins[21]	4175039	1			T32	36525		T33	1		T1	15
all_pins[22]	4175039	1			T32	36525		T33	1		T1	15
all_pins[23]	4175039	1			T32	36525		T33	1		T1	15
all_pins[24]	4175039	1			T32	36525		T33	1		T1	15
all_pins[25]	4175039	1			T32	36525		T33	1		T1	15
all_pins[26]	4175039	1			T32	36525		T33	1		T1	15
all_pins[27]	4175039	1			T32	36525		T33	1		T1	15
all_pins[28]	4175039	1			T32	36525		T33	1		T1	15
all_pins[29]	4175039	1			T32	36525		T33	1		T1	15
all_pins[30]	4175039	1			T32	36525		T33	1		T1	15
all_pins[31]	4175039	1			T32	36525		T33	1		T1	15

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	83016423	1			T32	730961		T33	32		T1	427
values[0x1]	50584825	1			T32	437839		T1	53		T11	394088
transitions[0x0=>0x1]	30317593	1			T32	264904		T1	33		T11	237177
transitions[0x1=>0x0]	30317446	1			T32	264904		T1	32		T11	237177

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2589199	1			T32	22725		T33	1		T1	10
all_pins[0]	values[0x1]	1585840	1			T32	13800		T1	5		T11	12489
all_pins[0]	transitions[0x0=>0x1]	983686	1			T32	8644		T1	4		T11	7843
all_pins[0]	transitions[0x1=>0x0]	976019	1			T32	8296		T1	1		T11	7601
all_pins[1]	values[0x0]	2591918	1			T32	22421		T33	1		T1	10
all_pins[1]	values[0x1]	1583121	1			T32	14104		T1	5		T11	12371
all_pins[1]	transitions[0x0=>0x1]	948457	1			T32	8546		T11	7596		T12	2077
all_pins[1]	transitions[0x1=>0x0]	951176	1			T32	8242		T11	7714		T12	2011
all_pins[2]	values[0x0]	2595073	1			T32	23390		T33	1		T1	12
all_pins[2]	values[0x1]	1579966	1			T32	13135		T1	3		T11	12767
all_pins[2]	transitions[0x0=>0x1]	943769	1			T32	7987		T11	7481		T12	1941
all_pins[2]	transitions[0x1=>0x0]	946924	1			T32	8956		T1	2		T11	7085
all_pins[3]	values[0x0]	2595647	1			T32	22936		T33	1		T1	11
all_pins[3]	values[0x1]	1579392	1			T32	13589		T1	4		T11	12307
all_pins[3]	transitions[0x0=>0x1]	945205	1			T32	7990		T1	1		T11	7260
all_pins[3]	transitions[0x1=>0x0]	945779	1			T32	7536		T11	7720		T12	1935
all_pins[4]	values[0x0]	2595227	1			T32	22552		T33	1		T1	11
all_pins[4]	values[0x1]	1579812	1			T32	13973		T1	4		T11	12214
all_pins[4]	transitions[0x0=>0x1]	945835	1			T32	8405		T1	1		T11	7594
all_pins[4]	transitions[0x1=>0x0]	945415	1			T32	8021		T1	1		T11	7687
all_pins[5]	values[0x0]	2594779	1			T32	22841		T33	1		T1	15
all_pins[5]	values[0x1]	1580260	1			T32	13684		T11	12606		T12	3088
all_pins[5]	transitions[0x0=>0x1]	945313	1			T32	7837		T11	7662		T12	1861
all_pins[5]	transitions[0x1=>0x0]	944865	1			T32	8126		T1	4		T11	7270
all_pins[6]	values[0x0]	2587452	1			T32	22675		T33	1		T1	15
all_pins[6]	values[0x1]	1587587	1			T32	13850		T11	12108		T12	3463
all_pins[6]	transitions[0x0=>0x1]	952170	1			T32	8531		T11	7104		T12	2248
all_pins[6]	transitions[0x1=>0x0]	944843	1			T32	8365		T11	7602		T12	1873
all_pins[7]	values[0x0]	2597085	1			T32	22873		T33	1		T1	15
all_pins[7]	values[0x1]	1577954	1			T32	13652		T11	12149		T12	3251
all_pins[7]	transitions[0x0=>0x1]	941268	1			T32	8286		T11	7582		T12	1902
all_pins[7]	transitions[0x1=>0x0]	950901	1			T32	8484		T11	7541		T12	2114
all_pins[8]	values[0x0]	2593839	1			T32	23009		T33	1		T1	15
all_pins[8]	values[0x1]	1581200	1			T32	13516		T11	11978		T12	3106
all_pins[8]	transitions[0x0=>0x1]	947773	1			T32	8122		T11	7097		T12	1798
all_pins[8]	transitions[0x1=>0x0]	944527	1			T32	8258		T11	7268		T12	1943
all_pins[9]	values[0x0]	2600049	1			T32	22753		T33	1		T1	12
all_pins[9]	values[0x1]	1574990	1			T32	13772		T1	3		T11	11882
all_pins[9]	transitions[0x0=>0x1]	942634	1			T32	8361		T1	3		T11	7160
all_pins[9]	transitions[0x1=>0x0]	948844	1			T32	8105		T11	7256		T12	1889
all_pins[10]	values[0x0]	2596977	1			T32	22297		T33	1		T1	12
all_pins[10]	values[0x1]	1578062	1			T32	14228		T1	3		T11	12336
all_pins[10]	transitions[0x0=>0x1]	948009	1			T32	8557		T1	1		T11	7678
all_pins[10]	transitions[0x1=>0x0]	944937	1			T32	8101		T1	1		T11	7224
all_pins[11]	values[0x0]	2596016	1			T32	22795		T33	1		T1	14
all_pins[11]	values[0x1]	1579023	1			T32	13730		T1	1		T11	12080
all_pins[11]	transitions[0x0=>0x1]	948003	1			T32	8046		T1	1		T11	7367
all_pins[11]	transitions[0x1=>0x0]	947042	1			T32	8544		T1	3		T11	7623
all_pins[12]	values[0x0]	2593625	1			T32	22575		T33	1		T1	13
all_pins[12]	values[0x1]	1581414	1			T32	13950		T1	2		T11	12622
all_pins[12]	transitions[0x0=>0x1]	947049	1			T32	8508		T1	1		T11	7680
all_pins[12]	transitions[0x1=>0x0]	944658	1			T32	8288		T11	7138		T12	2139
all_pins[13]	values[0x0]	2589501	1			T32	22743		T33	1		T1	15
all_pins[13]	values[0x1]	1585538	1			T32	13782		T11	12465		T12	3437
all_pins[13]	transitions[0x0=>0x1]	949984	1			T32	8155		T11	7432		T12	2216
all_pins[13]	transitions[0x1=>0x0]	945860	1			T32	8323		T1	2		T11	7589
all_pins[14]	values[0x0]	2593768	1			T32	23130		T33	1		T1	15
all_pins[14]	values[0x1]	1581271	1			T32	13395		T11	12468		T12	3454
all_pins[14]	transitions[0x0=>0x1]	944267	1			T32	8001		T11	7549		T12	2013
all_pins[14]	transitions[0x1=>0x0]	948534	1			T32	8388		T11	7546		T12	1996
all_pins[15]	values[0x0]	2594770	1			T32	23211		T33	1		T1	15
all_pins[15]	values[0x1]	1580269	1			T32	13314		T11	12350		T12	3464
all_pins[15]	transitions[0x0=>0x1]	946054	1			T32	8269		T11	7392		T12	2175
all_pins[15]	transitions[0x1=>0x0]	947056	1			T32	8350		T11	7510		T12	2165
all_pins[16]	values[0x0]	2593913	1			T32	23028		T33	1		T1	13
all_pins[16]	values[0x1]	1581126	1			T32	13497		T1	2		T11	12497
all_pins[16]	transitions[0x0=>0x1]	946513	1			T32	8167		T1	2		T11	7423
all_pins[16]	transitions[0x1=>0x0]	945656	1			T32	7984		T11	7276		T12	2107
all_pins[17]	values[0x0]	2599087	1			T32	22268		T33	1		T1	12
all_pins[17]	values[0x1]	1575952	1			T32	14257		T1	3		T11	12624
all_pins[17]	transitions[0x0=>0x1]	940557	1			T32	8580		T1	3		T11	7491
all_pins[17]	transitions[0x1=>0x0]	945731	1			T32	7820		T1	2		T11	7364
all_pins[18]	values[0x0]	2587716	1			T32	23045		T33	1		T1	15
all_pins[18]	values[0x1]	1587323	1			T32	13480		T11	12261		T12	3235
all_pins[18]	transitions[0x0=>0x1]	950866	1			T32	8019		T11	7073		T12	1962
all_pins[18]	transitions[0x1=>0x0]	939495	1			T32	8796		T1	3		T11	7436
all_pins[19]	values[0x0]	2594252	1			T32	23096		T33	1		T1	13
all_pins[19]	values[0x1]	1580787	1			T32	13429		T1	2		T11	11911
all_pins[19]	transitions[0x0=>0x1]	943223	1			T32	8157		T1	2		T11	7074
all_pins[19]	transitions[0x1=>0x0]	949759	1			T32	8208		T11	7424		T12	2020
all_pins[20]	values[0x0]	2592280	1			T32	23174		T33	1		T1	13
all_pins[20]	values[0x1]	1582759	1			T32	13351		T1	2		T11	12208
all_pins[20]	transitions[0x0=>0x1]	947619	1			T32	8402		T1	2		T11	7629
all_pins[20]	transitions[0x1=>0x0]	945647	1			T32	8480		T1	2		T11	7332
all_pins[21]	values[0x0]	2598309	1			T32	22707		T33	1		T1	10
all_pins[21]	values[0x1]	1576730	1			T32	13818		T1	5		T11	12269
all_pins[21]	transitions[0x0=>0x1]	943605	1			T32	8537		T1	3		T11	7290
all_pins[21]	transitions[0x1=>0x0]	949634	1			T32	8070		T11	7229		T12	2026
all_pins[22]	values[0x0]	2592284	1			T32	23150		T33	1		T1	15
all_pins[22]	values[0x1]	1582755	1			T32	13375		T11	12555		T12	3423
all_pins[22]	transitions[0x0=>0x1]	949049	1			T32	7978		T11	7622		T12	2161
all_pins[22]	transitions[0x1=>0x0]	943024	1			T32	8421		T1	5		T11	7336
all_pins[23]	values[0x0]	2589536	1			T32	22883		T33	1		T1	15
all_pins[23]	values[0x1]	1585503	1			T32	13642		T11	12550		T12	3107
all_pins[23]	transitions[0x0=>0x1]	948537	1			T32	8446		T11	7396		T12	1755
all_pins[23]	transitions[0x1=>0x0]	945789	1			T32	8179		T11	7401		T12	2071
all_pins[24]	values[0x0]	2592818	1			T32	22795		T33	1		T1	11
all_pins[24]	values[0x1]	1582221	1			T32	13730		T1	4		T11	12001
all_pins[24]	transitions[0x0=>0x1]	946464	1			T32	8198		T1	4		T11	7159
all_pins[24]	transitions[0x1=>0x0]	949746	1			T32	8110		T11	7708		T12	1732
all_pins[25]	values[0x0]	2591943	1			T32	23103		T33	1		T1	15
all_pins[25]	values[0x1]	1583096	1			T32	13422		T11	11953		T12	3082
all_pins[25]	transitions[0x0=>0x1]	948879	1			T32	8204		T11	7181		T12	1815
all_pins[25]	transitions[0x1=>0x0]	948004	1			T32	8512		T1	4		T11	7229
all_pins[26]	values[0x0]	2596820	1			T32	22598		T33	1		T1	15
all_pins[26]	values[0x1]	1578219	1			T32	13927		T11	12851		T12	3375
all_pins[26]	transitions[0x0=>0x1]	946083	1			T32	8654		T11	7827		T12	2146
all_pins[26]	transitions[0x1=>0x0]	950960	1			T32	8149		T11	6929		T12	1853
all_pins[27]	values[0x0]	2597226	1			T32	22588		T33	1		T1	15
all_pins[27]	values[0x1]	1577813	1			T32	13937		T11	12368		T12	3097
all_pins[27]	transitions[0x0=>0x1]	945490	1			T32	8476		T11	7203		T12	1845
all_pins[27]	transitions[0x1=>0x0]	945896	1			T32	8466		T11	7686		T12	2123
all_pins[28]	values[0x0]	2601062	1			T32	22549		T33	1		T1	15
all_pins[28]	values[0x1]	1573977	1			T32	13976		T11	11620		T12	3517
all_pins[28]	transitions[0x0=>0x1]	944666	1			T32	8446		T11	6750		T12	2330
all_pins[28]	transitions[0x1=>0x0]	948502	1			T32	8407		T11	7498		T12	1910
all_pins[29]	values[0x0]	2595966	1			T32	22871		T33	1		T1	13
all_pins[29]	values[0x1]	1579073	1			T32	13654		T1	2		T11	12489
all_pins[29]	transitions[0x0=>0x1]	945367	1			T32	8264		T1	2		T11	7574
all_pins[29]	transitions[0x1=>0x0]	940271	1			T32	8586		T11	6705		T12	2012
all_pins[30]	values[0x0]	2591567	1			T32	23107		T33	1		T1	15
all_pins[30]	values[0x1]	1583472	1			T32	13418		T11	12492		T12	3367
all_pins[30]	transitions[0x0=>0x1]	947072	1			T32	8177		T11	7487		T12	2112
all_pins[30]	transitions[0x1=>0x0]	942673	1			T32	8413		T1	2		T11	7484
all_pins[31]	values[0x0]	2596719	1			T32	23073		T33	1		T1	12
all_pins[31]	values[0x1]	1578320	1			T32	13452		T1	3		T11	12247
all_pins[31]	transitions[0x0=>0x1]	944127	1			T32	7954		T1	3		T11	7521
all_pins[31]	transitions[0x1=>0x0]	949279	1			T32	7920		T11	7766		T12	2140