Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14064972	1			T32	107550		T33	341		T1	29
all_values[1]	14064972	1			T32	107550		T33	341		T1	29
all_values[2]	14064972	1			T32	107550		T33	341		T1	29
all_values[3]	14064972	1			T32	107550		T33	341		T1	29
all_values[4]	14064972	1			T32	107550		T33	341		T1	29
all_values[5]	14064972	1			T32	107550		T33	341		T1	29
all_values[6]	14064972	1			T32	107550		T33	341		T1	29
all_values[7]	14064972	1			T32	107550		T33	341		T1	29
all_values[8]	14064972	1			T32	107550		T33	341		T1	29
all_values[9]	14064972	1			T32	107550		T33	341		T1	29
all_values[10]	14064972	1			T32	107550		T33	341		T1	29
all_values[11]	14064972	1			T32	107550		T33	341		T1	29
all_values[12]	14064972	1			T32	107550		T33	341		T1	29
all_values[13]	14064972	1			T32	107550		T33	341		T1	29
all_values[14]	14064972	1			T32	107550		T33	341		T1	29
all_values[15]	14064972	1			T32	107550		T33	341		T1	29
all_values[16]	14064972	1			T32	107550		T33	341		T1	29
all_values[17]	14064972	1			T32	107550		T33	341		T1	29
all_values[18]	14064972	1			T32	107550		T33	341		T1	29
all_values[19]	14064972	1			T32	107550		T33	341		T1	29
all_values[20]	14064972	1			T32	107550		T33	341		T1	29
all_values[21]	14064972	1			T32	107550		T33	341		T1	29
all_values[22]	14064972	1			T32	107550		T33	341		T1	29
all_values[23]	14064972	1			T32	107550		T33	341		T1	29
all_values[24]	14064972	1			T32	107550		T33	341		T1	29
all_values[25]	14064972	1			T32	107550		T33	341		T1	29
all_values[26]	14064972	1			T32	107550		T33	341		T1	29
all_values[27]	14064972	1			T32	107550		T33	341		T1	29
all_values[28]	14064972	1			T32	107550		T33	341		T1	29
all_values[29]	14064972	1			T32	107550		T33	341		T1	29
all_values[30]	14064972	1			T32	107550		T33	341		T1	29
all_values[31]	14064972	1			T32	107550		T33	341		T1	29

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

261775084

1

T32

193685

T33

10912

T1

758

auto[1]

188304020

1

T32

150474

T1

170

T11

130988

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109664417

1

T32

730461

T33

10912

T1

707

auto[1]

340414687

1

T32

271113

T1

221

T11

233591

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

445167068

1

T32

340346

T33

10912

T1

881

auto[1]

4912036

1

T32

38133

T1

47

T11

33355

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2848708	1			T32	17658		T33	341		T1	14
all_values[0]	auto[0]	auto[0]	auto[1]	5263176	1			T32	41104		T1	4		T11	37008
all_values[0]	auto[0]	auto[1]	auto[0]	570582	1			T32	4660		T1	5		T11	3711
all_values[0]	auto[0]	auto[1]	auto[1]	5228997	1			T32	42943		T1	3		T11	35721
all_values[0]	auto[1]	auto[0]	auto[1]	76264	1			T32	602		T1	1		T11	535
all_values[0]	auto[1]	auto[1]	auto[1]	77245	1			T32	583		T1	2		T11	508
all_values[1]	auto[0]	auto[0]	auto[0]	2847540	1			T32	17326		T33	341		T1	14
all_values[1]	auto[0]	auto[0]	auto[1]	5256399	1			T32	39326		T1	5		T11	35315
all_values[1]	auto[0]	auto[1]	auto[0]	577129	1			T32	5856		T1	5		T11	4076
all_values[1]	auto[0]	auto[1]	auto[1]	5229984	1			T32	43860		T1	3		T11	37292
all_values[1]	auto[1]	auto[0]	auto[1]	76853	1			T32	568		T11	494		T12	96
all_values[1]	auto[1]	auto[1]	auto[1]	77067	1			T32	614		T1	2		T11	539
all_values[2]	auto[0]	auto[0]	auto[0]	2852048	1			T32	18165		T33	341		T1	17
all_values[2]	auto[0]	auto[0]	auto[1]	5272544	1			T32	43691		T1	5		T11	35061
all_values[2]	auto[0]	auto[1]	auto[0]	569632	1			T32	5039		T1	2		T11	4305
all_values[2]	auto[0]	auto[1]	auto[1]	5217742	1			T32	39483		T1	3		T11	36879
all_values[2]	auto[1]	auto[0]	auto[1]	76542	1			T32	585		T1	1		T11	520
all_values[2]	auto[1]	auto[1]	auto[1]	76464	1			T32	587		T1	1		T11	524
all_values[3]	auto[0]	auto[0]	auto[0]	2847003	1			T32	17894		T33	341		T1	14
all_values[3]	auto[0]	auto[0]	auto[1]	5237858	1			T32	42599		T1	5		T11	35857
all_values[3]	auto[0]	auto[1]	auto[0]	581763	1			T32	4358		T1	5		T11	4478
all_values[3]	auto[0]	auto[1]	auto[1]	5245011	1			T32	41489		T1	3		T11	36010
all_values[3]	auto[1]	auto[0]	auto[1]	76897	1			T32	600		T11	562		T12	105
all_values[3]	auto[1]	auto[1]	auto[1]	76440	1			T32	610		T1	2		T11	454
all_values[4]	auto[0]	auto[0]	auto[0]	2854237	1			T32	17410		T33	341		T1	21
all_values[4]	auto[0]	auto[0]	auto[1]	5238826	1			T32	41388		T1	1		T11	37780
all_values[4]	auto[0]	auto[1]	auto[0]	571984	1			T32	5195		T1	2		T11	3785
all_values[4]	auto[0]	auto[1]	auto[1]	5246024	1			T32	42344		T1	3		T11	35258
all_values[4]	auto[1]	auto[0]	auto[1]	77704	1			T32	591		T1	1		T11	508
all_values[4]	auto[1]	auto[1]	auto[1]	76197	1			T32	622		T1	1		T11	529
all_values[5]	auto[0]	auto[0]	auto[0]	2857924	1			T32	17612		T33	341		T1	21
all_values[5]	auto[0]	auto[0]	auto[1]	5250412	1			T32	42900		T1	2		T11	35944
all_values[5]	auto[0]	auto[1]	auto[0]	575263	1			T32	4902		T1	6		T11	4438
all_values[5]	auto[0]	auto[1]	auto[1]	5227796	1			T32	40929		T11	36290		T12	8670
all_values[5]	auto[1]	auto[0]	auto[1]	76495	1			T32	595		T11	513		T12	99
all_values[5]	auto[1]	auto[1]	auto[1]	77082	1			T32	612		T11	554		T12	91
all_values[6]	auto[0]	auto[0]	auto[0]	2853825	1			T32	18217		T33	341		T1	23
all_values[6]	auto[0]	auto[0]	auto[1]	5209858	1			T32	41576		T1	3		T11	35800
all_values[6]	auto[0]	auto[1]	auto[0]	573246	1			T32	4619		T11	4427		T12	982
all_values[6]	auto[0]	auto[1]	auto[1]	5274580	1			T32	41970		T11	36035		T12	9262
all_values[6]	auto[1]	auto[0]	auto[1]	76606	1			T32	608		T1	3		T11	533
all_values[6]	auto[1]	auto[1]	auto[1]	76857	1			T32	560		T11	511		T12	91
all_values[7]	auto[0]	auto[0]	auto[0]	2857816	1			T32	18048		T33	341		T1	16
all_values[7]	auto[0]	auto[0]	auto[1]	5240285	1			T32	41934		T1	10		T11	35670
all_values[7]	auto[0]	auto[1]	auto[0]	564847	1			T32	4355		T11	5138		T12	1185
all_values[7]	auto[0]	auto[1]	auto[1]	5248979	1			T32	42014		T11	35335		T12	9275
all_values[7]	auto[1]	auto[0]	auto[1]	76751	1			T32	590		T1	3		T11	492
all_values[7]	auto[1]	auto[1]	auto[1]	76294	1			T32	609		T11	544		T12	91
all_values[8]	auto[0]	auto[0]	auto[0]	2851499	1			T32	18310		T33	341		T1	16
all_values[8]	auto[0]	auto[0]	auto[1]	5263080	1			T32	43749		T1	6		T11	36227
all_values[8]	auto[0]	auto[1]	auto[0]	572328	1			T32	4562		T1	6		T11	4856
all_values[8]	auto[0]	auto[1]	auto[1]	5224635	1			T32	39740		T11	35199		T12	8700
all_values[8]	auto[1]	auto[0]	auto[1]	76648	1			T32	653		T1	1		T11	500
all_values[8]	auto[1]	auto[1]	auto[1]	76782	1			T32	536		T11	509		T12	102
all_values[9]	auto[0]	auto[0]	auto[0]	2852038	1			T32	18091		T33	341		T1	14
all_values[9]	auto[0]	auto[0]	auto[1]	5250326	1			T32	41731		T1	5		T11	35620
all_values[9]	auto[0]	auto[1]	auto[0]	575608	1			T32	4782		T1	6		T11	4868
all_values[9]	auto[0]	auto[1]	auto[1]	5233665	1			T32	41745		T1	2		T11	35665
all_values[9]	auto[1]	auto[0]	auto[1]	77187	1			T32	544		T11	547		T12	103
all_values[9]	auto[1]	auto[1]	auto[1]	76148	1			T32	657		T1	2		T11	496
all_values[10]	auto[0]	auto[0]	auto[0]	2859983	1			T32	17465		T33	341		T1	20
all_values[10]	auto[0]	auto[0]	auto[1]	5271088	1			T32	42663		T1	3		T11	34886
all_values[10]	auto[0]	auto[1]	auto[0]	574738	1			T32	4495		T1	2		T11	4172
all_values[10]	auto[0]	auto[1]	auto[1]	5205858	1			T32	41739		T1	3		T11	37403
all_values[10]	auto[1]	auto[0]	auto[1]	76751	1			T32	612		T11	542		T12	95
all_values[10]	auto[1]	auto[1]	auto[1]	76554	1			T32	576		T1	1		T11	494
all_values[11]	auto[0]	auto[0]	auto[0]	2855937	1			T32	18078		T33	341		T1	18
all_values[11]	auto[0]	auto[0]	auto[1]	5245151	1			T32	41855		T1	7		T11	36523
all_values[11]	auto[0]	auto[1]	auto[0]	573944	1			T32	5116		T1	3		T11	4132
all_values[11]	auto[0]	auto[1]	auto[1]	5236282	1			T32	41305		T11	35201		T12	10174
all_values[11]	auto[1]	auto[0]	auto[1]	77301	1			T32	601		T11	485		T12	102
all_values[11]	auto[1]	auto[1]	auto[1]	76357	1			T32	595		T1	1		T11	569
all_values[12]	auto[0]	auto[0]	auto[0]	2852266	1			T32	17542		T33	341		T1	17
all_values[12]	auto[0]	auto[0]	auto[1]	5240583	1			T32	42414		T1	6		T11	34753
all_values[12]	auto[0]	auto[1]	auto[0]	571861	1			T32	4858		T1	2		T11	5035
all_values[12]	auto[0]	auto[1]	auto[1]	5246641	1			T32	41529		T1	1		T11	36648
all_values[12]	auto[1]	auto[0]	auto[1]	76948	1			T32	601		T1	2		T11	556
all_values[12]	auto[1]	auto[1]	auto[1]	76673	1			T32	606		T1	1		T11	537
all_values[13]	auto[0]	auto[0]	auto[0]	2850182	1			T32	18394		T33	341		T1	16
all_values[13]	auto[0]	auto[0]	auto[1]	5226179	1			T32	41068		T1	7		T11	35654
all_values[13]	auto[0]	auto[1]	auto[0]	562367	1			T32	4949		T1	6		T11	4624
all_values[13]	auto[0]	auto[1]	auto[1]	5272444	1			T32	41954		T11	36006		T12	9502
all_values[13]	auto[1]	auto[0]	auto[1]	77256	1			T32	585		T11	552		T12	89
all_values[13]	auto[1]	auto[1]	auto[1]	76544	1			T32	600		T11	490		T12	100
all_values[14]	auto[0]	auto[0]	auto[0]	2853134	1			T32	17639		T33	341		T1	21
all_values[14]	auto[0]	auto[0]	auto[1]	5237825	1			T32	43045		T1	1		T11	36256
all_values[14]	auto[0]	auto[1]	auto[0]	569792	1			T32	5204		T1	6		T11	4244
all_values[14]	auto[0]	auto[1]	auto[1]	5250546	1			T32	40457		T11	35327		T12	9731
all_values[14]	auto[1]	auto[0]	auto[1]	77065	1			T32	609		T1	1		T11	510
all_values[14]	auto[1]	auto[1]	auto[1]	76610	1			T32	596		T11	512		T12	93
all_values[15]	auto[0]	auto[0]	auto[0]	2850615	1			T32	17697		T33	341		T1	18
all_values[15]	auto[0]	auto[0]	auto[1]	5273313	1			T32	41806		T1	5		T11	35711
all_values[15]	auto[0]	auto[1]	auto[0]	571598	1			T32	4874		T1	6		T11	4213
all_values[15]	auto[0]	auto[1]	auto[1]	5215645	1			T32	41950		T11	36713		T12	9092
all_values[15]	auto[1]	auto[0]	auto[1]	77718	1			T32	620		T11	545		T12	107
all_values[15]	auto[1]	auto[1]	auto[1]	76083	1			T32	603		T11	554		T12	84
all_values[16]	auto[0]	auto[0]	auto[0]	2850971	1			T32	18311		T33	341		T1	18
all_values[16]	auto[0]	auto[0]	auto[1]	5255601	1			T32	41788		T1	5		T11	34794
all_values[16]	auto[0]	auto[1]	auto[0]	577340	1			T32	4955		T1	2		T11	4052
all_values[16]	auto[0]	auto[1]	auto[1]	5228106	1			T32	41338		T1	1		T11	37173
all_values[16]	auto[1]	auto[0]	auto[1]	76778	1			T32	578		T1	2		T11	508
all_values[16]	auto[1]	auto[1]	auto[1]	76176	1			T32	580		T1	1		T11	532
all_values[17]	auto[0]	auto[0]	auto[0]	2855964	1			T32	17484		T33	341		T1	19
all_values[17]	auto[0]	auto[0]	auto[1]	5246641	1			T32	42960		T11	35565		T12	10023
all_values[17]	auto[0]	auto[1]	auto[0]	579735	1			T32	5154		T1	8		T11	4643
all_values[17]	auto[0]	auto[1]	auto[1]	5229510	1			T32	40735		T1	2		T11	36730
all_values[17]	auto[1]	auto[0]	auto[1]	76703	1			T32	600		T11	519		T12	106
all_values[17]	auto[1]	auto[1]	auto[1]	76419	1			T32	617		T11	521		T12	85
all_values[18]	auto[0]	auto[0]	auto[0]	2846838	1			T32	18082		T33	341		T1	22
all_values[18]	auto[0]	auto[0]	auto[1]	5245639	1			T32	42747		T1	1		T11	35717
all_values[18]	auto[0]	auto[1]	auto[0]	572971	1			T32	5144		T1	6		T11	5285
all_values[18]	auto[0]	auto[1]	auto[1]	5246055	1			T32	40415		T11	35706		T12	9041
all_values[18]	auto[1]	auto[0]	auto[1]	77412	1			T32	591		T11	564		T12	98
all_values[18]	auto[1]	auto[1]	auto[1]	76057	1			T32	571		T11	499		T12	90
all_values[19]	auto[0]	auto[0]	auto[0]	2847490	1			T32	18238		T33	341		T1	19
all_values[19]	auto[0]	auto[0]	auto[1]	5209352	1			T32	43962		T1	2		T11	37611
all_values[19]	auto[0]	auto[1]	auto[0]	578396	1			T32	4504		T1	3		T11	4549
all_values[19]	auto[0]	auto[1]	auto[1]	5276353	1			T32	39634		T1	2		T11	34381
all_values[19]	auto[1]	auto[0]	auto[1]	76727	1			T32	653		T1	2		T11	535
all_values[19]	auto[1]	auto[1]	auto[1]	76654	1			T32	559		T1	1		T11	500
all_values[20]	auto[0]	auto[0]	auto[0]	2860494	1			T32	18972		T33	341		T1	20
all_values[20]	auto[0]	auto[0]	auto[1]	5233954	1			T32	42425		T1	4		T11	36475
all_values[20]	auto[0]	auto[1]	auto[0]	570927	1			T32	4600		T1	2		T11	4265
all_values[20]	auto[0]	auto[1]	auto[1]	5246076	1			T32	40374		T1	2		T11	35706
all_values[20]	auto[1]	auto[0]	auto[1]	76592	1			T32	642		T1	1		T11	529
all_values[20]	auto[1]	auto[1]	auto[1]	76929	1			T32	537		T11	492		T12	115
all_values[21]	auto[0]	auto[0]	auto[0]	2864963	1			T32	17992		T33	341		T1	16
all_values[21]	auto[0]	auto[0]	auto[1]	5247147	1			T32	40857		T1	3		T11	36609
all_values[21]	auto[0]	auto[1]	auto[0]	576267	1			T32	5003		T1	5		T11	4264
all_values[21]	auto[0]	auto[1]	auto[1]	5222864	1			T32	42517		T1	4		T11	35870
all_values[21]	auto[1]	auto[0]	auto[1]	77026	1			T32	558		T11	525		T12	110
all_values[21]	auto[1]	auto[1]	auto[1]	76705	1			T32	623		T1	1		T11	511
all_values[22]	auto[0]	auto[0]	auto[0]	2848515	1			T32	18303		T33	341		T1	20
all_values[22]	auto[0]	auto[0]	auto[1]	5261902	1			T32	41744		T1	7		T11	35969
all_values[22]	auto[0]	auto[1]	auto[0]	573412	1			T32	5100		T11	4712		T12	1315
all_values[22]	auto[0]	auto[1]	auto[1]	5227622	1			T32	41216		T11	36146		T12	9455
all_values[22]	auto[1]	auto[0]	auto[1]	76781	1			T32	563		T1	2		T11	489
all_values[22]	auto[1]	auto[1]	auto[1]	76740	1			T32	624		T11	539		T12	83
all_values[23]	auto[0]	auto[0]	auto[0]	2848948	1			T32	17707		T33	341		T1	14
all_values[23]	auto[0]	auto[0]	auto[1]	5270131	1			T32	42456		T1	7		T11	36806
all_values[23]	auto[0]	auto[1]	auto[0]	570678	1			T32	5049		T1	6		T11	4874
all_values[23]	auto[0]	auto[1]	auto[1]	5221337	1			T32	41134		T11	35032		T12	8919
all_values[23]	auto[1]	auto[0]	auto[1]	76940	1			T32	617		T1	2		T11	536
all_values[23]	auto[1]	auto[1]	auto[1]	76938	1			T32	587		T11	536		T12	108
all_values[24]	auto[0]	auto[0]	auto[0]	2852229	1			T32	17602		T33	341		T1	16
all_values[24]	auto[0]	auto[0]	auto[1]	5259308	1			T32	40806		T1	3		T11	37100
all_values[24]	auto[0]	auto[1]	auto[0]	566519	1			T32	5151		T1	6		T11	4245
all_values[24]	auto[0]	auto[1]	auto[1]	5232984	1			T32	42776		T1	3		T11	35382
all_values[24]	auto[1]	auto[0]	auto[1]	77062	1			T32	605		T11	512		T12	95
all_values[24]	auto[1]	auto[1]	auto[1]	76870	1			T32	610		T1	1		T11	498
all_values[25]	auto[0]	auto[0]	auto[0]	2846883	1			T32	17919		T33	341		T1	20
all_values[25]	auto[0]	auto[0]	auto[1]	5238474	1			T32	41728		T1	8		T11	36255
all_values[25]	auto[0]	auto[1]	auto[0]	576939	1			T32	4460		T11	5043		T12	1348
all_values[25]	auto[0]	auto[1]	auto[1]	5248742	1			T32	42244		T11	35041		T12	8950
all_values[25]	auto[1]	auto[0]	auto[1]	77174	1			T32	595		T1	1		T11	539
all_values[25]	auto[1]	auto[1]	auto[1]	76760	1			T32	604		T11	497		T12	92
all_values[26]	auto[0]	auto[0]	auto[0]	2856472	1			T32	17867		T33	341		T1	17
all_values[26]	auto[0]	auto[0]	auto[1]	5248554	1			T32	40278		T1	6		T11	34628
all_values[26]	auto[0]	auto[1]	auto[0]	575924	1			T32	4597		T1	4		T11	4921
all_values[26]	auto[0]	auto[1]	auto[1]	5230448	1			T32	43636		T11	36840		T12	9693
all_values[26]	auto[1]	auto[0]	auto[1]	76918	1			T32	551		T1	2		T11	539
all_values[26]	auto[1]	auto[1]	auto[1]	76656	1			T32	621		T11	535		T12	90
all_values[27]	auto[0]	auto[0]	auto[0]	2854563	1			T32	18059		T33	341		T1	27
all_values[27]	auto[0]	auto[0]	auto[1]	5287134	1			T32	41651		T1	2		T11	36445
all_values[27]	auto[0]	auto[1]	auto[0]	576810	1			T32	4458		T11	4356		T12	988
all_values[27]	auto[0]	auto[1]	auto[1]	5193631	1			T32	42147		T11	35876		T12	8854
all_values[27]	auto[1]	auto[0]	auto[1]	77041	1			T32	633		T11	520		T12	103
all_values[27]	auto[1]	auto[1]	auto[1]	75793	1			T32	602		T11	522		T12	83
all_values[28]	auto[0]	auto[0]	auto[0]	2860484	1			T32	17905		T33	341		T1	25
all_values[28]	auto[0]	auto[0]	auto[1]	5273191	1			T32	40269		T1	4		T11	37716
all_values[28]	auto[0]	auto[1]	auto[0]	580286	1			T32	5221		T11	4610		T12	1520
all_values[28]	auto[0]	auto[1]	auto[1]	5197954	1			T32	42966		T11	33899		T12	9326
all_values[28]	auto[1]	auto[0]	auto[1]	76844	1			T32	620		T11	571		T12	100
all_values[28]	auto[1]	auto[1]	auto[1]	76213	1			T32	569		T11	495		T12	94
all_values[29]	auto[0]	auto[0]	auto[0]	2853287	1			T32	18073		T33	341		T1	17
all_values[29]	auto[0]	auto[0]	auto[1]	5242564	1			T32	43358		T1	6		T11	35594
all_values[29]	auto[0]	auto[1]	auto[0]	587492	1			T32	5313		T1	2		T11	4543
all_values[29]	auto[0]	auto[1]	auto[1]	5227996	1			T32	39642		T1	1		T11	36211
all_values[29]	auto[1]	auto[0]	auto[1]	77233	1			T32	606		T1	2		T11	538
all_values[29]	auto[1]	auto[1]	auto[1]	76400	1			T32	558		T1	1		T11	471
all_values[30]	auto[0]	auto[0]	auto[0]	2853271	1			T32	17818		T33	341		T1	26
all_values[30]	auto[0]	auto[0]	auto[1]	5249192	1			T32	42751		T1	3		T11	36120
all_values[30]	auto[0]	auto[1]	auto[0]	579855	1			T32	5340		T11	4351		T12	1150
all_values[30]	auto[0]	auto[1]	auto[1]	5229104	1			T32	40484		T11	36061		T12	9293
all_values[30]	auto[1]	auto[0]	auto[1]	76453	1			T32	573		T11	478		T12	82
all_values[30]	auto[1]	auto[1]	auto[1]	77097	1			T32	584		T11	552		T12	112
all_values[31]	auto[0]	auto[0]	auto[0]	2853594	1			T32	17861		T33	341		T1	18
all_values[31]	auto[0]	auto[0]	auto[1]	5267523	1			T32	41360		T11	34988		T12	9238
all_values[31]	auto[0]	auto[1]	auto[0]	564463	1			T32	4849		T1	7		T11	4050
all_values[31]	auto[0]	auto[1]	auto[1]	5225830	1			T32	42308		T1	2		T11	37062
all_values[31]	auto[1]	auto[0]	auto[1]	77483	1			T32	577		T1	1		T11	540
all_values[31]	auto[1]	auto[1]	auto[1]	76079	1			T32	595		T1	1		T11	495

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal