Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[1]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[2]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[3]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[4]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[5]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[6]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[7]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[8]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[9]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[10]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[11]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[12]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[13]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[14]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[15]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[16]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[17]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[18]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[19]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[20]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[21]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[22]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[23]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[24]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[25]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[26]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[27]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[28]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[29]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[30]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[31]	13873120	1			T32	108283		T33	553		T1	44

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272750707

1

T32

228853

T33

12411

T1

748

auto[1]

171189133

1

T32

117652

T33

5285

T1

660

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

356756843

1

T32

271501

T33

11025

T1

1338

auto[1]

87182997

1

T32

750038

T33

6671

T1

70

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

330865101

1

T32

244668

T33

10845

T1

1179

auto[1]

113074739

1

T32

101837

T33

6851

T1

229

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5278711	1			T32	40929		T33	166		T1	17
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3687699	1			T32	23630		T33	50		T1	17
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1374305	1			T32	11566		T33	134		T11	10540
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1864744	1			T32	18822		T33	92		T1	4
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	310123	1			T32	1434		T1	4		T11	1182
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1357538	1			T32	11902		T33	111		T1	2
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5275751	1			T32	40619		T33	152		T1	8
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3692503	1			T32	23666		T33	76		T1	26
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1374015	1			T32	11584		T33	106		T11	11132
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1859805	1			T32	19391		T33	117		T1	4
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	310100	1			T32	1498		T1	2		T11	1063
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1360946	1			T32	11525		T33	102		T1	4
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5288329	1			T32	40744		T33	179		T1	20
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3683805	1			T32	23395		T33	61		T1	14
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1368213	1			T32	12513		T33	118		T11	11100
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1864431	1			T32	18214		T33	88		T1	8
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	309376	1			T32	1492		T11	1149		T12	2000
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1358966	1			T32	11925		T33	107		T1	2
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5283997	1			T32	41311		T33	162		T1	10
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3685296	1			T32	23594		T33	64		T1	24
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1375453	1			T32	11672		T33	100		T11	11316
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1864687	1			T32	18723		T33	102		T1	4
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	310070	1			T32	1498		T1	4		T11	1177
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1353617	1			T32	11485		T33	125		T1	2
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5282742	1			T32	40266		T33	138		T1	28
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3685861	1			T32	23640		T33	68		T1	16
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1372195	1			T32	11461		T33	128		T11	10595
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1864986	1			T32	19129		T33	115		T11	16521
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	307997	1			T32	1654		T11	1263		T12	1821
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1359339	1			T32	12133		T33	104		T11	10715
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5285357	1			T32	41606		T33	149		T1	18
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3683565	1			T32	23639		T33	67		T1	17
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1372886	1			T32	12259		T33	102		T1	3
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1861463	1			T32	17670		T33	96		T1	4
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	310502	1			T32	1457		T11	1239		T12	1795
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1359347	1			T32	11652		T33	139		T1	2
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5289137	1			T32	41684		T33	169		T1	10
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3685072	1			T32	23592		T33	65		T1	28
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1369414	1			T32	11684		T33	115		T11	10933
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1870245	1			T32	18345		T33	110		T1	4
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	307915	1			T32	1588		T11	1197		T12	1625
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1351337	1			T32	11390		T33	94		T1	2
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5274206	1			T32	40719		T33	171		T1	25
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3691609	1			T32	23596		T33	68		T1	15
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1369176	1			T32	11820		T33	122		T11	10594
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1867850	1			T32	18915		T33	90		T1	4
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	309703	1			T32	1489		T11	1208		T12	1780
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1360576	1			T32	11744		T33	102		T11	10986
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5282663	1			T32	41564		T33	172		T1	21
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3685503	1			T32	23562		T33	64		T1	6
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1374748	1			T32	11928		T33	126		T1	3
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1865210	1			T32	18227		T33	109		T1	12
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	307862	1			T32	1409		T11	1122		T12	1927
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1357134	1			T32	11593		T33	82		T1	2
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5285284	1			T32	41361		T33	175		T1	14
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3681446	1			T32	23542		T33	65		T1	26
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1370834	1			T32	12031		T33	117		T11	10796
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1864195	1			T32	17688		T33	124		T11	16439
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	310557	1			T32	1451		T1	4		T11	1212
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1360804	1			T32	12210		T33	72		T11	11002
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5268497	1			T32	41244		T33	142		T1	15
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3689656	1			T32	23536		T33	57		T1	16
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1368575	1			T32	12023		T33	106		T1	3
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1875940	1			T32	18461		T33	134		T1	4
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	310152	1			T32	1490		T1	4		T11	1181
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1360300	1			T32	11529		T33	114		T1	2
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5286630	1			T32	41221		T33	209		T1	6
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3680354	1			T32	23592		T33	65		T1	21
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1369603	1			T32	12195		T33	92		T1	3
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1867693	1			T32	17997		T33	98		T1	8
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	310559	1			T32	1468		T1	4		T11	1272
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1358281	1			T32	11810		T33	89		T1	2
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5289739	1			T32	40688		T33	163		T1	29
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3673511	1			T32	23531		T33	58		T1	11
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1369263	1			T32	11615		T33	100		T11	10807
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1870009	1			T32	18942		T33	108		T1	4
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	309239	1			T32	1587		T11	1156		T12	1791
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1361359	1			T32	11920		T33	124		T11	10587
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5293102	1			T32	41197		T33	165		T1	10
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3677599	1			T32	23730		T33	69		T1	20
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1369649	1			T32	12033		T33	124		T11	11014
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1863836	1			T32	18085		T33	99		T1	4
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	310635	1			T32	1599		T1	8		T11	1151
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1358299	1			T32	11639		T33	96		T1	2
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5288528	1			T32	41199		T33	168		T1	21
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3688423	1			T32	23871		T33	64		T1	9
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1369165	1			T32	12113		T33	94		T11	10576
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1864474	1			T32	18004		T33	121		T1	8
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	308725	1			T32	1362		T1	2		T11	1166
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1353805	1			T32	11734		T33	106		T1	4
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5278633	1			T32	40693		T33	163		T1	29
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3681809	1			T32	23474		T33	65		T1	11
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1362281	1			T32	11657		T33	94		T11	10800
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1873759	1			T32	19083		T33	117		T1	4
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	309593	1			T32	1587		T11	1143		T12	1881
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1367045	1			T32	11789		T33	114		T11	11042
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5282473	1			T32	41714		T33	145		T1	15
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3696927	1			T32	23493		T33	69		T1	23
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1363521	1			T32	11777		T33	131		T11	10708
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1865846	1			T32	18385		T33	114		T1	4
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	310393	1			T32	1498		T11	1222		T12	1981
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1353960	1			T32	11416		T33	94		T1	2
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5298723	1			T32	41496		T33	205		T1	15
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3676335	1			T32	23337		T33	57		T1	17
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1363731	1			T32	11606		T33	99		T11	11218
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1872118	1			T32	18635		T33	106		T1	4
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	310046	1			T32	1632		T1	5		T11	1144
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1352167	1			T32	11577		T33	86		T1	3
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5294551	1			T32	41112		T33	153		T1	20
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3676849	1			T32	23235		T33	59		T1	18
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1364709	1			T32	11322		T33	138		T11	11168
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1866947	1			T32	19385		T33	96		T1	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	313787	1			T32	1590		T11	1134		T12	1845
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1356277	1			T32	11639		T33	107		T1	2
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5294064	1			T32	41557		T33	185		T1	14
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3685306	1			T32	23568		T33	62		T1	22
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1368631	1			T32	11756		T33	94		T11	10965
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1863244	1			T32	18359		T33	102		T1	4
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	309998	1			T32	1514		T1	2		T11	1117
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1351877	1			T32	11529		T33	110		T1	2
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5289581	1			T32	40760		T33	188		T1	16
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3685238	1			T32	23589		T33	63		T1	27
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1361530	1			T32	11586		T33	94		T11	10959
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1872052	1			T32	19165		T33	102		T11	16132
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	312782	1			T32	1559		T1	1		T11	1128
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1351937	1			T32	11624		T33	106		T11	10731
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5291010	1			T32	41350		T33	163		T1	29
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3684788	1			T32	23492		T33	57		T1	10
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1365605	1			T32	11809		T33	85		T1	3
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1864607	1			T32	18752		T33	140		T11	16208
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	310169	1			T32	1525		T1	2		T11	1136
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1356941	1			T32	11355		T33	108		T11	10483
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5293420	1			T32	41314		T33	211		T1	14
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3680747	1			T32	23364		T33	59		T1	23
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1365575	1			T32	11703		T33	100		T11	11105
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1869596	1			T32	18737		T33	102		T1	4
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	312029	1			T32	1466		T1	1		T11	1149
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1351753	1			T32	11699		T33	81		T1	2
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5308600	1			T32	40708		T33	168		T1	22
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3672947	1			T32	23736		T33	72		T1	18
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1363430	1			T32	11427		T33	98		T1	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1870070	1			T32	19274		T33	101		T1	2
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	309451	1			T32	1601		T1	1		T11	1122
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1348622	1			T32	11537		T33	114		T11	10900
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5297632	1			T32	41528		T33	180		T1	23
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3678966	1			T32	23564		T33	60		T1	7
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1366454	1			T32	11808		T33	122		T11	11340
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1861426	1			T32	18261		T33	85		T1	8
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	311613	1			T32	1466		T1	4		T11	1048
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1357029	1			T32	11656		T33	106		T1	2
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5291337	1			T32	41342		T33	193		T1	14
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3678827	1			T32	23471		T33	67		T1	30
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1366305	1			T32	11229		T33	73		T11	10515
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1869226	1			T32	18816		T33	124		T11	16746
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	312100	1			T32	1553		T11	1313		T12	1816
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1355325	1			T32	11872		T33	96		T11	10531
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5289702	1			T32	41568		T33	154		T1	25
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3676409	1			T32	23478		T33	65		T1	16
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1369053	1			T32	11750		T33	98		T1	3
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1871353	1			T32	18420		T33	146		T11	16017
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	308771	1			T32	1553		T11	1178		T12	1965
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1357832	1			T32	11514		T33	90		T11	10915
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5292335	1			T32	41307		T33	146		T1	25
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3679056	1			T32	23485		T33	62		T1	5
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1363716	1			T32	11330		T33	77		T11	11082
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1871410	1			T32	18833		T33	164		T1	8
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	313712	1			T32	1537		T1	4		T11	1060
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1352891	1			T32	11791		T33	104		T1	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5293118	1			T32	41139		T33	158		T1	14
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3684780	1			T32	23729		T33	56		T1	26
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1365862	1			T32	11550		T33	96		T11	10693
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1865024	1			T32	18681		T33	150		T11	16396
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	310643	1			T32	1555		T1	3		T11	1164
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1353693	1			T32	11629		T33	93		T1	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5293471	1			T32	41271		T33	182		T1	17
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3684185	1			T32	23637		T33	54		T1	21
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1366044	1			T32	11614		T33	118		T11	10875
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1864390	1			T32	18658		T33	109		T1	4
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	310369	1			T32	1481		T11	1254		T12	1703
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1354661	1			T32	11622		T33	90		T1	2
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5293637	1			T32	41122		T33	184		T1	28
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3680663	1			T32	23663		T33	63		T1	4
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1364290	1			T32	11731		T33	110		T1	2
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1869907	1			T32	18563		T33	106		T1	8
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	309643	1			T32	1426		T11	1157		T12	1856
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1354980	1			T32	11778		T33	90		T1	2
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5298635	1			T32	40706		T33	175		T1	24
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3678910	1			T32	23379		T33	62		T1	15
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1368631	1			T32	11683		T33	88		T1	3
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1859707	1			T32	19041		T33	112		T1	2
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	309740	1			T32	1489		T11	1174		T12	1675
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1357497	1			T32	11985		T33	116		T11	10470

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal