Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[1]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[2]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[3]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[4]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[5]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[6]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[7]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[8]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[9]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[10]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[11]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[12]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[13]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[14]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[15]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[16]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[17]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[18]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[19]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[20]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[21]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[22]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[23]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[24]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[25]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[26]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[27]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[28]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[29]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[30]	13873120	1			T32	108283		T33	553		T1	44
bins_for_gpio_bits[31]	13873120	1			T32	108283		T33	553		T1	44

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272750707

1

T32

228853

T33

12411

T1

748

auto[1]

171189133

1

T32

117652

T33

5285

T1

660

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272739862

1

T32

228825

T33

12403

T1

728

auto[1]

171199978

1

T32

117680

T33

5293

T1

680

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8274194	1			T32	69204		T33	361		T1	20
bins_for_gpio_bits[0]	auto[0]	auto[1]	243226	1			T32	2106		T33	30		T11	1997
bins_for_gpio_bits[0]	auto[1]	auto[0]	243566	1			T32	2113		T33	31		T1	1
bins_for_gpio_bits[0]	auto[1]	auto[1]	5112134	1			T32	34860		T33	131		T1	23
bins_for_gpio_bits[1]	auto[0]	auto[0]	8266242	1			T32	69456		T33	346		T1	11
bins_for_gpio_bits[1]	auto[0]	auto[1]	242972	1			T32	2127		T33	29		T11	1975
bins_for_gpio_bits[1]	auto[1]	auto[0]	243329	1			T32	2138		T33	29		T1	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	5120577	1			T32	34562		T33	149		T1	32
bins_for_gpio_bits[2]	auto[0]	auto[0]	8278097	1			T32	69326		T33	359		T1	27
bins_for_gpio_bits[2]	auto[0]	auto[1]	242597	1			T32	2133		T33	25		T11	1983
bins_for_gpio_bits[2]	auto[1]	auto[0]	242876	1			T32	2145		T33	26		T1	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	5109550	1			T32	34679		T33	143		T1	16
bins_for_gpio_bits[3]	auto[0]	auto[0]	8280954	1			T32	69601		T33	337		T1	13
bins_for_gpio_bits[3]	auto[0]	auto[1]	242821	1			T32	2093		T33	26		T11	2014
bins_for_gpio_bits[3]	auto[1]	auto[0]	243183	1			T32	2105		T33	27		T1	1
bins_for_gpio_bits[3]	auto[1]	auto[1]	5106162	1			T32	34484		T33	163		T1	30
bins_for_gpio_bits[4]	auto[0]	auto[0]	8276510	1			T32	68681		T33	354		T1	28
bins_for_gpio_bits[4]	auto[0]	auto[1]	243029	1			T32	2165		T33	27		T11	1997
bins_for_gpio_bits[4]	auto[1]	auto[0]	243413	1			T32	2175		T33	27		T11	2006
bins_for_gpio_bits[4]	auto[1]	auto[1]	5110168	1			T32	35262		T33	145		T1	16
bins_for_gpio_bits[5]	auto[0]	auto[0]	8276468	1			T32	69434		T33	317		T1	24
bins_for_gpio_bits[5]	auto[0]	auto[1]	242930	1			T32	2093		T33	29		T11	2051
bins_for_gpio_bits[5]	auto[1]	auto[0]	243238	1			T32	2101		T33	30		T1	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	5110484	1			T32	34655		T33	177		T1	19
bins_for_gpio_bits[6]	auto[0]	auto[0]	8285809	1			T32	69658		T33	368		T1	13
bins_for_gpio_bits[6]	auto[0]	auto[1]	242646	1			T32	2048		T33	26		T11	2043
bins_for_gpio_bits[6]	auto[1]	auto[0]	242987	1			T32	2055		T33	26		T1	1
bins_for_gpio_bits[6]	auto[1]	auto[1]	5101678	1			T32	34522		T33	133		T1	30
bins_for_gpio_bits[7]	auto[0]	auto[0]	8267591	1			T32	69281		T33	354		T1	29
bins_for_gpio_bits[7]	auto[0]	auto[1]	243310	1			T32	2165		T33	29		T11	2034
bins_for_gpio_bits[7]	auto[1]	auto[0]	243641	1			T32	2173		T33	29		T11	2045
bins_for_gpio_bits[7]	auto[1]	auto[1]	5118578	1			T32	34664		T33	141		T1	15
bins_for_gpio_bits[8]	auto[0]	auto[0]	8278994	1			T32	69623		T33	381		T1	35
bins_for_gpio_bits[8]	auto[0]	auto[1]	243301	1			T32	2088		T33	26		T11	2015
bins_for_gpio_bits[8]	auto[1]	auto[0]	243627	1			T32	2096		T33	26		T1	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	5107198	1			T32	34476		T33	120		T1	8
bins_for_gpio_bits[9]	auto[0]	auto[0]	8276864	1			T32	68876		T33	394		T1	14
bins_for_gpio_bits[9]	auto[0]	auto[1]	243114	1			T32	2194		T33	22		T11	2043
bins_for_gpio_bits[9]	auto[1]	auto[0]	243449	1			T32	2204		T33	22		T11	2048
bins_for_gpio_bits[9]	auto[1]	auto[1]	5109693	1			T32	35009		T33	115		T1	30
bins_for_gpio_bits[10]	auto[0]	auto[0]	8269289	1			T32	69609		T33	355		T1	21
bins_for_gpio_bits[10]	auto[0]	auto[1]	243395	1			T32	2112		T33	27		T11	1994
bins_for_gpio_bits[10]	auto[1]	auto[0]	243723	1			T32	2119		T33	27		T1	1
bins_for_gpio_bits[10]	auto[1]	auto[1]	5116713	1			T32	34443		T33	144		T1	22
bins_for_gpio_bits[11]	auto[0]	auto[0]	8280979	1			T32	69299		T33	373		T1	16
bins_for_gpio_bits[11]	auto[0]	auto[1]	242616	1			T32	2102		T33	25		T11	1979
bins_for_gpio_bits[11]	auto[1]	auto[0]	242947	1			T32	2114		T33	26		T1	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	5106578	1			T32	34768		T33	129		T1	27
bins_for_gpio_bits[12]	auto[0]	auto[0]	8284868	1			T32	69091		T33	341		T1	33
bins_for_gpio_bits[12]	auto[0]	auto[1]	243794	1			T32	2148		T33	30		T11	2017
bins_for_gpio_bits[12]	auto[1]	auto[0]	244143	1			T32	2154		T33	30		T11	2022
bins_for_gpio_bits[12]	auto[1]	auto[1]	5100315	1			T32	34890		T33	152		T1	11
bins_for_gpio_bits[13]	auto[0]	auto[0]	8283926	1			T32	69254		T33	363		T1	13
bins_for_gpio_bits[13]	auto[0]	auto[1]	242347	1			T32	2058		T33	25		T11	1986
bins_for_gpio_bits[13]	auto[1]	auto[0]	242661	1			T32	2061		T33	25		T1	1
bins_for_gpio_bits[13]	auto[1]	auto[1]	5104186	1			T32	34910		T33	140		T1	30
bins_for_gpio_bits[14]	auto[0]	auto[0]	8278686	1			T32	69199		T33	354		T1	28
bins_for_gpio_bits[14]	auto[0]	auto[1]	243166	1			T32	2108		T33	29		T11	2035
bins_for_gpio_bits[14]	auto[1]	auto[0]	243481	1			T32	2117		T33	29		T1	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	5107787	1			T32	34859		T33	141		T1	15
bins_for_gpio_bits[15]	auto[0]	auto[0]	8270810	1			T32	69278		T33	346		T1	33
bins_for_gpio_bits[15]	auto[0]	auto[1]	243513	1			T32	2149		T33	28		T11	2030
bins_for_gpio_bits[15]	auto[1]	auto[0]	243863	1			T32	2155		T33	28		T11	2034
bins_for_gpio_bits[15]	auto[1]	auto[1]	5114934	1			T32	34701		T33	151		T1	11
bins_for_gpio_bits[16]	auto[0]	auto[0]	8268463	1			T32	69793		T33	359		T1	18
bins_for_gpio_bits[16]	auto[0]	auto[1]	243007	1			T32	2071		T33	31		T11	1972
bins_for_gpio_bits[16]	auto[1]	auto[0]	243377	1			T32	2083		T33	31		T1	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	5118273	1			T32	34336		T33	132		T1	25
bins_for_gpio_bits[17]	auto[0]	auto[0]	8291358	1			T32	69622		T33	391		T1	18
bins_for_gpio_bits[17]	auto[0]	auto[1]	242875	1			T32	2107		T33	19		T11	2038
bins_for_gpio_bits[17]	auto[1]	auto[0]	243214	1			T32	2115		T33	19		T1	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	5095673	1			T32	34439		T33	124		T1	25
bins_for_gpio_bits[18]	auto[0]	auto[0]	8283365	1			T32	69688		T33	357		T1	23
bins_for_gpio_bits[18]	auto[0]	auto[1]	242452	1			T32	2118		T33	29		T11	1989
bins_for_gpio_bits[18]	auto[1]	auto[0]	242842	1			T32	2131		T33	30		T1	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	5104461	1			T32	34346		T33	137		T1	20
bins_for_gpio_bits[19]	auto[0]	auto[0]	8283355	1			T32	69620		T33	353		T1	17
bins_for_gpio_bits[19]	auto[0]	auto[1]	242255	1			T32	2041		T33	28		T11	1954
bins_for_gpio_bits[19]	auto[1]	auto[0]	242584	1			T32	2052		T33	28		T1	1
bins_for_gpio_bits[19]	auto[1]	auto[1]	5104926	1			T32	34570		T33	144		T1	26
bins_for_gpio_bits[20]	auto[0]	auto[0]	8280132	1			T32	69370		T33	360		T1	16
bins_for_gpio_bits[20]	auto[0]	auto[1]	242702	1			T32	2130		T33	24		T11	2010
bins_for_gpio_bits[20]	auto[1]	auto[0]	243031	1			T32	2141		T33	24		T11	2016
bins_for_gpio_bits[20]	auto[1]	auto[1]	5107255	1			T32	34642		T33	145		T1	28
bins_for_gpio_bits[21]	auto[0]	auto[0]	8277678	1			T32	69820		T33	360		T1	32
bins_for_gpio_bits[21]	auto[0]	auto[1]	243196	1			T32	2079		T33	28		T11	1981
bins_for_gpio_bits[21]	auto[1]	auto[0]	243544	1			T32	2091		T33	28		T11	1992
bins_for_gpio_bits[21]	auto[1]	auto[1]	5108702	1			T32	34293		T33	137		T1	12
bins_for_gpio_bits[22]	auto[0]	auto[0]	8286086	1			T32	69680		T33	391		T1	17
bins_for_gpio_bits[22]	auto[0]	auto[1]	242148	1			T32	2068		T33	21		T11	2006
bins_for_gpio_bits[22]	auto[1]	auto[0]	242505	1			T32	2074		T33	22		T1	1
bins_for_gpio_bits[22]	auto[1]	auto[1]	5102381	1			T32	34461		T33	119		T1	26
bins_for_gpio_bits[23]	auto[0]	auto[0]	8298728	1			T32	69289		T33	342		T1	25
bins_for_gpio_bits[23]	auto[0]	auto[1]	243075	1			T32	2114		T33	25		T11	2014
bins_for_gpio_bits[23]	auto[1]	auto[0]	243372	1			T32	2120		T33	25		T11	2023
bins_for_gpio_bits[23]	auto[1]	auto[1]	5087945	1			T32	34760		T33	161		T1	19
bins_for_gpio_bits[24]	auto[0]	auto[0]	8282472	1			T32	69484		T33	360		T1	30
bins_for_gpio_bits[24]	auto[0]	auto[1]	242693	1			T32	2102		T33	27		T11	1990
bins_for_gpio_bits[24]	auto[1]	auto[0]	243040	1			T32	2113		T33	27		T1	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	5104915	1			T32	34584		T33	139		T1	13
bins_for_gpio_bits[25]	auto[0]	auto[0]	8283489	1			T32	69285		T33	366		T1	14
bins_for_gpio_bits[25]	auto[0]	auto[1]	243054	1			T32	2094		T33	24		T11	1990
bins_for_gpio_bits[25]	auto[1]	auto[0]	243379	1			T32	2102		T33	24		T11	1995
bins_for_gpio_bits[25]	auto[1]	auto[1]	5103198	1			T32	34802		T33	139		T1	30
bins_for_gpio_bits[26]	auto[0]	auto[0]	8286568	1			T32	69619		T33	374		T1	28
bins_for_gpio_bits[26]	auto[0]	auto[1]	243141	1			T32	2114		T33	24		T11	2010
bins_for_gpio_bits[26]	auto[1]	auto[0]	243540	1			T32	2119		T33	24		T11	2016
bins_for_gpio_bits[26]	auto[1]	auto[1]	5099871	1			T32	34431		T33	131		T1	16
bins_for_gpio_bits[27]	auto[0]	auto[0]	8284571	1			T32	69362		T33	359		T1	32
bins_for_gpio_bits[27]	auto[0]	auto[1]	242564	1			T32	2100		T33	28		T11	2016
bins_for_gpio_bits[27]	auto[1]	auto[0]	242890	1			T32	2108		T33	28		T1	1
bins_for_gpio_bits[27]	auto[1]	auto[1]	5103095	1			T32	34713		T33	138		T1	11
bins_for_gpio_bits[28]	auto[0]	auto[0]	8280802	1			T32	69213		T33	376		T1	14
bins_for_gpio_bits[28]	auto[0]	auto[1]	242841	1			T32	2147		T33	27		T11	1976
bins_for_gpio_bits[28]	auto[1]	auto[0]	243202	1			T32	2157		T33	28		T11	1981
bins_for_gpio_bits[28]	auto[1]	auto[1]	5106275	1			T32	34766		T33	122		T1	30
bins_for_gpio_bits[29]	auto[0]	auto[0]	8281048	1			T32	69420		T33	385		T1	20
bins_for_gpio_bits[29]	auto[0]	auto[1]	242522	1			T32	2113		T33	24		T11	1981
bins_for_gpio_bits[29]	auto[1]	auto[0]	242857	1			T32	2123		T33	24		T1	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	5106693	1			T32	34627		T33	120		T1	23
bins_for_gpio_bits[30]	auto[0]	auto[0]	8283832	1			T32	69315		T33	376		T1	37
bins_for_gpio_bits[30]	auto[0]	auto[1]	243638	1			T32	2096		T33	24		T11	2021
bins_for_gpio_bits[30]	auto[1]	auto[0]	244002	1			T32	2101		T33	24		T1	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	5101648	1			T32	34771		T33	129		T1	6
bins_for_gpio_bits[31]	auto[0]	auto[0]	8283955	1			T32	69246		T33	351		T1	29
bins_for_gpio_bits[31]	auto[0]	auto[1]	242739	1			T32	2175		T33	24		T11	1960
bins_for_gpio_bits[31]	auto[1]	auto[0]	243018	1			T32	2184		T33	24		T11	1966
bins_for_gpio_bits[31]	auto[1]	auto[1]	5103408	1			T32	34678		T33	154		T1	15