Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8188148 |
1 |
|
|
T32 |
59364 |
|
T33 |
341 |
|
T1 |
19 |
| auto[1] |
5876824 |
1 |
|
|
T32 |
48186 |
|
T1 |
10 |
|
T11 |
39940 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13314777 |
1 |
|
|
T32 |
101246 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
750195 |
1 |
|
|
T32 |
6304 |
|
T11 |
5305 |
|
T12 |
1454 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8172593 |
1 |
|
|
T32 |
59445 |
|
T33 |
341 |
|
T1 |
26 |
| auto[1] |
5892379 |
1 |
|
|
T32 |
48105 |
|
T1 |
3 |
|
T11 |
40859 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2582580 |
1 |
|
|
T32 |
20968 |
|
T11 |
18477 |
|
T12 |
4475 |
| auto[1] |
auto[0] |
auto[1] |
377266 |
1 |
|
|
T32 |
3156 |
|
T11 |
2803 |
|
T12 |
755 |
| auto[1] |
auto[1] |
auto[0] |
2559604 |
1 |
|
|
T32 |
20833 |
|
T1 |
3 |
|
T11 |
17077 |
| auto[1] |
auto[1] |
auto[1] |
372929 |
1 |
|
|
T32 |
3148 |
|
T11 |
2502 |
|
T12 |
699 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8180792 |
1 |
|
|
T32 |
57220 |
|
T33 |
341 |
|
T1 |
19 |
| auto[1] |
5884180 |
1 |
|
|
T32 |
50330 |
|
T1 |
10 |
|
T11 |
41907 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13314777 |
1 |
|
|
T32 |
101283 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
750195 |
1 |
|
|
T32 |
6267 |
|
T11 |
5541 |
|
T12 |
1697 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8174704 |
1 |
|
|
T32 |
59925 |
|
T33 |
341 |
|
T1 |
22 |
| auto[1] |
5890268 |
1 |
|
|
T32 |
47625 |
|
T1 |
7 |
|
T11 |
42467 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2574537 |
1 |
|
|
T32 |
19090 |
|
T1 |
4 |
|
T11 |
18952 |
| auto[1] |
auto[0] |
auto[1] |
376377 |
1 |
|
|
T32 |
2902 |
|
T11 |
2808 |
|
T12 |
810 |
| auto[1] |
auto[1] |
auto[0] |
2565536 |
1 |
|
|
T32 |
22268 |
|
T1 |
3 |
|
T11 |
17974 |
| auto[1] |
auto[1] |
auto[1] |
373818 |
1 |
|
|
T32 |
3365 |
|
T11 |
2733 |
|
T12 |
887 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8207822 |
1 |
|
|
T32 |
60740 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5857150 |
1 |
|
|
T32 |
46810 |
|
T1 |
6 |
|
T11 |
42069 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13317279 |
1 |
|
|
T32 |
101619 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
747693 |
1 |
|
|
T32 |
5931 |
|
T11 |
5502 |
|
T12 |
1543 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8192555 |
1 |
|
|
T32 |
61794 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5872417 |
1 |
|
|
T32 |
45756 |
|
T1 |
4 |
|
T11 |
42839 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2585476 |
1 |
|
|
T32 |
19853 |
|
T1 |
4 |
|
T11 |
18310 |
| auto[1] |
auto[0] |
auto[1] |
377744 |
1 |
|
|
T32 |
2938 |
|
T11 |
2628 |
|
T12 |
796 |
| auto[1] |
auto[1] |
auto[0] |
2539248 |
1 |
|
|
T32 |
19972 |
|
T11 |
19027 |
|
T12 |
4254 |
| auto[1] |
auto[1] |
auto[1] |
369949 |
1 |
|
|
T32 |
2993 |
|
T11 |
2874 |
|
T12 |
747 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8178389 |
1 |
|
|
T32 |
60534 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5886583 |
1 |
|
|
T32 |
47016 |
|
T1 |
4 |
|
T11 |
39902 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13315973 |
1 |
|
|
T32 |
101470 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
748999 |
1 |
|
|
T32 |
6080 |
|
T11 |
4699 |
|
T12 |
1586 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8181652 |
1 |
|
|
T32 |
59914 |
|
T33 |
341 |
|
T1 |
26 |
| auto[1] |
5883320 |
1 |
|
|
T32 |
47636 |
|
T1 |
3 |
|
T11 |
37695 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2582323 |
1 |
|
|
T32 |
21364 |
|
T1 |
3 |
|
T11 |
16783 |
| auto[1] |
auto[0] |
auto[1] |
376348 |
1 |
|
|
T32 |
3087 |
|
T11 |
2425 |
|
T12 |
714 |
| auto[1] |
auto[1] |
auto[0] |
2551998 |
1 |
|
|
T32 |
20192 |
|
T11 |
16213 |
|
T12 |
4765 |
| auto[1] |
auto[1] |
auto[1] |
372651 |
1 |
|
|
T32 |
2993 |
|
T11 |
2274 |
|
T12 |
872 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8169797 |
1 |
|
|
T32 |
60557 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5895175 |
1 |
|
|
T32 |
46993 |
|
T1 |
4 |
|
T11 |
42220 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13312707 |
1 |
|
|
T32 |
100997 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
752265 |
1 |
|
|
T32 |
6553 |
|
T11 |
5107 |
|
T12 |
1568 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8167547 |
1 |
|
|
T32 |
58033 |
|
T33 |
341 |
|
T1 |
26 |
| auto[1] |
5897425 |
1 |
|
|
T32 |
49517 |
|
T1 |
3 |
|
T11 |
40748 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2575504 |
1 |
|
|
T32 |
21902 |
|
T1 |
3 |
|
T11 |
16858 |
| auto[1] |
auto[0] |
auto[1] |
376134 |
1 |
|
|
T32 |
3323 |
|
T11 |
2309 |
|
T12 |
797 |
| auto[1] |
auto[1] |
auto[0] |
2569656 |
1 |
|
|
T32 |
21062 |
|
T11 |
18783 |
|
T12 |
4700 |
| auto[1] |
auto[1] |
auto[1] |
376131 |
1 |
|
|
T32 |
3230 |
|
T11 |
2798 |
|
T12 |
771 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8153617 |
1 |
|
|
T32 |
60047 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5911355 |
1 |
|
|
T32 |
47503 |
|
T1 |
6 |
|
T11 |
41120 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13315362 |
1 |
|
|
T32 |
101434 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
749610 |
1 |
|
|
T32 |
6116 |
|
T11 |
5232 |
|
T12 |
1522 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8168107 |
1 |
|
|
T32 |
59885 |
|
T33 |
341 |
|
T1 |
22 |
| auto[1] |
5896865 |
1 |
|
|
T32 |
47665 |
|
T1 |
7 |
|
T11 |
40550 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2559547 |
1 |
|
|
T32 |
20840 |
|
T1 |
4 |
|
T11 |
17414 |
| auto[1] |
auto[0] |
auto[1] |
372547 |
1 |
|
|
T32 |
2991 |
|
T11 |
2484 |
|
T12 |
797 |
| auto[1] |
auto[1] |
auto[0] |
2587708 |
1 |
|
|
T32 |
20709 |
|
T1 |
3 |
|
T11 |
17904 |
| auto[1] |
auto[1] |
auto[1] |
377063 |
1 |
|
|
T32 |
3125 |
|
T11 |
2748 |
|
T12 |
725 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8168024 |
1 |
|
|
T32 |
61293 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5896948 |
1 |
|
|
T32 |
46257 |
|
T1 |
6 |
|
T11 |
40083 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13314729 |
1 |
|
|
T32 |
101690 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
750243 |
1 |
|
|
T32 |
5860 |
|
T11 |
5344 |
|
T12 |
1596 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8173833 |
1 |
|
|
T32 |
61793 |
|
T33 |
341 |
|
T1 |
26 |
| auto[1] |
5891139 |
1 |
|
|
T32 |
45757 |
|
T1 |
3 |
|
T11 |
41471 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2557940 |
1 |
|
|
T32 |
20567 |
|
T11 |
18205 |
|
T12 |
4289 |
| auto[1] |
auto[0] |
auto[1] |
372946 |
1 |
|
|
T32 |
2953 |
|
T11 |
2724 |
|
T12 |
731 |
| auto[1] |
auto[1] |
auto[0] |
2582956 |
1 |
|
|
T32 |
19330 |
|
T1 |
3 |
|
T11 |
17922 |
| auto[1] |
auto[1] |
auto[1] |
377297 |
1 |
|
|
T32 |
2907 |
|
T11 |
2620 |
|
T12 |
865 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8201646 |
1 |
|
|
T32 |
60123 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5863326 |
1 |
|
|
T32 |
47427 |
|
T1 |
6 |
|
T11 |
41480 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13319664 |
1 |
|
|
T32 |
101617 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
745308 |
1 |
|
|
T32 |
5933 |
|
T11 |
5028 |
|
T12 |
1587 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8205980 |
1 |
|
|
T32 |
62075 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5858992 |
1 |
|
|
T32 |
45475 |
|
T1 |
4 |
|
T11 |
39710 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2566356 |
1 |
|
|
T32 |
20248 |
|
T1 |
4 |
|
T11 |
16930 |
| auto[1] |
auto[0] |
auto[1] |
373422 |
1 |
|
|
T32 |
3048 |
|
T11 |
2348 |
|
T12 |
742 |
| auto[1] |
auto[1] |
auto[0] |
2547328 |
1 |
|
|
T32 |
19294 |
|
T11 |
17752 |
|
T12 |
4821 |
| auto[1] |
auto[1] |
auto[1] |
371886 |
1 |
|
|
T32 |
2885 |
|
T11 |
2680 |
|
T12 |
845 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8183350 |
1 |
|
|
T32 |
60677 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5881622 |
1 |
|
|
T32 |
46873 |
|
T1 |
4 |
|
T11 |
41757 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13314582 |
1 |
|
|
T32 |
101296 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
750390 |
1 |
|
|
T32 |
6254 |
|
T11 |
5235 |
|
T12 |
1510 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8175433 |
1 |
|
|
T32 |
59525 |
|
T33 |
341 |
|
T1 |
22 |
| auto[1] |
5889539 |
1 |
|
|
T32 |
48025 |
|
T1 |
7 |
|
T11 |
41368 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2571998 |
1 |
|
|
T32 |
21240 |
|
T1 |
7 |
|
T11 |
17516 |
| auto[1] |
auto[0] |
auto[1] |
375153 |
1 |
|
|
T32 |
3158 |
|
T11 |
2536 |
|
T12 |
674 |
| auto[1] |
auto[1] |
auto[0] |
2567151 |
1 |
|
|
T32 |
20531 |
|
T11 |
18617 |
|
T12 |
4841 |
| auto[1] |
auto[1] |
auto[1] |
375237 |
1 |
|
|
T32 |
3096 |
|
T11 |
2699 |
|
T12 |
836 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8179308 |
1 |
|
|
T32 |
61044 |
|
T33 |
341 |
|
T1 |
19 |
| auto[1] |
5885664 |
1 |
|
|
T32 |
46506 |
|
T1 |
10 |
|
T11 |
41894 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13315445 |
1 |
|
|
T32 |
101451 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
749527 |
1 |
|
|
T32 |
6099 |
|
T11 |
5368 |
|
T12 |
1359 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8173573 |
1 |
|
|
T32 |
60131 |
|
T33 |
341 |
|
T1 |
22 |
| auto[1] |
5891399 |
1 |
|
|
T32 |
47419 |
|
T1 |
7 |
|
T11 |
41884 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2572433 |
1 |
|
|
T32 |
20802 |
|
T1 |
4 |
|
T11 |
17699 |
| auto[1] |
auto[0] |
auto[1] |
375262 |
1 |
|
|
T32 |
2992 |
|
T11 |
2511 |
|
T12 |
726 |
| auto[1] |
auto[1] |
auto[0] |
2569439 |
1 |
|
|
T32 |
20518 |
|
T1 |
3 |
|
T11 |
18817 |
| auto[1] |
auto[1] |
auto[1] |
374265 |
1 |
|
|
T32 |
3107 |
|
T11 |
2857 |
|
T12 |
633 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8169889 |
1 |
|
|
T32 |
61420 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5895083 |
1 |
|
|
T32 |
46130 |
|
T1 |
6 |
|
T11 |
41490 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13317965 |
1 |
|
|
T32 |
101704 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
747007 |
1 |
|
|
T32 |
5846 |
|
T11 |
5109 |
|
T12 |
1315 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8195503 |
1 |
|
|
T32 |
61131 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
5869469 |
1 |
|
|
T32 |
46419 |
|
T11 |
39568 |
|
T12 |
9566 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2562183 |
1 |
|
|
T32 |
21322 |
|
T11 |
16936 |
|
T12 |
4214 |
| auto[1] |
auto[0] |
auto[1] |
372982 |
1 |
|
|
T32 |
3093 |
|
T11 |
2528 |
|
T12 |
677 |
| auto[1] |
auto[1] |
auto[0] |
2560279 |
1 |
|
|
T32 |
19251 |
|
T11 |
17523 |
|
T12 |
4037 |
| auto[1] |
auto[1] |
auto[1] |
374025 |
1 |
|
|
T32 |
2753 |
|
T11 |
2581 |
|
T12 |
638 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8133569 |
1 |
|
|
T32 |
62853 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5931403 |
1 |
|
|
T32 |
44697 |
|
T1 |
6 |
|
T11 |
39430 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13316230 |
1 |
|
|
T32 |
101320 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
748742 |
1 |
|
|
T32 |
6230 |
|
T11 |
5236 |
|
T12 |
1522 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8178329 |
1 |
|
|
T32 |
59565 |
|
T33 |
341 |
|
T1 |
22 |
| auto[1] |
5886643 |
1 |
|
|
T32 |
47985 |
|
T1 |
7 |
|
T11 |
40874 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2554131 |
1 |
|
|
T32 |
22459 |
|
T1 |
4 |
|
T11 |
17636 |
| auto[1] |
auto[0] |
auto[1] |
372026 |
1 |
|
|
T32 |
3450 |
|
T11 |
2513 |
|
T12 |
662 |
| auto[1] |
auto[1] |
auto[0] |
2583770 |
1 |
|
|
T32 |
19296 |
|
T1 |
3 |
|
T11 |
18002 |
| auto[1] |
auto[1] |
auto[1] |
376716 |
1 |
|
|
T32 |
2780 |
|
T11 |
2723 |
|
T12 |
860 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8201134 |
1 |
|
|
T32 |
62441 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5863838 |
1 |
|
|
T32 |
45109 |
|
T1 |
6 |
|
T11 |
41708 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13312848 |
1 |
|
|
T32 |
101555 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
752124 |
1 |
|
|
T32 |
5995 |
|
T11 |
5302 |
|
T12 |
1374 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8166295 |
1 |
|
|
T32 |
61503 |
|
T33 |
341 |
|
T1 |
26 |
| auto[1] |
5898677 |
1 |
|
|
T32 |
46047 |
|
T1 |
3 |
|
T11 |
41344 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2580951 |
1 |
|
|
T32 |
21219 |
|
T11 |
17691 |
|
T12 |
4120 |
| auto[1] |
auto[0] |
auto[1] |
377130 |
1 |
|
|
T32 |
3165 |
|
T11 |
2569 |
|
T12 |
649 |
| auto[1] |
auto[1] |
auto[0] |
2565602 |
1 |
|
|
T32 |
18833 |
|
T1 |
3 |
|
T11 |
18351 |
| auto[1] |
auto[1] |
auto[1] |
374994 |
1 |
|
|
T32 |
2830 |
|
T11 |
2733 |
|
T12 |
725 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8171040 |
1 |
|
|
T32 |
62039 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5893932 |
1 |
|
|
T32 |
45511 |
|
T1 |
4 |
|
T11 |
40463 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13313979 |
1 |
|
|
T32 |
101642 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
750993 |
1 |
|
|
T32 |
5908 |
|
T11 |
5365 |
|
T12 |
1388 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8165624 |
1 |
|
|
T32 |
61120 |
|
T33 |
341 |
|
T1 |
26 |
| auto[1] |
5899348 |
1 |
|
|
T32 |
46430 |
|
T1 |
3 |
|
T11 |
42120 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2578367 |
1 |
|
|
T32 |
20999 |
|
T1 |
3 |
|
T11 |
18439 |
| auto[1] |
auto[0] |
auto[1] |
376653 |
1 |
|
|
T32 |
2994 |
|
T11 |
2691 |
|
T12 |
689 |
| auto[1] |
auto[1] |
auto[0] |
2569988 |
1 |
|
|
T32 |
19523 |
|
T11 |
18316 |
|
T12 |
4077 |
| auto[1] |
auto[1] |
auto[1] |
374340 |
1 |
|
|
T32 |
2914 |
|
T11 |
2674 |
|
T12 |
699 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8189136 |
1 |
|
|
T32 |
59407 |
|
T33 |
341 |
|
T1 |
19 |
| auto[1] |
5875836 |
1 |
|
|
T32 |
48143 |
|
T1 |
10 |
|
T11 |
40645 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13318722 |
1 |
|
|
T32 |
101681 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
746250 |
1 |
|
|
T32 |
5869 |
|
T11 |
5570 |
|
T12 |
1595 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8203402 |
1 |
|
|
T32 |
61490 |
|
T33 |
341 |
|
T1 |
22 |
| auto[1] |
5861570 |
1 |
|
|
T32 |
46060 |
|
T1 |
7 |
|
T11 |
42138 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2573710 |
1 |
|
|
T32 |
20421 |
|
T1 |
4 |
|
T11 |
18091 |
| auto[1] |
auto[0] |
auto[1] |
376478 |
1 |
|
|
T32 |
2952 |
|
T11 |
2820 |
|
T12 |
840 |
| auto[1] |
auto[1] |
auto[0] |
2541610 |
1 |
|
|
T32 |
19770 |
|
T1 |
3 |
|
T11 |
18477 |
| auto[1] |
auto[1] |
auto[1] |
369772 |
1 |
|
|
T32 |
2917 |
|
T11 |
2750 |
|
T12 |
755 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8187198 |
1 |
|
|
T32 |
60610 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
5877774 |
1 |
|
|
T32 |
46940 |
|
T11 |
41397 |
|
T12 |
10853 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13321096 |
1 |
|
|
T32 |
101538 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
743876 |
1 |
|
|
T32 |
6012 |
|
T11 |
5278 |
|
T12 |
1631 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8216310 |
1 |
|
|
T32 |
61370 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5848662 |
1 |
|
|
T32 |
46180 |
|
T1 |
4 |
|
T11 |
40864 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2558742 |
1 |
|
|
T32 |
20124 |
|
T1 |
4 |
|
T11 |
18081 |
| auto[1] |
auto[0] |
auto[1] |
372983 |
1 |
|
|
T32 |
3069 |
|
T11 |
2722 |
|
T12 |
726 |
| auto[1] |
auto[1] |
auto[0] |
2546044 |
1 |
|
|
T32 |
20044 |
|
T11 |
17505 |
|
T12 |
4957 |
| auto[1] |
auto[1] |
auto[1] |
370893 |
1 |
|
|
T32 |
2943 |
|
T11 |
2556 |
|
T12 |
905 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8196019 |
1 |
|
|
T32 |
60780 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5868953 |
1 |
|
|
T32 |
46770 |
|
T1 |
6 |
|
T11 |
40442 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13319164 |
1 |
|
|
T32 |
101361 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
745808 |
1 |
|
|
T32 |
6189 |
|
T11 |
5177 |
|
T12 |
1573 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8199531 |
1 |
|
|
T32 |
60201 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
5865441 |
1 |
|
|
T32 |
47349 |
|
T11 |
40120 |
|
T12 |
10533 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2560626 |
1 |
|
|
T32 |
20602 |
|
T11 |
17681 |
|
T12 |
5053 |
| auto[1] |
auto[0] |
auto[1] |
373461 |
1 |
|
|
T32 |
3048 |
|
T11 |
2629 |
|
T12 |
891 |
| auto[1] |
auto[1] |
auto[0] |
2559007 |
1 |
|
|
T32 |
20558 |
|
T11 |
17262 |
|
T12 |
3907 |
| auto[1] |
auto[1] |
auto[1] |
372347 |
1 |
|
|
T32 |
3141 |
|
T11 |
2548 |
|
T12 |
682 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8188599 |
1 |
|
|
T32 |
59013 |
|
T33 |
341 |
|
T1 |
19 |
| auto[1] |
5876373 |
1 |
|
|
T32 |
48537 |
|
T1 |
10 |
|
T11 |
40125 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13317192 |
1 |
|
|
T32 |
101273 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
747780 |
1 |
|
|
T32 |
6277 |
|
T11 |
5174 |
|
T12 |
1579 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8187450 |
1 |
|
|
T32 |
59875 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5877522 |
1 |
|
|
T32 |
47675 |
|
T1 |
4 |
|
T11 |
40141 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2574337 |
1 |
|
|
T32 |
19900 |
|
T1 |
4 |
|
T11 |
18204 |
| auto[1] |
auto[0] |
auto[1] |
374291 |
1 |
|
|
T32 |
3029 |
|
T11 |
2709 |
|
T12 |
719 |
| auto[1] |
auto[1] |
auto[0] |
2555405 |
1 |
|
|
T32 |
21498 |
|
T11 |
16763 |
|
T12 |
4838 |
| auto[1] |
auto[1] |
auto[1] |
373489 |
1 |
|
|
T32 |
3248 |
|
T11 |
2465 |
|
T12 |
860 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8162531 |
1 |
|
|
T32 |
60242 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
5902441 |
1 |
|
|
T32 |
47308 |
|
T11 |
40581 |
|
T12 |
10390 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13314596 |
1 |
|
|
T32 |
101590 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
750376 |
1 |
|
|
T32 |
5960 |
|
T11 |
5228 |
|
T12 |
1556 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8178645 |
1 |
|
|
T32 |
61077 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5886327 |
1 |
|
|
T32 |
46473 |
|
T1 |
4 |
|
T11 |
41011 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2567738 |
1 |
|
|
T32 |
20396 |
|
T1 |
4 |
|
T11 |
17908 |
| auto[1] |
auto[0] |
auto[1] |
375964 |
1 |
|
|
T32 |
3069 |
|
T11 |
2513 |
|
T12 |
821 |
| auto[1] |
auto[1] |
auto[0] |
2568213 |
1 |
|
|
T32 |
20117 |
|
T11 |
17875 |
|
T12 |
4408 |
| auto[1] |
auto[1] |
auto[1] |
374412 |
1 |
|
|
T32 |
2891 |
|
T11 |
2715 |
|
T12 |
735 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8181944 |
1 |
|
|
T32 |
58696 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5883028 |
1 |
|
|
T32 |
48854 |
|
T1 |
4 |
|
T11 |
42296 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13317683 |
1 |
|
|
T32 |
101652 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
747289 |
1 |
|
|
T32 |
5898 |
|
T11 |
5132 |
|
T12 |
1671 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8206388 |
1 |
|
|
T32 |
61030 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5858584 |
1 |
|
|
T32 |
46520 |
|
T1 |
4 |
|
T11 |
40084 |