Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8184831 |
1 |
|
|
T32 |
61107 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5880141 |
1 |
|
|
T32 |
46443 |
|
T1 |
6 |
|
T11 |
41282 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13313401 |
1 |
|
|
T32 |
101470 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
751571 |
1 |
|
|
T32 |
6080 |
|
T11 |
5457 |
|
T12 |
1544 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8170795 |
1 |
|
|
T32 |
61015 |
|
T33 |
341 |
|
T1 |
22 |
| auto[1] |
5894177 |
1 |
|
|
T32 |
46535 |
|
T1 |
7 |
|
T11 |
42168 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2582024 |
1 |
|
|
T32 |
19969 |
|
T1 |
4 |
|
T11 |
18637 |
| auto[1] |
auto[0] |
auto[1] |
379354 |
1 |
|
|
T32 |
2980 |
|
T11 |
2743 |
|
T12 |
831 |
| auto[1] |
auto[1] |
auto[0] |
2560582 |
1 |
|
|
T32 |
20486 |
|
T1 |
3 |
|
T11 |
18074 |
| auto[1] |
auto[1] |
auto[1] |
372217 |
1 |
|
|
T32 |
3100 |
|
T11 |
2714 |
|
T12 |
713 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |