Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8140289 |
1 |
|
|
T32 |
60401 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
5924683 |
1 |
|
|
T32 |
47149 |
|
T11 |
40973 |
|
T12 |
10335 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13309661 |
1 |
|
|
T32 |
101474 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
755311 |
1 |
|
|
T32 |
6076 |
|
T11 |
4849 |
|
T12 |
1540 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8138648 |
1 |
|
|
T32 |
59649 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
5926324 |
1 |
|
|
T32 |
47901 |
|
T11 |
38701 |
|
T12 |
10539 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2565002 |
1 |
|
|
T32 |
20948 |
|
T11 |
16321 |
|
T12 |
4201 |
| auto[1] |
auto[0] |
auto[1] |
374358 |
1 |
|
|
T32 |
3076 |
|
T11 |
2281 |
|
T12 |
672 |
| auto[1] |
auto[1] |
auto[0] |
2606011 |
1 |
|
|
T32 |
20877 |
|
T11 |
17531 |
|
T12 |
4798 |
| auto[1] |
auto[1] |
auto[1] |
380953 |
1 |
|
|
T32 |
3000 |
|
T11 |
2568 |
|
T12 |
868 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |