Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8174852 |
1 |
|
|
T32 |
60572 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
5890120 |
1 |
|
|
T32 |
46978 |
|
T11 |
41017 |
|
T12 |
10551 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13312748 |
1 |
|
|
T32 |
101449 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
752224 |
1 |
|
|
T32 |
6101 |
|
T11 |
5287 |
|
T12 |
1438 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8158240 |
1 |
|
|
T32 |
60371 |
|
T33 |
341 |
|
T1 |
26 |
| auto[1] |
5906732 |
1 |
|
|
T32 |
47179 |
|
T1 |
3 |
|
T11 |
40540 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2578680 |
1 |
|
|
T32 |
20089 |
|
T1 |
3 |
|
T11 |
17629 |
| auto[1] |
auto[0] |
auto[1] |
376986 |
1 |
|
|
T32 |
3012 |
|
T11 |
2672 |
|
T12 |
763 |
| auto[1] |
auto[1] |
auto[0] |
2575828 |
1 |
|
|
T32 |
20989 |
|
T11 |
17624 |
|
T12 |
4130 |
| auto[1] |
auto[1] |
auto[1] |
375238 |
1 |
|
|
T32 |
3089 |
|
T11 |
2615 |
|
T12 |
675 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |