Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8191227 |
1 |
|
|
T32 |
62712 |
|
T33 |
341 |
|
T1 |
23 |
| auto[1] |
5873745 |
1 |
|
|
T32 |
44838 |
|
T1 |
6 |
|
T11 |
40564 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13317722 |
1 |
|
|
T32 |
101904 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
747250 |
1 |
|
|
T32 |
5646 |
|
T11 |
5252 |
|
T12 |
1417 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8190429 |
1 |
|
|
T32 |
62611 |
|
T33 |
341 |
|
T1 |
26 |
| auto[1] |
5874543 |
1 |
|
|
T32 |
44939 |
|
T1 |
3 |
|
T11 |
40757 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2579706 |
1 |
|
|
T32 |
19783 |
|
T11 |
18711 |
|
T12 |
4900 |
| auto[1] |
auto[0] |
auto[1] |
375896 |
1 |
|
|
T32 |
2710 |
|
T11 |
2773 |
|
T12 |
767 |
| auto[1] |
auto[1] |
auto[0] |
2547587 |
1 |
|
|
T32 |
19510 |
|
T1 |
3 |
|
T11 |
16794 |
| auto[1] |
auto[1] |
auto[1] |
371354 |
1 |
|
|
T32 |
2936 |
|
T11 |
2479 |
|
T12 |
650 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |