Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8179551 |
1 |
|
|
T32 |
60366 |
|
T33 |
341 |
|
T1 |
19 |
| auto[1] |
5885421 |
1 |
|
|
T32 |
47184 |
|
T1 |
10 |
|
T11 |
41029 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13315155 |
1 |
|
|
T32 |
101292 |
|
T33 |
341 |
|
T1 |
29 |
| auto[1] |
749817 |
1 |
|
|
T32 |
6258 |
|
T11 |
5001 |
|
T12 |
1691 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8173731 |
1 |
|
|
T32 |
59718 |
|
T33 |
341 |
|
T1 |
25 |
| auto[1] |
5891241 |
1 |
|
|
T32 |
47832 |
|
T1 |
4 |
|
T11 |
39795 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2579036 |
1 |
|
|
T32 |
21003 |
|
T1 |
4 |
|
T11 |
17858 |
| auto[1] |
auto[0] |
auto[1] |
376790 |
1 |
|
|
T32 |
3253 |
|
T11 |
2494 |
|
T12 |
833 |
| auto[1] |
auto[1] |
auto[0] |
2562388 |
1 |
|
|
T32 |
20571 |
|
T11 |
16936 |
|
T12 |
4659 |
| auto[1] |
auto[1] |
auto[1] |
373027 |
1 |
|
|
T32 |
3005 |
|
T11 |
2507 |
|
T12 |
858 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |